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Kumar Gala243be8e2011-01-19 03:05:26 -06001/*
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +00002 * Copyright 2011-2012 Freescale Semiconductor, Inc.
Kumar Gala243be8e2011-01-19 03:05:26 -06003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala243be8e2011-01-19 03:05:26 -06005 */
6
7#ifndef _ASM_MPC85xx_CONFIG_H_
8#define _ASM_MPC85xx_CONFIG_H_
9
10/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
11
York Sun2a5fcb82012-10-28 08:12:54 +000012/*
13 * This macro should be removed when we no longer care about backwards
14 * compatibility with older operating systems.
15 */
16#define CONFIG_PPC_SPINTABLE_COMPATIBLE
17
York Sun34e026f2014-03-27 17:54:47 -070018#include <fsl_ddrc_version.h>
19#define CONFIG_SYS_FSL_DDR_BE
York Sun57495e42012-10-08 07:44:22 +000020
Prabhakar Kushwaha1b4175d2014-01-18 12:28:30 +053021/* IP endianness */
22#define CONFIG_SYS_FSL_IFC_BE
Ruchika Gupta028dbb82014-09-09 11:50:31 +053023#define CONFIG_SYS_FSL_SEC_BE
gaurav ranaa2e225e2015-02-27 09:43:49 +053024#define CONFIG_SYS_FSL_SFP_BE
gaurav ranae04916a2015-02-27 09:46:17 +053025#define CONFIG_SYS_FSL_SEC_MON_BE
Prabhakar Kushwaha1b4175d2014-01-18 12:28:30 +053026
Kumar Gala243be8e2011-01-19 03:05:26 -060027/* Number of TLB CAM entries we have on FSL Book-E chips */
28#if defined(CONFIG_E500MC)
29#define CONFIG_SYS_NUM_TLBCAMS 64
30#elif defined(CONFIG_E500)
31#define CONFIG_SYS_NUM_TLBCAMS 16
32#endif
33
York Sun24ad75a2016-11-16 11:06:47 -080034#if defined(CONFIG_ARCH_MPC8536)
Kumar Gala243be8e2011-01-19 03:05:26 -060035#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +000036#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
Kumar Gala243be8e2011-01-19 03:05:26 -060037#define CONFIG_SYS_FSL_SEC_COMPAT 2
York Sun9855b3b2014-05-23 13:15:00 -070038#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -070039#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -060040
York Sun7f825212016-11-16 11:13:06 -080041#elif defined(CONFIG_ARCH_MPC8540)
Kumar Gala243be8e2011-01-19 03:05:26 -060042#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -070043#define CONFIG_SYS_FSL_DDRC_GEN1
Kumar Gala243be8e2011-01-19 03:05:26 -060044
York Sun3aff3082016-11-16 11:18:31 -080045#elif defined(CONFIG_ARCH_MPC8541)
Kumar Gala243be8e2011-01-19 03:05:26 -060046#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -070047#define CONFIG_SYS_FSL_DDRC_GEN1
Kumar Gala243be8e2011-01-19 03:05:26 -060048#define CONFIG_SYS_FSL_SEC_COMPAT 2
49
York Sun25cb74b2016-11-15 13:57:15 -080050#elif defined(CONFIG_ARCH_MPC8544)
Kumar Gala243be8e2011-01-19 03:05:26 -060051#define CONFIG_SYS_FSL_NUM_LAWS 10
York Sun5614e712013-09-30 09:22:09 -070052#define CONFIG_SYS_FSL_DDRC_GEN2
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +000053#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala243be8e2011-01-19 03:05:26 -060054#define CONFIG_SYS_FSL_SEC_COMPAT 2
York Sun954a1a42013-08-20 15:09:43 -070055#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -060056
York Sun281ed4c2016-11-15 13:52:34 -080057#elif defined(CONFIG_ARCH_MPC8548)
Kumar Gala243be8e2011-01-19 03:05:26 -060058#define CONFIG_SYS_FSL_NUM_LAWS 10
York Sun5614e712013-09-30 09:22:09 -070059#define CONFIG_SYS_FSL_DDRC_GEN2
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +000060#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala243be8e2011-01-19 03:05:26 -060061#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala5ace2992011-09-16 09:54:30 -050062#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
Kumar Gala2b3a1cd2011-10-03 08:37:57 -050063#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
chenhui zhaoaada81d2011-10-03 08:38:50 -050064#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
Liu Gang7d67ed52012-03-08 00:33:14 +000065#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
66#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
67#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
68#define CONFIG_SYS_FSL_RMU
69#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun954a1a42013-08-20 15:09:43 -070070#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan9c3f77e2013-08-16 15:10:37 +080071#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
72#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
Kumar Gala243be8e2011-01-19 03:05:26 -060073
York Sun3c3d8ab2016-11-16 11:23:23 -080074#elif defined(CONFIG_ARCH_MPC8555)
Kumar Gala243be8e2011-01-19 03:05:26 -060075#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -070076#define CONFIG_SYS_FSL_DDRC_GEN1
Kumar Gala243be8e2011-01-19 03:05:26 -060077#define CONFIG_SYS_FSL_SEC_COMPAT 2
78
York Sun99d0a312016-11-16 11:26:45 -080079#elif defined(CONFIG_ARCH_MPC8560)
Kumar Gala243be8e2011-01-19 03:05:26 -060080#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -070081#define CONFIG_SYS_FSL_DDRC_GEN1
Kumar Gala243be8e2011-01-19 03:05:26 -060082
York Sund07c3842016-11-16 11:32:17 -080083#elif defined(CONFIG_ARCH_MPC8568)
Kumar Gala243be8e2011-01-19 03:05:26 -060084#define CONFIG_SYS_FSL_NUM_LAWS 10
York Sun5614e712013-09-30 09:22:09 -070085#define CONFIG_SYS_FSL_DDRC_GEN2
Kumar Gala243be8e2011-01-19 03:05:26 -060086#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galafdb4dad2011-01-31 23:09:25 -060087#define QE_MURAM_SIZE 0x10000UL
88#define MAX_QE_RISC 2
89#define QE_NUM_OF_SNUM 28
Liu Gang7d67ed52012-03-08 00:33:14 +000090#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
91#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
92#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
93#define CONFIG_SYS_FSL_RMU
94#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala243be8e2011-01-19 03:05:26 -060095
York Sun23b36a72016-11-16 11:34:52 -080096#elif defined(CONFIG_ARCH_MPC8569)
Kumar Gala243be8e2011-01-19 03:05:26 -060097#define CONFIG_SYS_FSL_NUM_LAWS 10
98#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galafdb4dad2011-01-31 23:09:25 -060099#define QE_MURAM_SIZE 0x20000UL
100#define MAX_QE_RISC 4
101#define QE_NUM_OF_SNUM 46
Liu Gang7d67ed52012-03-08 00:33:14 +0000102#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
103#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
104#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
105#define CONFIG_SYS_FSL_RMU
106#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun9855b3b2014-05-23 13:15:00 -0700107#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700108#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600109
York Sunc8f48472016-11-16 11:39:20 -0800110#elif defined(CONFIG_ARCH_MPC8572)
Kumar Gala243be8e2011-01-19 03:05:26 -0600111#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +0000112#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600113#define CONFIG_SYS_FSL_SEC_COMPAT 2
York Suneb0aff72011-01-25 21:51:27 -0800114#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sun91671912011-01-25 22:05:49 -0800115#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
York Sun9855b3b2014-05-23 13:15:00 -0700116#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700117#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600118
York Sun7d5f9f82016-11-16 13:08:52 -0800119#elif defined(CONFIG_ARCH_P1010)
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530120#define CONFIG_FSL_SDHC_V2_3
Kumar Gala243be8e2011-01-19 03:05:26 -0600121#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000122#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala243be8e2011-01-19 03:05:26 -0600123#define CONFIG_TSECV2
124#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530125#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
126#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530127#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Mingkai Hu362ee042013-05-16 10:18:13 +0800128#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
Kumar Gala8f290842011-05-20 00:39:21 -0500129#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530130#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal42aee642011-06-30 03:00:28 -0500131#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalfb855f42011-06-29 16:32:52 +0530132#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Shengzhou Liu424bf942013-08-15 09:31:47 +0800133#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
Poonam Aggrwalbc6bbd62011-07-07 20:36:47 +0530134#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
York Sun954a1a42013-08-20 15:09:43 -0700135#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800136#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
York Sun9855b3b2014-05-23 13:15:00 -0700137#define CONFIG_SYS_FSL_ERRATUM_A004508
Nikhil Badola11856912014-02-26 17:43:15 +0530138#define CONFIG_SYS_FSL_ERRATUM_A007075
Sriram Dash15a6d492016-08-17 11:47:53 +0530139#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
Suresh Gupta9c641a82014-02-26 14:29:12 +0530140#define CONFIG_SYS_FSL_ERRATUM_A006261
Nikhil Badola0dc78ff2014-11-21 17:25:21 +0530141#define CONFIG_SYS_FSL_ERRATUM_A004477
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800142#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
Haijun.Zhangf28bea02014-01-10 13:52:19 +0800143#define CONFIG_ESDHC_HC_BLK_ADDR
Kumar Gala243be8e2011-01-19 03:05:26 -0600144
Kumar Gala093cffb2011-02-05 13:45:07 -0600145/* P1011 is single core version of P1020 */
York Sun1cdd96f2016-11-16 15:54:15 -0800146#elif defined(CONFIG_ARCH_P1011)
Kumar Gala243be8e2011-01-19 03:05:26 -0600147#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000148#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600149#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000150#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600151#define CONFIG_SYS_FSL_SEC_COMPAT 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530152#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Kumar Gala093cffb2011-02-05 13:45:07 -0600153#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
154#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun9855b3b2014-05-23 13:15:00 -0700155#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700156#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600157
York Sun484fff62016-11-18 10:02:14 -0800158#elif defined(CONFIG_ARCH_P1020)
Kumar Gala243be8e2011-01-19 03:05:26 -0600159#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000160#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600161#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000162#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600163#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala093cffb2011-02-05 13:45:07 -0600164#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
165#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun9855b3b2014-05-23 13:15:00 -0700166#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700167#define CONFIG_SYS_FSL_ERRATUM_A005125
ramneek mehresh80ba6a62014-05-13 15:36:07 +0530168#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
ramneek mehreshf1810d82013-10-18 17:40:17 +0530169#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
ramneek mehresh80ba6a62014-05-13 15:36:07 +0530170#endif
Kumar Gala243be8e2011-01-19 03:05:26 -0600171
York Suna9907992016-11-18 10:59:02 -0800172#elif defined(CONFIG_ARCH_P1021)
Kumar Gala243be8e2011-01-19 03:05:26 -0600173#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000174#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600175#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000176#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600177#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala093cffb2011-02-05 13:45:07 -0600178#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
179#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600180#define QE_MURAM_SIZE 0x6000UL
181#define MAX_QE_RISC 1
182#define QE_NUM_OF_SNUM 28
York Sun9855b3b2014-05-23 13:15:00 -0700183#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700184#define CONFIG_SYS_FSL_ERRATUM_A005125
ramneek mehreshf1810d82013-10-18 17:40:17 +0530185#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Kumar Gala243be8e2011-01-19 03:05:26 -0600186
York Sunfeb9e252016-11-16 15:23:52 -0800187#elif defined(CONFIG_ARCH_P1022)
Kumar Gala243be8e2011-01-19 03:05:26 -0600188#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000189#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600190#define CONFIG_TSECV2
191#define CONFIG_SYS_FSL_SEC_COMPAT 2
Ying Zhang703f5682015-01-30 14:52:11 +0800192#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Jiang Yutang2d7534a2011-01-30 17:06:20 -0600193#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
194#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
195#define CONFIG_FSL_SATA_ERRATUM_A001
York Sun9855b3b2014-05-23 13:15:00 -0700196#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700197#define CONFIG_SYS_FSL_ERRATUM_A005125
Nikhil Badola0dc78ff2014-11-21 17:25:21 +0530198#define CONFIG_SYS_FSL_ERRATUM_A004477
Kumar Gala243be8e2011-01-19 03:05:26 -0600199
York Sun9bb1d6b2016-11-16 15:45:31 -0800200#elif defined(CONFIG_ARCH_P1023)
Roy Zang67a719d2011-02-03 22:14:19 -0600201#define CONFIG_SYS_FSL_NUM_LAWS 12
202#define CONFIG_SYS_FSL_SEC_COMPAT 4
203#define CONFIG_SYS_NUM_FMAN 1
204#define CONFIG_SYS_NUM_FM1_DTSEC 2
205#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530206#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Roy Zang67a719d2011-02-03 22:14:19 -0600207#define CONFIG_SYS_QMAN_NUM_PORTALS 3
208#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galac657d892011-02-04 00:43:34 -0600209#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala8f290842011-05-20 00:39:21 -0500210#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
York Sun9855b3b2014-05-23 13:15:00 -0700211#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700212#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800213#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
214#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Roy Zang67a719d2011-02-03 22:14:19 -0600215
Kumar Gala093cffb2011-02-05 13:45:07 -0600216/* P1024 is lower end variant of P1020 */
York Sun52b6f132016-11-18 11:00:57 -0800217#elif defined(CONFIG_ARCH_P1024)
Kumar Gala093cffb2011-02-05 13:45:07 -0600218#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000219#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala093cffb2011-02-05 13:45:07 -0600220#define CONFIG_TSECV2
221#define CONFIG_FSL_PCIE_DISABLE_ASPM
222#define CONFIG_SYS_FSL_SEC_COMPAT 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530223#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Kumar Gala093cffb2011-02-05 13:45:07 -0600224#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
225#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun9855b3b2014-05-23 13:15:00 -0700226#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700227#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala093cffb2011-02-05 13:45:07 -0600228
229/* P1025 is lower end variant of P1021 */
York Sun4167a672016-11-18 11:05:38 -0800230#elif defined(CONFIG_ARCH_P1025)
Kumar Gala093cffb2011-02-05 13:45:07 -0600231#define CONFIG_SYS_FSL_NUM_LAWS 12
Nikhil Badola1ff10a82015-05-21 09:07:53 +0530232#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000233#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala093cffb2011-02-05 13:45:07 -0600234#define CONFIG_TSECV2
235#define CONFIG_FSL_PCIE_DISABLE_ASPM
236#define CONFIG_SYS_FSL_SEC_COMPAT 2
237#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
238#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600239#define QE_MURAM_SIZE 0x6000UL
240#define MAX_QE_RISC 1
241#define QE_NUM_OF_SNUM 28
York Sun9855b3b2014-05-23 13:15:00 -0700242#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700243#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala093cffb2011-02-05 13:45:07 -0600244
York Sun45936372016-11-18 11:08:43 -0800245#elif defined(CONFIG_ARCH_P2020)
Kumar Gala243be8e2011-01-19 03:05:26 -0600246#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000247#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600248#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala6e7f0bc02011-01-26 01:43:15 -0600249#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala5103a032011-01-29 15:36:10 -0600250#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Liu Gang7d67ed52012-03-08 00:33:14 +0000251#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
252#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
253#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
254#define CONFIG_SYS_FSL_RMU
255#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun9855b3b2014-05-23 13:15:00 -0700256#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700257#define CONFIG_SYS_FSL_ERRATUM_A005125
Nikhil Badola0dc78ff2014-11-21 17:25:21 +0530258#define CONFIG_SYS_FSL_ERRATUM_A004477
ramneek mehreshf1810d82013-10-18 17:40:17 +0530259#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
York Sun9855b3b2014-05-23 13:15:00 -0700260
York Sunce040c82016-11-18 11:15:21 -0800261#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
York Sund1001e32012-10-08 07:44:15 +0000262#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700263#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala1f979872011-05-13 01:16:07 -0500264#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
265#define CONFIG_SYS_FSL_NUM_LAWS 32
266#define CONFIG_SYS_FSL_SEC_COMPAT 4
267#define CONFIG_SYS_NUM_FMAN 1
268#define CONFIG_SYS_NUM_FM1_DTSEC 5
269#define CONFIG_SYS_NUM_FM1_10GEC 1
270#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530271#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Kumar Gala1f979872011-05-13 01:16:07 -0500272#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
273#define CONFIG_SYS_FSL_TBCLK_DIV 32
274#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
275#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
276#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500277#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala1f979872011-05-13 01:16:07 -0500278#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun5e23ab02012-05-07 07:26:47 +0000279#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei99d7b0a2013-03-11 17:56:34 +0000280#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala43f082b2011-11-22 06:51:15 -0600281#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sune22be772013-03-25 07:30:11 +0000282#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun41085082011-11-20 10:01:35 -0800283#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000284#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
285#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
286#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000287#define CONFIG_SYS_FSL_ERRATUM_A004510
288#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
289#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
290#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000291#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi01180332012-10-25 12:40:00 +0000292#define CONFIG_SYS_FSL_ERRATUM_A004849
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800293#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Suresh Gupta9c641a82014-02-26 14:29:12 +0530294#define CONFIG_SYS_FSL_ERRATUM_A006261
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800295#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Kumar Gala1f979872011-05-13 01:16:07 -0500296
York Sun5e5fdd22016-11-18 11:20:40 -0800297#elif defined(CONFIG_ARCH_P3041)
York Sund1001e32012-10-08 07:44:15 +0000298#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700299#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Galab5c87532011-02-16 02:03:29 -0600300#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600301#define CONFIG_SYS_FSL_NUM_LAWS 32
302#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galafbee0f72011-01-25 12:42:32 -0600303#define CONFIG_SYS_NUM_FMAN 1
304#define CONFIG_SYS_NUM_FM1_DTSEC 5
305#define CONFIG_SYS_NUM_FM1_10GEC 1
306#define CONFIG_NUM_DDR_CONTROLLERS 1
York Sun34e026f2014-03-27 17:54:47 -0700307#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
Kumar Galac657d892011-02-04 00:43:34 -0600308#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600309#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala8f290842011-05-20 00:39:21 -0500310#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Roy Zang86221f02011-04-13 00:08:51 -0500311#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
312#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500313#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
ramneek mehreshf1810d82013-10-18 17:40:17 +0530314#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Lei Xu30009762011-04-19 15:28:41 +0800315#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun57125f22012-08-08 18:04:53 +0000316#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei99d7b0a2013-03-11 17:56:34 +0000317#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala43f082b2011-11-22 06:51:15 -0600318#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sune22be772013-03-25 07:30:11 +0000319#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun41085082011-11-20 10:01:35 -0800320#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000321#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
322#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
323#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000324#define CONFIG_SYS_FSL_ERRATUM_A004510
325#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
326#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
327#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000328#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi01180332012-10-25 12:40:00 +0000329#define CONFIG_SYS_FSL_ERRATUM_A004849
York Sund217a9a2013-06-25 11:37:49 -0700330#define CONFIG_SYS_FSL_ERRATUM_A005812
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800331#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Suresh Gupta9c641a82014-02-26 14:29:12 +0530332#define CONFIG_SYS_FSL_ERRATUM_A006261
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800333#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala243be8e2011-01-19 03:05:26 -0600334
York Sune71372c2016-11-18 11:24:40 -0800335#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
York Sund1001e32012-10-08 07:44:15 +0000336#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700337#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Galab5c87532011-02-16 02:03:29 -0600338#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Gala243be8e2011-01-19 03:05:26 -0600339#define CONFIG_SYS_FSL_NUM_LAWS 32
340#define CONFIG_SYS_FSL_SEC_COMPAT 4
341#define CONFIG_SYS_NUM_FMAN 2
342#define CONFIG_SYS_NUM_FM1_DTSEC 4
343#define CONFIG_SYS_NUM_FM2_DTSEC 4
344#define CONFIG_SYS_NUM_FM1_10GEC 1
345#define CONFIG_SYS_NUM_FM2_10GEC 1
346#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700347#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530348#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Kumar Galac657d892011-02-04 00:43:34 -0600349#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600350#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala8f290842011-05-20 00:39:21 -0500351#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Kumar Gala243be8e2011-01-19 03:05:26 -0600352#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
353#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sunfa8d23c2011-01-10 12:03:01 +0000354#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Gala243be8e2011-01-19 03:05:26 -0600355#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
356#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
357#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
Zang Roy-R619114e0be342012-09-18 09:50:08 +0000358#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
Kumar Gala243be8e2011-01-19 03:05:26 -0600359#define CONFIG_SYS_P4080_ERRATUM_CPU22
York Sun5e23ab02012-05-07 07:26:47 +0000360#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala243be8e2011-01-19 03:05:26 -0600361#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medvedf8af0b2010-08-31 22:57:38 -0500362#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabid90fdba2011-04-18 17:16:00 -0500363#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabida30b9f2011-04-01 13:19:36 -0500364#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Gala43f082b2011-11-22 06:51:15 -0600365#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun41085082011-11-20 10:01:35 -0800366#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000367#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
368#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
369#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
370#define CONFIG_SYS_FSL_RMU
371#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Scott Wood33eee332012-08-14 10:14:53 +0000372#define CONFIG_SYS_FSL_ERRATUM_A004510
373#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
374#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
Liu Gangd59c5572012-09-28 21:26:19 +0000375#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi01180332012-10-25 12:40:00 +0000376#define CONFIG_SYS_FSL_ERRATUM_A004849
Timur Tabid607b962012-11-01 08:20:23 +0000377#define CONFIG_SYS_FSL_ERRATUM_A004580
Yuanquan Chenc0a4e6b2012-11-26 23:49:45 +0000378#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
York Sund217a9a2013-06-25 11:37:49 -0700379#define CONFIG_SYS_FSL_ERRATUM_A005812
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800380#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Nikhil Badola11856912014-02-26 17:43:15 +0530381#define CONFIG_SYS_FSL_ERRATUM_A007075
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800382#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala243be8e2011-01-19 03:05:26 -0600383
York Suncefe11c2016-11-18 11:30:56 -0800384#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
York Sunffd06e02012-10-08 07:44:30 +0000385#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sund1001e32012-10-08 07:44:15 +0000386#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700387#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Galab5c87532011-02-16 02:03:29 -0600388#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600389#define CONFIG_SYS_FSL_NUM_LAWS 32
390#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galafbee0f72011-01-25 12:42:32 -0600391#define CONFIG_SYS_NUM_FMAN 1
392#define CONFIG_SYS_NUM_FM1_DTSEC 5
393#define CONFIG_SYS_NUM_FM1_10GEC 1
394#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700395#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530396#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Kumar Galac657d892011-02-04 00:43:34 -0600397#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600398#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala8f290842011-05-20 00:39:21 -0500399#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Roy Zang86221f02011-04-13 00:08:51 -0500400#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
401#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500402#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu30009762011-04-19 15:28:41 +0800403#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei99d7b0a2013-03-11 17:56:34 +0000404#define CONFIG_SYS_FSL_ERRATUM_USB14
York Sune22be772013-03-25 07:30:11 +0000405#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun41085082011-11-20 10:01:35 -0800406#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000407#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
408#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
409#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000410#define CONFIG_SYS_FSL_ERRATUM_A004510
411#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
412#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000413#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800414#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Suresh Gupta9c641a82014-02-26 14:29:12 +0530415#define CONFIG_SYS_FSL_ERRATUM_A006261
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800416#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala243be8e2011-01-19 03:05:26 -0600417
York Sun95390362016-11-18 11:39:36 -0800418#elif defined(CONFIG_ARCH_P5040)
Timur Tabi1956e432012-10-23 10:48:09 +0000419#define CONFIG_SYS_PPC64
Timur Tabi49054432012-10-05 11:09:19 +0000420#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700421#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Timur Tabi49054432012-10-05 11:09:19 +0000422#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
423#define CONFIG_SYS_FSL_NUM_LAWS 32
424#define CONFIG_SYS_FSL_SEC_COMPAT 4
425#define CONFIG_SYS_NUM_FMAN 2
426#define CONFIG_SYS_NUM_FM1_DTSEC 5
427#define CONFIG_SYS_NUM_FM1_10GEC 1
428#define CONFIG_SYS_NUM_FM2_DTSEC 5
429#define CONFIG_SYS_NUM_FM2_10GEC 1
430#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700431#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530432#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Timur Tabi49054432012-10-05 11:09:19 +0000433#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
434#define CONFIG_SYS_FSL_TBCLK_DIV 16
435#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
Timur Tabi49054432012-10-05 11:09:19 +0000436#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
437#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
438#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
439#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei99d7b0a2013-03-11 17:56:34 +0000440#define CONFIG_SYS_FSL_ERRATUM_USB14
Timur Tabi49054432012-10-05 11:09:19 +0000441#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
442#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
443#define CONFIG_SYS_FSL_ERRATUM_A004699
Timur Tabi49054432012-10-05 11:09:19 +0000444#define CONFIG_SYS_FSL_ERRATUM_A004510
445#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
Suresh Gupta9c641a82014-02-26 14:29:12 +0530446#define CONFIG_SYS_FSL_ERRATUM_A006261
Timur Tabi49054432012-10-05 11:09:19 +0000447#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
York Sund217a9a2013-06-25 11:37:49 -0700448#define CONFIG_SYS_FSL_ERRATUM_A005812
Timur Tabi49054432012-10-05 11:09:19 +0000449
York Sun115d60c2016-11-15 14:09:50 -0800450#elif defined(CONFIG_ARCH_BSC9131)
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000451#define CONFIG_FSL_SDHC_V2_3
452#define CONFIG_SYS_FSL_NUM_LAWS 12
453#define CONFIG_TSECV2
454#define CONFIG_SYS_FSL_SEC_COMPAT 4
455#define CONFIG_NUM_DDR_CONTROLLERS 1
York Sun34e026f2014-03-27 17:54:47 -0700456#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530457#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Priyanka Jain765b0bd2013-04-04 09:31:54 +0530458#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
459#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
Mingkai Hu362ee042013-05-16 10:18:13 +0800460#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000461#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000462#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun954a1a42013-08-20 15:09:43 -0700463#define CONFIG_SYS_FSL_ERRATUM_A005125
Nikhil Badola0dc78ff2014-11-21 17:25:21 +0530464#define CONFIG_SYS_FSL_ERRATUM_A004477
Haijun.Zhangf28bea02014-01-10 13:52:19 +0800465#define CONFIG_ESDHC_HC_BLK_ADDR
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000466
York Sun115d60c2016-11-15 14:09:50 -0800467#elif defined(CONFIG_ARCH_BSC9132)
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000468#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
469#define CONFIG_FSL_SDHC_V2_3
470#define CONFIG_SYS_FSL_NUM_LAWS 12
471#define CONFIG_TSECV2
472#define CONFIG_SYS_FSL_SEC_COMPAT 4
473#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700474#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
ramneek mehreshf1810d82013-10-18 17:40:17 +0530475#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Priyanka Jain64501c62013-07-02 09:21:04 +0530476#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
477#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
478#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
479#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
York Sun061ffed2013-04-18 19:31:01 -0700480#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000481#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000482#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
483#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
484#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
York Sun954a1a42013-08-20 15:09:43 -0700485#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lanf1a96ec2014-05-07 10:50:20 +0800486#define CONFIG_SYS_FSL_ERRATUM_A005434
Nikhil Badola0dc78ff2014-11-21 17:25:21 +0530487#define CONFIG_SYS_FSL_ERRATUM_A004477
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800488#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
489#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Haijun.Zhangf28bea02014-01-10 13:52:19 +0800490#define CONFIG_ESDHC_HC_BLK_ADDR
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000491
York Suncdb72c52016-11-21 13:41:30 -0800492#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
York Sun3d2972f2013-03-25 07:40:05 +0000493#define CONFIG_E6500
York Sunffd06e02012-10-08 07:44:30 +0000494#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun9e758752012-10-08 07:44:19 +0000495#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
496#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
York Sunf6981432013-03-25 07:40:07 +0000497#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
York Sun9e758752012-10-08 07:44:19 +0000498#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
York Sun26bc57d2016-11-21 13:35:41 -0800499#ifdef CONFIG_ARCH_T4240
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530500#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
York Sun9e758752012-10-08 07:44:19 +0000501#define CONFIG_SYS_NUM_FM1_DTSEC 8
502#define CONFIG_SYS_NUM_FM1_10GEC 2
503#define CONFIG_SYS_NUM_FM2_DTSEC 8
504#define CONFIG_SYS_NUM_FM2_10GEC 2
505#define CONFIG_NUM_DDR_CONTROLLERS 3
Sriram Dashf413d1c2016-08-17 11:47:54 +0530506#define CONFIG_SYS_FSL_ERRATUM_A006261
York Sun3d2972f2013-03-25 07:40:05 +0000507#else
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800508#define CONFIG_SYS_NUM_FM1_DTSEC 6
York Sun3d2972f2013-03-25 07:40:05 +0000509#define CONFIG_SYS_NUM_FM1_10GEC 1
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800510#define CONFIG_SYS_NUM_FM2_DTSEC 8
York Sun3d2972f2013-03-25 07:40:05 +0000511#define CONFIG_SYS_NUM_FM2_10GEC 1
512#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun652a7bb2016-11-21 13:31:34 -0800513#if defined(CONFIG_ARCH_T4160)
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800514#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800515#endif
York Sun3d2972f2013-03-25 07:40:05 +0000516#endif
York Sunb6240842013-03-25 07:33:29 +0000517#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
518#define CONFIG_SYS_FSL_NUM_LAWS 32
Prabhakar Kushwahaa4c955b2013-07-31 16:56:41 +0530519#define CONFIG_SYS_FSL_SRDS_1
520#define CONFIG_SYS_FSL_SRDS_2
York Sunb6240842013-03-25 07:33:29 +0000521#define CONFIG_SYS_FSL_SRDS_3
522#define CONFIG_SYS_FSL_SRDS_4
523#define CONFIG_SYS_FSL_SEC_COMPAT 4
524#define CONFIG_SYS_NUM_FMAN 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530525#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530526#define CONFIG_SYS_PME_CLK 0
York Sunb6240842013-03-25 07:33:29 +0000527#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Mingkai Hu362ee042013-05-16 10:18:13 +0800528#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
York Sunb6240842013-03-25 07:33:29 +0000529#define CONFIG_SYS_FMAN_V3
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530530#define CONFIG_SYS_FM1_CLK 3
531#define CONFIG_SYS_FM2_CLK 3
York Sunb6240842013-03-25 07:33:29 +0000532#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
533#define CONFIG_SYS_FSL_TBCLK_DIV 16
534#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
535#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
536#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
537#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Liu Gang08047932013-06-25 18:12:14 +0800538#define CONFIG_SYS_FSL_SRIO_LIODN
York Sunb6240842013-03-25 07:33:29 +0000539#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
540#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
541#define CONFIG_SYS_FSL_ERRATUM_A004468
542#define CONFIG_SYS_FSL_ERRATUM_A_004934
543#define CONFIG_SYS_FSL_ERRATUM_A005871
York Sun133fbfa2013-09-16 12:49:31 -0700544#define CONFIG_SYS_FSL_ERRATUM_A006379
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530545#define CONFIG_SYS_FSL_ERRATUM_A007186
Scott Wood82125192013-05-15 17:50:13 -0500546#define CONFIG_SYS_FSL_ERRATUM_A006593
Nikhil Badolaf3dff692014-10-17 09:12:07 +0530547#define CONFIG_SYS_FSL_ERRATUM_A007798
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530548#define CONFIG_SYS_FSL_SFP_VER_3_0
York Sunb6240842013-03-25 07:33:29 +0000549#define CONFIG_SYS_FSL_PCI_VER_3_X
550
York Sunb41f1922016-11-18 11:56:57 -0800551#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000552#define CONFIG_E6500
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000553#define CONFIG_SYS_PPC64 /* 64-bit core */
554#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
555#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
556#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530557#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
558#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
559#define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000560#define CONFIG_SYS_FSL_NUM_LAWS 32
Prabhakar Kushwahaa4c955b2013-07-31 16:56:41 +0530561#define CONFIG_SYS_FSL_SRDS_1
562#define CONFIG_SYS_FSL_SRDS_2
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530563#define CONFIG_SYS_MAPLE
564#define CONFIG_SYS_CPRI
565#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000566#define CONFIG_SYS_FSL_SEC_COMPAT 4
567#define CONFIG_SYS_NUM_FMAN 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530568#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530569#define CONFIG_SYS_FM1_CLK 0
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530570#define CONFIG_SYS_CPRI_CLK 3
571#define CONFIG_SYS_ULB_CLK 4
572#define CONFIG_SYS_ETVPE_CLK 1
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000573#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Mingkai Hu362ee042013-05-16 10:18:13 +0800574#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000575#define CONFIG_SYS_FMAN_V3
576#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
577#define CONFIG_SYS_FSL_TBCLK_DIV 16
578#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
579#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
580#define CONFIG_SYS_FSL_ERRATUM_A_004934
Shengzhou Liu04feb572013-02-27 21:56:54 +0000581#define CONFIG_SYS_FSL_ERRATUM_A005871
York Sun133fbfa2013-09-16 12:49:31 -0700582#define CONFIG_SYS_FSL_ERRATUM_A006379
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530583#define CONFIG_SYS_FSL_ERRATUM_A007186
Scott Wood82125192013-05-15 17:50:13 -0500584#define CONFIG_SYS_FSL_ERRATUM_A006593
Nikhil Badola11856912014-02-26 17:43:15 +0530585#define CONFIG_SYS_FSL_ERRATUM_A007075
Shaveta Leekha7af9a072014-02-26 16:08:22 +0530586#define CONFIG_SYS_FSL_ERRATUM_A006475
587#define CONFIG_SYS_FSL_ERRATUM_A006384
York Sunc3678b02014-03-28 15:07:27 -0700588#define CONFIG_SYS_FSL_ERRATUM_A007212
Nikhil Badola0dc78ff2014-11-21 17:25:21 +0530589#define CONFIG_SYS_FSL_ERRATUM_A004477
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530590#define CONFIG_SYS_FSL_SFP_VER_3_0
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000591
York Sun3006ebc2016-11-18 11:44:43 -0800592#ifdef CONFIG_ARCH_B4860
York Sunf6981432013-03-25 07:40:07 +0000593#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530594#define CONFIG_MAX_DSP_CPUS 12
595#define CONFIG_NUM_DSP_CPUS 6
Shaveta Leekha6df82e32014-02-26 16:07:37 +0530596#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530597#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
York Sund2404142012-10-08 07:44:20 +0000598#define CONFIG_SYS_NUM_FM1_DTSEC 6
599#define CONFIG_SYS_NUM_FM1_10GEC 2
Poonam Aggrwale394ceb2012-12-23 19:22:33 +0000600#define CONFIG_NUM_DDR_CONTROLLERS 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530601#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
York Sund2404142012-10-08 07:44:20 +0000602#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
603#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
604#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Liu Gang32f38ee2013-06-25 18:12:13 +0800605#define CONFIG_SYS_FSL_SRIO_LIODN
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000606#else
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530607#define CONFIG_MAX_DSP_CPUS 2
Shaveta Leekha6df82e32014-02-26 16:07:37 +0530608#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000609#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530610#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000611#define CONFIG_SYS_NUM_FM1_DTSEC 4
612#define CONFIG_SYS_NUM_FM1_10GEC 0
613#define CONFIG_NUM_DDR_CONTROLLERS 1
614#endif
York Sund2404142012-10-08 07:44:20 +0000615
York Sun5449c982016-11-18 13:36:39 -0800616#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\
Priyanka Jain2967af62013-10-18 12:30:21 +0530617defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
York Sun5f208d12013-03-25 07:40:06 +0000618#define CONFIG_E5500
619#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
620#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
York Sunf6981432013-03-25 07:40:07 +0000621#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
York Sun5f208d12013-03-25 07:40:06 +0000622#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
York Sun34e026f2014-03-27 17:54:47 -0700623#ifdef CONFIG_SYS_FSL_DDR4
624#define CONFIG_SYS_FSL_DDRC_GEN4
625#endif
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530626#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530627#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
York Sun5f208d12013-03-25 07:40:06 +0000628#define CONFIG_SYS_FSL_NUM_LAWS 16
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530629#define CONFIG_SYS_FSL_SRDS_1
630#define CONFIG_SYS_FSL_SEC_COMPAT 5
York Sun5f208d12013-03-25 07:40:06 +0000631#define CONFIG_SYS_NUM_FMAN 1
632#define CONFIG_SYS_NUM_FM1_DTSEC 5
633#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530634#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530635#define CONFIG_PME_PLAT_CLK_DIV 2
636#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530637#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
638#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
Prabhakar Kushwaha9f074e62014-10-29 22:33:09 +0530639#define CONFIG_SYS_FSL_ERRATUM_A008044
York Sun5f208d12013-03-25 07:40:06 +0000640#define CONFIG_SYS_FMAN_V3
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530641#define CONFIG_FM_PLAT_CLK_DIV 1
642#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +0800643#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
644 per rcw field value */
645#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530646#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
Priyanka Jainb1359912013-12-17 14:25:52 +0530647#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
Prabhakar Kushwahae03c76c2013-12-11 12:49:13 +0530648#define CONFIG_SYS_FSL_TBCLK_DIV 16
York Sun5f208d12013-03-25 07:40:06 +0000649#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
Nikhil Badolaa4f7cba2014-01-27 15:21:58 +0530650#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
York Sun5f208d12013-03-25 07:40:06 +0000651#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Haijun.Zhang1336e2d2014-03-18 17:04:23 +0800652#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
653#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
Zhao Qiang2a44efe2014-03-21 16:21:45 +0800654#define QE_MURAM_SIZE 0x6000UL
655#define MAX_QE_RISC 1
656#define QE_NUM_OF_SNUM 28
gaurav ranae622d9e2015-03-26 15:52:47 +0530657#define CONFIG_SYS_FSL_SFP_VER_3_0
Shengzhou Liua46b1852015-11-20 15:52:04 +0800658#define CONFIG_SYS_FSL_ERRATUM_A008378
Shengzhou Liua994b3d2015-12-16 16:45:41 +0800659#define CONFIG_SYS_FSL_ERRATUM_A009663
York Sun5f208d12013-03-25 07:40:06 +0000660
York Sune5d5f5a2016-11-18 13:01:34 -0800661#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) ||\
Shengzhou Liuf6050792014-11-24 17:11:54 +0800662defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
663#define CONFIG_E5500
664#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
665#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
666#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
667#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
668#define CONFIG_SYS_FMAN_V3
669#ifdef CONFIG_SYS_FSL_DDR4
670#define CONFIG_SYS_FSL_DDRC_GEN4
671#endif
Shengzhou Liuf6050792014-11-24 17:11:54 +0800672#define CONFIG_SYS_FSL_NUM_CC_PLL 2
673#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
Shengzhou Liuf6050792014-11-24 17:11:54 +0800674#define CONFIG_SYS_FSL_NUM_LAWS 16
675#define CONFIG_SYS_FSL_SRDS_1
676#define CONFIG_SYS_FSL_SEC_COMPAT 5
677#define CONFIG_SYS_NUM_FMAN 1
678#define CONFIG_SYS_NUM_FM1_DTSEC 4
679#define CONFIG_SYS_NUM_FM1_10GEC 1
Shengzhou Liucc19c252014-11-24 17:11:57 +0800680#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
Shengzhou Liuf6050792014-11-24 17:11:54 +0800681#define CONFIG_NUM_DDR_CONTROLLERS 1
682#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
683#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
684#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
685#define CONFIG_SYS_FM1_CLK 0
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +0800686#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
687 per rcw field value */
Shengzhou Liuf6050792014-11-24 17:11:54 +0800688#define CONFIG_QBMAN_CLK_DIV 1
689#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
690#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
691#define CONFIG_SYS_FSL_TBCLK_DIV 16
692#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
693#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
694#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Shengzhou Liuf6050792014-11-24 17:11:54 +0800695#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
696#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
697#define QE_MURAM_SIZE 0x6000UL
698#define MAX_QE_RISC 1
699#define QE_NUM_OF_SNUM 28
700#define CONFIG_SYS_FSL_SFP_VER_3_0
Shengzhou Liua46b1852015-11-20 15:52:04 +0800701#define CONFIG_SYS_FSL_ERRATUM_A008378
Shengzhou Liua994b3d2015-12-16 16:45:41 +0800702#define CONFIG_SYS_FSL_ERRATUM_A009663
Shengzhou Liuf6050792014-11-24 17:11:54 +0800703
York Sun0f3d80e2016-11-21 12:54:19 -0800704#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800705#define CONFIG_E6500
706#define CONFIG_SYS_PPC64 /* 64-bit core */
707#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
708#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
709#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
710#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
711#define CONFIG_SYS_FSL_QMAN_V3
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800712#define CONFIG_SYS_FSL_NUM_LAWS 32
713#define CONFIG_SYS_FSL_SEC_COMPAT 4
714#define CONFIG_SYS_NUM_FMAN 1
715#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
716#define CONFIG_SYS_FSL_SRDS_1
717#define CONFIG_SYS_FSL_PCI_VER_3_X
York Sun0f3d80e2016-11-21 12:54:19 -0800718#if defined(CONFIG_ARCH_T2080)
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800719#define CONFIG_SYS_NUM_FM1_DTSEC 8
720#define CONFIG_SYS_NUM_FM1_10GEC 4
721#define CONFIG_SYS_FSL_SRDS_2
722#define CONFIG_SYS_FSL_SRIO_LIODN
723#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
724#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
725#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
York Sun0f3d80e2016-11-21 12:54:19 -0800726#elif defined(CONFIG_ARCH_T2081)
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800727#define CONFIG_SYS_NUM_FM1_DTSEC 6
728#define CONFIG_SYS_NUM_FM1_10GEC 2
729#endif
Shengzhou Liu2ffa96d2013-12-18 10:27:55 +0800730#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800731#define CONFIG_NUM_DDR_CONTROLLERS 1
732#define CONFIG_PME_PLAT_CLK_DIV 1
733#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
734#define CONFIG_SYS_FM1_CLK 0
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +0800735#define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
736 per rcw field value */
737#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800738#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
739#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
740#define CONFIG_SYS_FMAN_V3
741#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
742#define CONFIG_SYS_FSL_TBCLK_DIV 16
743#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
744#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
745#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
York Sunc3678b02014-03-28 15:07:27 -0700746#define CONFIG_SYS_FSL_ERRATUM_A007212
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800747#define CONFIG_SYS_FSL_SFP_VER_3_0
748#define CONFIG_SYS_FSL_ISBC_VER 2
Haijun.Zhang1336e2d2014-03-18 17:04:23 +0800749#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Shengzhou Liuc665c472014-04-24 11:10:09 +0800750#define CONFIG_SYS_FSL_ERRATUM_A006593
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530751#define CONFIG_SYS_FSL_ERRATUM_A007186
Shengzhou Liuc665c472014-04-24 11:10:09 +0800752#define CONFIG_SYS_FSL_ERRATUM_A006379
Haijun.Zhang1336e2d2014-03-18 17:04:23 +0800753#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530754#define CONFIG_SYS_FSL_SFP_VER_3_0
Haijun.Zhang1336e2d2014-03-18 17:04:23 +0800755
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800756
York Sun4fd64742016-11-15 18:44:22 -0800757#elif defined(CONFIG_ARCH_C29X)
Mingkai Hu3b75e982013-07-04 17:30:36 +0800758#define CONFIG_FSL_SDHC_V2_3
759#define CONFIG_SYS_FSL_NUM_LAWS 12
760#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
761#define CONFIG_TSECV2_1
762#define CONFIG_SYS_FSL_SEC_COMPAT 6
763#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
764#define CONFIG_NUM_DDR_CONTROLLERS 1
York Sun34e026f2014-03-27 17:54:47 -0700765#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
Mingkai Hu3b75e982013-07-04 17:30:36 +0800766#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
York Sun954a1a42013-08-20 15:09:43 -0700767#define CONFIG_SYS_FSL_ERRATUM_A005125
Alex Porosanu404bf452016-04-29 15:17:59 +0300768#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
769#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
Mingkai Hu3b75e982013-07-04 17:30:36 +0800770
York Sun10343402016-11-18 12:29:51 -0800771#elif defined(CONFIG_ARCH_QEMU_E500)
Alexander Graffa08d392014-04-11 17:09:45 +0200772
Kumar Gala243be8e2011-01-19 03:05:26 -0600773#else
774#error Processor type not defined for this platform
775#endif
776
York Sunf6981432013-03-25 07:40:07 +0000777#ifdef CONFIG_E6500
778#define CONFIG_SYS_FSL_THREADS_PER_CORE 2
779#else
780#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
781#endif
782
York Sun5614e712013-09-30 09:22:09 -0700783#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
784 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
York Sun34e026f2014-03-27 17:54:47 -0700785 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
786 !defined(CONFIG_SYS_FSL_DDRC_GEN4)
York Sun5614e712013-09-30 09:22:09 -0700787#define CONFIG_SYS_FSL_DDRC_GEN3
788#endif
789
York Sun4fd64742016-11-15 18:44:22 -0800790#if !defined(CONFIG_ARCH_C29X)
Alex Porosanu404bf452016-04-29 15:17:59 +0300791#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
792#endif
793
Kumar Gala243be8e2011-01-19 03:05:26 -0600794#endif /* _ASM_MPC85xx_CONFIG_H_ */