Gitiles
Code Review Sign In
gerrit.cesnet.cz / github / trini / u-boot / 3d2972feac4383f5c0f929996976d00f9c072339 / . / arch / powerpc / include / asm / config_mpc85xx.h
blob: 569cb8e7c4225cb543bcf73132c374a1e422825f [file] [log] [blame]
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]1/*
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000[diff] [blame]2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 */
20
21#ifndef _ASM_MPC85xx_CONFIG_H_
22#define _ASM_MPC85xx_CONFIG_H_
23
24/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
25
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]26#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
27#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
28#endif
29
York Sun2a5fcb82012-10-28 08:12:54 +0000[diff] [blame]30/*
31 * This macro should be removed when we no longer care about backwards
32 * compatibility with older operating systems.
33 */
34#define CONFIG_PPC_SPINTABLE_COMPATIBLE
35
York Sun57495e42012-10-08 07:44:22 +0000[diff] [blame]36#define FSL_DDR_VER_4_7 47
37
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]38/* Number of TLB CAM entries we have on FSL Book-E chips */
39#if defined(CONFIG_E500MC)
40#define CONFIG_SYS_NUM_TLBCAMS 64
41#elif defined(CONFIG_E500)
42#define CONFIG_SYS_NUM_TLBCAMS 16
43#endif
44
45#if defined(CONFIG_MPC8536)
46#define CONFIG_MAX_CPUS 1
47#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +0000[diff] [blame]48#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]49#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]50#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]51
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100[diff] [blame]52#elif defined(CONFIG_MPC8540)
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]53#define CONFIG_MAX_CPUS 1
54#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]55#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]56
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100[diff] [blame]57#elif defined(CONFIG_MPC8541)
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]58#define CONFIG_MAX_CPUS 1
59#define CONFIG_SYS_FSL_NUM_LAWS 8
60#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]61#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]62
63#elif defined(CONFIG_MPC8544)
64#define CONFIG_MAX_CPUS 1
65#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +0000[diff] [blame]66#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]67#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]68#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]69
70#elif defined(CONFIG_MPC8548)
71#define CONFIG_MAX_CPUS 1
72#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +0000[diff] [blame]73#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]74#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]75#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala5ace2992011-09-16 09:54:30 -0500[diff] [blame]76#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
Kumar Gala2b3a1cd2011-10-03 08:37:57 -0500[diff] [blame]77#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
chenhui zhaoaada81d2011-10-03 08:38:50 -0500[diff] [blame]78#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]79#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
80#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
81#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
82#define CONFIG_SYS_FSL_RMU
83#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]84
85#elif defined(CONFIG_MPC8555)
86#define CONFIG_MAX_CPUS 1
87#define CONFIG_SYS_FSL_NUM_LAWS 8
88#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]89#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]90
91#elif defined(CONFIG_MPC8560)
92#define CONFIG_MAX_CPUS 1
93#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]94#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]95
96#elif defined(CONFIG_MPC8568)
97#define CONFIG_MAX_CPUS 1
98#define CONFIG_SYS_FSL_NUM_LAWS 10
99#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galafdb4dad2011-01-31 23:09:25 -0600[diff] [blame]100#define QE_MURAM_SIZE 0x10000UL
101#define MAX_QE_RISC 2
102#define QE_NUM_OF_SNUM 28
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]103#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]104#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
105#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
106#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
107#define CONFIG_SYS_FSL_RMU
108#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]109
110#elif defined(CONFIG_MPC8569)
111#define CONFIG_MAX_CPUS 1
112#define CONFIG_SYS_FSL_NUM_LAWS 10
113#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galafdb4dad2011-01-31 23:09:25 -0600[diff] [blame]114#define QE_MURAM_SIZE 0x20000UL
115#define MAX_QE_RISC 4
116#define QE_NUM_OF_SNUM 46
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]117#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]118#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
119#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
120#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
121#define CONFIG_SYS_FSL_RMU
122#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]123
124#elif defined(CONFIG_MPC8572)
125#define CONFIG_MAX_CPUS 2
126#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +0000[diff] [blame]127#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]128#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]129#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Suneb0aff72011-01-25 21:51:27 -0800[diff] [blame]130#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sun91671912011-01-25 22:05:49 -0800[diff] [blame]131#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]132
133#elif defined(CONFIG_P1010)
134#define CONFIG_MAX_CPUS 1
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530[diff] [blame]135#define CONFIG_FSL_SDHC_V2_3
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]136#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]137#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]138#define CONFIG_TSECV2
139#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530[diff] [blame]140#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
141#define CONFIG_NUM_DDR_CONTROLLERS 1
142#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]143#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530[diff] [blame]144#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal42aee642011-06-30 03:00:28 -0500[diff] [blame]145#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalfb855f42011-06-29 16:32:52 +0530[diff] [blame]146#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwalbc6bbd62011-07-07 20:36:47 +0530[diff] [blame]147#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]148
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]149/* P1011 is single core version of P1020 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]150#elif defined(CONFIG_P1011)
151#define CONFIG_MAX_CPUS 1
152#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]153#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]154#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000[diff] [blame]155#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]156#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]157#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]158#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
159#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]160
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]161/* P1012 is single core version of P1021 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]162#elif defined(CONFIG_P1012)
163#define CONFIG_MAX_CPUS 1
164#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]165#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]166#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000[diff] [blame]167#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]168#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]169#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]170#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
171#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600[diff] [blame]172#define QE_MURAM_SIZE 0x6000UL
173#define MAX_QE_RISC 1
174#define QE_NUM_OF_SNUM 28
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]175
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]176/* P1013 is single core version of P1022 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]177#elif defined(CONFIG_P1013)
178#define CONFIG_MAX_CPUS 1
179#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]180#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]181#define CONFIG_TSECV2
182#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]183#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang2d7534a2011-01-30 17:06:20 -0600[diff] [blame]184#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
185#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
186#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]187
188#elif defined(CONFIG_P1014)
189#define CONFIG_MAX_CPUS 1
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530[diff] [blame]190#define CONFIG_FSL_SDHC_V2_3
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]191#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]192#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]193#define CONFIG_TSECV2
194#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530[diff] [blame]195#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
196#define CONFIG_NUM_DDR_CONTROLLERS 1
197#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530[diff] [blame]198#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal42aee642011-06-30 03:00:28 -0500[diff] [blame]199#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalfb855f42011-06-29 16:32:52 +0530[diff] [blame]200#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwalbc6bbd62011-07-07 20:36:47 +0530[diff] [blame]201#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]202
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]203/* P1017 is single core version of P1023 */
Roy Zang67a719d2011-02-03 22:14:19 -0600[diff] [blame]204#elif defined(CONFIG_P1017)
205#define CONFIG_MAX_CPUS 1
206#define CONFIG_SYS_FSL_NUM_LAWS 12
207#define CONFIG_SYS_FSL_SEC_COMPAT 4
208#define CONFIG_SYS_NUM_FMAN 1
209#define CONFIG_SYS_NUM_FM1_DTSEC 2
210#define CONFIG_NUM_DDR_CONTROLLERS 1
211#define CONFIG_SYS_QMAN_NUM_PORTALS 3
212#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]213#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]214#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]215#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang67a719d2011-02-03 22:14:19 -0600[diff] [blame]216
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]217#elif defined(CONFIG_P1020)
218#define CONFIG_MAX_CPUS 2
219#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]220#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]221#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000[diff] [blame]222#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]223#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]224#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]225#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
226#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]227
228#elif defined(CONFIG_P1021)
229#define CONFIG_MAX_CPUS 2
230#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]231#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]232#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000[diff] [blame]233#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]234#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]235#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]236#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
237#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600[diff] [blame]238#define QE_MURAM_SIZE 0x6000UL
239#define MAX_QE_RISC 1
240#define QE_NUM_OF_SNUM 28
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]241
242#elif defined(CONFIG_P1022)
243#define CONFIG_MAX_CPUS 2
244#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]245#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]246#define CONFIG_TSECV2
247#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]248#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang2d7534a2011-01-30 17:06:20 -0600[diff] [blame]249#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
250#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
251#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]252
Roy Zang67a719d2011-02-03 22:14:19 -0600[diff] [blame]253#elif defined(CONFIG_P1023)
254#define CONFIG_MAX_CPUS 2
255#define CONFIG_SYS_FSL_NUM_LAWS 12
256#define CONFIG_SYS_FSL_SEC_COMPAT 4
257#define CONFIG_SYS_NUM_FMAN 1
258#define CONFIG_SYS_NUM_FM1_DTSEC 2
259#define CONFIG_NUM_DDR_CONTROLLERS 1
260#define CONFIG_SYS_QMAN_NUM_PORTALS 3
261#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]262#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]263#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]264#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang67a719d2011-02-03 22:14:19 -0600[diff] [blame]265
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]266/* P1024 is lower end variant of P1020 */
267#elif defined(CONFIG_P1024)
268#define CONFIG_MAX_CPUS 2
269#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]270#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]271#define CONFIG_TSECV2
272#define CONFIG_FSL_PCIE_DISABLE_ASPM
273#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]274#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]275#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
276#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
277
278/* P1025 is lower end variant of P1021 */
279#elif defined(CONFIG_P1025)
280#define CONFIG_MAX_CPUS 2
281#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]282#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]283#define CONFIG_TSECV2
284#define CONFIG_FSL_PCIE_DISABLE_ASPM
285#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]286#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]287#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
288#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600[diff] [blame]289#define QE_MURAM_SIZE 0x6000UL
290#define MAX_QE_RISC 1
291#define QE_NUM_OF_SNUM 28
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]292
293/* P2010 is single core version of P2020 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]294#elif defined(CONFIG_P2010)
295#define CONFIG_MAX_CPUS 1
296#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]297#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]298#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]299#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala6e7f0bc02011-01-26 01:43:15 -0600[diff] [blame]300#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala5103a032011-01-29 15:36:10 -0600[diff] [blame]301#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]302
303#elif defined(CONFIG_P2020)
304#define CONFIG_MAX_CPUS 2
305#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]306#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]307#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]308#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala6e7f0bc02011-01-26 01:43:15 -0600[diff] [blame]309#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala5103a032011-01-29 15:36:10 -0600[diff] [blame]310#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]311#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
312#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
313#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
314#define CONFIG_SYS_FSL_RMU
315#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]316
Scott Wood3e978f52012-08-14 10:14:51 +0000[diff] [blame]317#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]318#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Gala1f979872011-05-13 01:16:07 -0500[diff] [blame]319#define CONFIG_MAX_CPUS 4
320#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
321#define CONFIG_SYS_FSL_NUM_LAWS 32
322#define CONFIG_SYS_FSL_SEC_COMPAT 4
323#define CONFIG_SYS_NUM_FMAN 1
324#define CONFIG_SYS_NUM_FM1_DTSEC 5
325#define CONFIG_SYS_NUM_FM1_10GEC 1
326#define CONFIG_NUM_DDR_CONTROLLERS 1
327#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
328#define CONFIG_SYS_FSL_TBCLK_DIV 32
329#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]330#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala1f979872011-05-13 01:16:07 -0500[diff] [blame]331#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
332#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500[diff] [blame]333#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala1f979872011-05-13 01:16:07 -0500[diff] [blame]334#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun5e23ab02012-05-07 07:26:47 +0000[diff] [blame]335#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei99d7b0a2013-03-11 17:56:34 +0000[diff] [blame]336#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala43f082b2011-11-22 06:51:15 -0600[diff] [blame]337#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sune22be772013-03-25 07:30:11 +0000[diff] [blame]338#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun41085082011-11-20 10:01:35 -0800[diff] [blame]339#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang19e4a002012-10-14 20:55:17 +0000[diff] [blame]340#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]341#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
342#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
343#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000[diff] [blame]344#define CONFIG_SYS_FSL_ERRATUM_A004510
345#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
346#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
347#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000[diff] [blame]348#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi01180332012-10-25 12:40:00 +0000[diff] [blame]349#define CONFIG_SYS_FSL_ERRATUM_A004849
Kumar Gala1f979872011-05-13 01:16:07 -0500[diff] [blame]350
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]351#elif defined(CONFIG_PPC_P3041)
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]352#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]353#define CONFIG_MAX_CPUS 4
Kumar Galab5c87532011-02-16 02:03:29 -0600[diff] [blame]354#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]355#define CONFIG_SYS_FSL_NUM_LAWS 32
356#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galafbee0f72011-01-25 12:42:32 -0600[diff] [blame]357#define CONFIG_SYS_NUM_FMAN 1
358#define CONFIG_SYS_NUM_FM1_DTSEC 5
359#define CONFIG_SYS_NUM_FM1_10GEC 1
360#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]361#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600[diff] [blame]362#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]363#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]364#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang86221f02011-04-13 00:08:51 -0500[diff] [blame]365#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
366#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500[diff] [blame]367#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu30009762011-04-19 15:28:41 +0800[diff] [blame]368#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun57125f22012-08-08 18:04:53 +0000[diff] [blame]369#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei99d7b0a2013-03-11 17:56:34 +0000[diff] [blame]370#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala43f082b2011-11-22 06:51:15 -0600[diff] [blame]371#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sune22be772013-03-25 07:30:11 +0000[diff] [blame]372#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun41085082011-11-20 10:01:35 -0800[diff] [blame]373#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang19e4a002012-10-14 20:55:17 +0000[diff] [blame]374#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]375#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
376#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
377#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000[diff] [blame]378#define CONFIG_SYS_FSL_ERRATUM_A004510
379#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
380#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
381#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000[diff] [blame]382#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi01180332012-10-25 12:40:00 +0000[diff] [blame]383#define CONFIG_SYS_FSL_ERRATUM_A004849
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]384
Scott Wood3e978f52012-08-14 10:14:51 +0000[diff] [blame]385#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]386#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]387#define CONFIG_MAX_CPUS 8
Kumar Galab5c87532011-02-16 02:03:29 -0600[diff] [blame]388#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]389#define CONFIG_SYS_FSL_NUM_LAWS 32
390#define CONFIG_SYS_FSL_SEC_COMPAT 4
391#define CONFIG_SYS_NUM_FMAN 2
392#define CONFIG_SYS_NUM_FM1_DTSEC 4
393#define CONFIG_SYS_NUM_FM2_DTSEC 4
394#define CONFIG_SYS_NUM_FM1_10GEC 1
395#define CONFIG_SYS_NUM_FM2_10GEC 1
396#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]397#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600[diff] [blame]398#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]399#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]400#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]401#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
402#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sunfa8d23c2011-01-10 12:03:01 +0000[diff] [blame]403#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]404#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
405#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
406#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
Zang Roy-R619114e0be342012-09-18 09:50:08 +0000[diff] [blame]407#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]408#define CONFIG_SYS_P4080_ERRATUM_CPU22
York Sun5e23ab02012-05-07 07:26:47 +0000[diff] [blame]409#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]410#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medvedf8af0b2010-08-31 22:57:38 -0500[diff] [blame]411#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabid90fdba2011-04-18 17:16:00 -0500[diff] [blame]412#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabida30b9f2011-04-01 13:19:36 -0500[diff] [blame]413#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Gala43f082b2011-11-22 06:51:15 -0600[diff] [blame]414#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun41085082011-11-20 10:01:35 -0800[diff] [blame]415#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang19e4a002012-10-14 20:55:17 +0000[diff] [blame]416#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]417#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
418#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
419#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
420#define CONFIG_SYS_FSL_RMU
421#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Scott Wood33eee332012-08-14 10:14:53 +0000[diff] [blame]422#define CONFIG_SYS_FSL_ERRATUM_A004510
423#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
424#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
Liu Gangd59c5572012-09-28 21:26:19 +0000[diff] [blame]425#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi01180332012-10-25 12:40:00 +0000[diff] [blame]426#define CONFIG_SYS_FSL_ERRATUM_A004849
Timur Tabid607b962012-11-01 08:20:23 +0000[diff] [blame]427#define CONFIG_SYS_FSL_ERRATUM_A004580
Yuanquan Chenc0a4e6b2012-11-26 23:49:45 +0000[diff] [blame]428#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]429
Scott Wood3e978f52012-08-14 10:14:51 +0000[diff] [blame]430#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
York Sunffd06e02012-10-08 07:44:30 +0000[diff] [blame]431#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]432#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]433#define CONFIG_MAX_CPUS 2
Kumar Galab5c87532011-02-16 02:03:29 -0600[diff] [blame]434#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]435#define CONFIG_SYS_FSL_NUM_LAWS 32
436#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galafbee0f72011-01-25 12:42:32 -0600[diff] [blame]437#define CONFIG_SYS_NUM_FMAN 1
438#define CONFIG_SYS_NUM_FM1_DTSEC 5
439#define CONFIG_SYS_NUM_FM1_10GEC 1
440#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]441#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600[diff] [blame]442#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]443#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]444#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang86221f02011-04-13 00:08:51 -0500[diff] [blame]445#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
446#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500[diff] [blame]447#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu30009762011-04-19 15:28:41 +0800[diff] [blame]448#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei99d7b0a2013-03-11 17:56:34 +0000[diff] [blame]449#define CONFIG_SYS_FSL_ERRATUM_USB14
York Sune22be772013-03-25 07:30:11 +0000[diff] [blame]450#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun41085082011-11-20 10:01:35 -0800[diff] [blame]451#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang19e4a002012-10-14 20:55:17 +0000[diff] [blame]452#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]453#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
454#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
455#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000[diff] [blame]456#define CONFIG_SYS_FSL_ERRATUM_A004510
457#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
458#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000[diff] [blame]459#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]460
Timur Tabi49054432012-10-05 11:09:19 +0000[diff] [blame]461#elif defined(CONFIG_PPC_P5040)
Timur Tabi1956e432012-10-23 10:48:09 +0000[diff] [blame]462#define CONFIG_SYS_PPC64
Timur Tabi49054432012-10-05 11:09:19 +0000[diff] [blame]463#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
464#define CONFIG_MAX_CPUS 4
465#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
466#define CONFIG_SYS_FSL_NUM_LAWS 32
467#define CONFIG_SYS_FSL_SEC_COMPAT 4
468#define CONFIG_SYS_NUM_FMAN 2
469#define CONFIG_SYS_NUM_FM1_DTSEC 5
470#define CONFIG_SYS_NUM_FM1_10GEC 1
471#define CONFIG_SYS_NUM_FM2_DTSEC 5
472#define CONFIG_SYS_NUM_FM2_10GEC 1
473#define CONFIG_NUM_DDR_CONTROLLERS 2
474#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
475#define CONFIG_SYS_FSL_TBCLK_DIV 16
476#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
477#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
478#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
479#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
480#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
481#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei99d7b0a2013-03-11 17:56:34 +0000[diff] [blame]482#define CONFIG_SYS_FSL_ERRATUM_USB14
Timur Tabi49054432012-10-05 11:09:19 +0000[diff] [blame]483#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
484#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
485#define CONFIG_SYS_FSL_ERRATUM_A004699
Timur Tabi49054432012-10-05 11:09:19 +0000[diff] [blame]486#define CONFIG_SYS_FSL_ERRATUM_A004510
487#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
488#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
489
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000[diff] [blame]490#elif defined(CONFIG_BSC9131)
491#define CONFIG_MAX_CPUS 1
492#define CONFIG_FSL_SDHC_V2_3
493#define CONFIG_SYS_FSL_NUM_LAWS 12
494#define CONFIG_TSECV2
495#define CONFIG_SYS_FSL_SEC_COMPAT 4
496#define CONFIG_NUM_DDR_CONTROLLERS 1
497#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
498#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000[diff] [blame]499#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
500
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000[diff] [blame]501#elif defined(CONFIG_BSC9132)
502#define CONFIG_MAX_CPUS 2
503#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
504#define CONFIG_FSL_SDHC_V2_3
505#define CONFIG_SYS_FSL_NUM_LAWS 12
506#define CONFIG_TSECV2
507#define CONFIG_SYS_FSL_SEC_COMPAT 4
508#define CONFIG_NUM_DDR_CONTROLLERS 2
509#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
510#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000[diff] [blame]511#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
512#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
513#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
514
York Sun3d2972f2013-03-25 07:40:05 +0000[diff] [blame^]515#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
516#define CONFIG_E6500
York Sunffd06e02012-10-08 07:44:30 +0000[diff] [blame]517#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun9e758752012-10-08 07:44:19 +0000[diff] [blame]518#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
519#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
520#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
York Sun3d2972f2013-03-25 07:40:05 +0000[diff] [blame^]521#ifdef CONFIG_PPC_T4240
York Sun9e758752012-10-08 07:44:19 +0000[diff] [blame]522#define CONFIG_MAX_CPUS 12
York Sun9e758752012-10-08 07:44:19 +0000[diff] [blame]523#define CONFIG_SYS_NUM_FM1_DTSEC 8
524#define CONFIG_SYS_NUM_FM1_10GEC 2
525#define CONFIG_SYS_NUM_FM2_DTSEC 8
526#define CONFIG_SYS_NUM_FM2_10GEC 2
527#define CONFIG_NUM_DDR_CONTROLLERS 3
York Sun3d2972f2013-03-25 07:40:05 +0000[diff] [blame^]528#else
York Sunb6240842013-03-25 07:33:29 +0000[diff] [blame]529#define CONFIG_MAX_CPUS 8
York Sun3d2972f2013-03-25 07:40:05 +0000[diff] [blame^]530#define CONFIG_SYS_NUM_FM1_DTSEC 7
531#define CONFIG_SYS_NUM_FM1_10GEC 1
532#define CONFIG_SYS_NUM_FM2_DTSEC 7
533#define CONFIG_SYS_NUM_FM2_10GEC 1
534#define CONFIG_NUM_DDR_CONTROLLERS 2
535#endif
York Sunb6240842013-03-25 07:33:29 +0000[diff] [blame]536#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
537#define CONFIG_SYS_FSL_NUM_LAWS 32
538#define CONFIG_SYS_FSL_SRDS_3
539#define CONFIG_SYS_FSL_SRDS_4
540#define CONFIG_SYS_FSL_SEC_COMPAT 4
541#define CONFIG_SYS_NUM_FMAN 2
York Sunb6240842013-03-25 07:33:29 +0000[diff] [blame]542#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
543#define CONFIG_SYS_FMAN_V3
544#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
545#define CONFIG_SYS_FSL_TBCLK_DIV 16
546#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
547#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
548#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
549#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
550#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
551#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
552#define CONFIG_SYS_FSL_ERRATUM_A004468
553#define CONFIG_SYS_FSL_ERRATUM_A_004934
554#define CONFIG_SYS_FSL_ERRATUM_A005871
555#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
556#define CONFIG_SYS_FSL_PCI_VER_3_X
557
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000[diff] [blame]558#elif defined(CONFIG_PPC_B4420)
559#define CONFIG_SYS_PPC64 /* 64-bit core */
560#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
561#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
562#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
563#define CONFIG_MAX_CPUS 2
564#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
565#define CONFIG_SYS_FSL_NUM_LAWS 32
566#define CONFIG_SYS_FSL_SEC_COMPAT 4
567#define CONFIG_SYS_NUM_FMAN 1
568#define CONFIG_SYS_NUM_FM1_DTSEC 4
569#define CONFIG_NUM_DDR_CONTROLLERS 1
570#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
571#define CONFIG_SYS_FMAN_V3
572#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
573#define CONFIG_SYS_FSL_TBCLK_DIV 16
574#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
575#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
576#define CONFIG_SYS_FSL_ERRATUM_A_004934
Shengzhou Liu04feb572013-02-27 21:56:54 +0000[diff] [blame]577#define CONFIG_SYS_FSL_ERRATUM_A005871
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000[diff] [blame]578#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
579
York Sund2404142012-10-08 07:44:20 +0000[diff] [blame]580#elif defined(CONFIG_PPC_B4860)
York Sunffd06e02012-10-08 07:44:30 +0000[diff] [blame]581#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sund2404142012-10-08 07:44:20 +0000[diff] [blame]582#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
583#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
584#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
585#define CONFIG_MAX_CPUS 4
586#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
587#define CONFIG_SYS_FSL_NUM_LAWS 32
588#define CONFIG_SYS_FSL_SEC_COMPAT 4
589#define CONFIG_SYS_NUM_FMAN 1
590#define CONFIG_SYS_NUM_FM1_DTSEC 6
591#define CONFIG_SYS_NUM_FM1_10GEC 2
Poonam Aggrwale394ceb2012-12-23 19:22:33 +0000[diff] [blame]592#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sund2404142012-10-08 07:44:20 +0000[diff] [blame]593#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Roy Zang111fd192012-10-08 07:44:21 +0000[diff] [blame]594#define CONFIG_SYS_FMAN_V3
York Sund2404142012-10-08 07:44:20 +0000[diff] [blame]595#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
596#define CONFIG_SYS_FSL_TBCLK_DIV 16
597#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
598#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
599#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
600#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
601#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
602#define CONFIG_SYS_FSL_ERRATUM_A_004934
Shengzhou Liu04feb572013-02-27 21:56:54 +0000[diff] [blame]603#define CONFIG_SYS_FSL_ERRATUM_A005871
York Sund2404142012-10-08 07:44:20 +0000[diff] [blame]604#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
605
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]606#else
607#error Processor type not defined for this platform
608#endif
609
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]610#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
611#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
612#endif
613
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]614#endif /* _ASM_MPC85xx_CONFIG_H_ */