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gerrit.cesnet.cz / github / trini / u-boot / 57495e4e5e70d6a4e9b8f053bdf099f9cdb363d2 / . / arch / powerpc / include / asm / config_mpc85xx.h
blob: ba13ddf9515e847a58ccf8df470b12437a6eae07 [file] [log] [blame]
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]1/*
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000[diff] [blame]2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 */
20
21#ifndef _ASM_MPC85xx_CONFIG_H_
22#define _ASM_MPC85xx_CONFIG_H_
23
24/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
25
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]26#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
27#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
28#endif
29
York Sun57495e42012-10-08 07:44:22 +0000[diff] [blame^]30#define FSL_DDR_VER_4_7 47
31
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]32/* Number of TLB CAM entries we have on FSL Book-E chips */
33#if defined(CONFIG_E500MC)
34#define CONFIG_SYS_NUM_TLBCAMS 64
35#elif defined(CONFIG_E500)
36#define CONFIG_SYS_NUM_TLBCAMS 16
37#endif
38
39#if defined(CONFIG_MPC8536)
40#define CONFIG_MAX_CPUS 1
41#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +0000[diff] [blame]42#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]43#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]44#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]45
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100[diff] [blame]46#elif defined(CONFIG_MPC8540)
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]47#define CONFIG_MAX_CPUS 1
48#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]49#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]50
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100[diff] [blame]51#elif defined(CONFIG_MPC8541)
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]52#define CONFIG_MAX_CPUS 1
53#define CONFIG_SYS_FSL_NUM_LAWS 8
54#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]55#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]56
57#elif defined(CONFIG_MPC8544)
58#define CONFIG_MAX_CPUS 1
59#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +0000[diff] [blame]60#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]61#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]62#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]63
64#elif defined(CONFIG_MPC8548)
65#define CONFIG_MAX_CPUS 1
66#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +0000[diff] [blame]67#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]68#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]69#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala5ace2992011-09-16 09:54:30 -0500[diff] [blame]70#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
Kumar Gala2b3a1cd2011-10-03 08:37:57 -0500[diff] [blame]71#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
chenhui zhaoaada81d2011-10-03 08:38:50 -0500[diff] [blame]72#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]73#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
74#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
75#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
76#define CONFIG_SYS_FSL_RMU
77#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]78
79#elif defined(CONFIG_MPC8555)
80#define CONFIG_MAX_CPUS 1
81#define CONFIG_SYS_FSL_NUM_LAWS 8
82#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]83#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]84
85#elif defined(CONFIG_MPC8560)
86#define CONFIG_MAX_CPUS 1
87#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]88#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]89
90#elif defined(CONFIG_MPC8568)
91#define CONFIG_MAX_CPUS 1
92#define CONFIG_SYS_FSL_NUM_LAWS 10
93#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galafdb4dad2011-01-31 23:09:25 -0600[diff] [blame]94#define QE_MURAM_SIZE 0x10000UL
95#define MAX_QE_RISC 2
96#define QE_NUM_OF_SNUM 28
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]97#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]98#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
99#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
100#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
101#define CONFIG_SYS_FSL_RMU
102#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]103
104#elif defined(CONFIG_MPC8569)
105#define CONFIG_MAX_CPUS 1
106#define CONFIG_SYS_FSL_NUM_LAWS 10
107#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galafdb4dad2011-01-31 23:09:25 -0600[diff] [blame]108#define QE_MURAM_SIZE 0x20000UL
109#define MAX_QE_RISC 4
110#define QE_NUM_OF_SNUM 46
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]111#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]112#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
113#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
114#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
115#define CONFIG_SYS_FSL_RMU
116#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]117
118#elif defined(CONFIG_MPC8572)
119#define CONFIG_MAX_CPUS 2
120#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +0000[diff] [blame]121#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]122#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]123#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Suneb0aff72011-01-25 21:51:27 -0800[diff] [blame]124#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sun91671912011-01-25 22:05:49 -0800[diff] [blame]125#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]126
127#elif defined(CONFIG_P1010)
128#define CONFIG_MAX_CPUS 1
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530[diff] [blame]129#define CONFIG_FSL_SDHC_V2_3
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]130#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]131#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]132#define CONFIG_TSECV2
133#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530[diff] [blame]134#define CONFIG_FSL_SATA_V2
135#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
136#define CONFIG_NUM_DDR_CONTROLLERS 1
137#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]138#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530[diff] [blame]139#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal42aee642011-06-30 03:00:28 -0500[diff] [blame]140#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalfb855f42011-06-29 16:32:52 +0530[diff] [blame]141#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwalbc6bbd62011-07-07 20:36:47 +0530[diff] [blame]142#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]143
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]144/* P1011 is single core version of P1020 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]145#elif defined(CONFIG_P1011)
146#define CONFIG_MAX_CPUS 1
147#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]148#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]149#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000[diff] [blame]150#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]151#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]152#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]153#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
154#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]155
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]156/* P1012 is single core version of P1021 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]157#elif defined(CONFIG_P1012)
158#define CONFIG_MAX_CPUS 1
159#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]160#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]161#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000[diff] [blame]162#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]163#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]164#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]165#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
166#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600[diff] [blame]167#define QE_MURAM_SIZE 0x6000UL
168#define MAX_QE_RISC 1
169#define QE_NUM_OF_SNUM 28
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]170
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]171/* P1013 is single core version of P1022 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]172#elif defined(CONFIG_P1013)
173#define CONFIG_MAX_CPUS 1
174#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]175#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]176#define CONFIG_TSECV2
177#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi3e0529f2011-11-21 17:10:22 -0600[diff] [blame]178#define CONFIG_FSL_SATA_V2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]179#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang2d7534a2011-01-30 17:06:20 -0600[diff] [blame]180#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
181#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
182#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]183
184#elif defined(CONFIG_P1014)
185#define CONFIG_MAX_CPUS 1
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530[diff] [blame]186#define CONFIG_FSL_SDHC_V2_3
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]187#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]188#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]189#define CONFIG_TSECV2
190#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530[diff] [blame]191#define CONFIG_FSL_SATA_V2
192#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
193#define CONFIG_NUM_DDR_CONTROLLERS 1
194#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530[diff] [blame]195#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal42aee642011-06-30 03:00:28 -0500[diff] [blame]196#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalfb855f42011-06-29 16:32:52 +0530[diff] [blame]197#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwalbc6bbd62011-07-07 20:36:47 +0530[diff] [blame]198#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]199
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]200/* P1017 is single core version of P1023 */
Roy Zang67a719d2011-02-03 22:14:19 -0600[diff] [blame]201#elif defined(CONFIG_P1017)
202#define CONFIG_MAX_CPUS 1
203#define CONFIG_SYS_FSL_NUM_LAWS 12
204#define CONFIG_SYS_FSL_SEC_COMPAT 4
205#define CONFIG_SYS_NUM_FMAN 1
206#define CONFIG_SYS_NUM_FM1_DTSEC 2
207#define CONFIG_NUM_DDR_CONTROLLERS 1
208#define CONFIG_SYS_QMAN_NUM_PORTALS 3
209#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]210#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]211#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]212#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang67a719d2011-02-03 22:14:19 -0600[diff] [blame]213
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]214#elif defined(CONFIG_P1020)
215#define CONFIG_MAX_CPUS 2
216#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]217#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]218#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000[diff] [blame]219#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]220#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]221#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]222#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
223#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]224
225#elif defined(CONFIG_P1021)
226#define CONFIG_MAX_CPUS 2
227#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]228#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]229#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000[diff] [blame]230#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]231#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]232#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]233#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
234#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600[diff] [blame]235#define QE_MURAM_SIZE 0x6000UL
236#define MAX_QE_RISC 1
237#define QE_NUM_OF_SNUM 28
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]238
239#elif defined(CONFIG_P1022)
240#define CONFIG_MAX_CPUS 2
241#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]242#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]243#define CONFIG_TSECV2
244#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi3e0529f2011-11-21 17:10:22 -0600[diff] [blame]245#define CONFIG_FSL_SATA_V2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]246#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang2d7534a2011-01-30 17:06:20 -0600[diff] [blame]247#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
248#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
249#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]250
Roy Zang67a719d2011-02-03 22:14:19 -0600[diff] [blame]251#elif defined(CONFIG_P1023)
252#define CONFIG_MAX_CPUS 2
253#define CONFIG_SYS_FSL_NUM_LAWS 12
254#define CONFIG_SYS_FSL_SEC_COMPAT 4
255#define CONFIG_SYS_NUM_FMAN 1
256#define CONFIG_SYS_NUM_FM1_DTSEC 2
257#define CONFIG_NUM_DDR_CONTROLLERS 1
258#define CONFIG_SYS_QMAN_NUM_PORTALS 3
259#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]260#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]261#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]262#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang67a719d2011-02-03 22:14:19 -0600[diff] [blame]263
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]264/* P1024 is lower end variant of P1020 */
265#elif defined(CONFIG_P1024)
266#define CONFIG_MAX_CPUS 2
267#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]268#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]269#define CONFIG_TSECV2
270#define CONFIG_FSL_PCIE_DISABLE_ASPM
271#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]272#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]273#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
274#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
275
276/* P1025 is lower end variant of P1021 */
277#elif defined(CONFIG_P1025)
278#define CONFIG_MAX_CPUS 2
279#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]280#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]281#define CONFIG_TSECV2
282#define CONFIG_FSL_PCIE_DISABLE_ASPM
283#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]284#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]285#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
286#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600[diff] [blame]287#define QE_MURAM_SIZE 0x6000UL
288#define MAX_QE_RISC 1
289#define QE_NUM_OF_SNUM 28
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]290
291/* P2010 is single core version of P2020 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]292#elif defined(CONFIG_P2010)
293#define CONFIG_MAX_CPUS 1
294#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]295#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]296#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]297#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala6e7f0bc02011-01-26 01:43:15 -0600[diff] [blame]298#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala5103a032011-01-29 15:36:10 -0600[diff] [blame]299#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]300
301#elif defined(CONFIG_P2020)
302#define CONFIG_MAX_CPUS 2
303#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]304#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]305#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]306#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala6e7f0bc02011-01-26 01:43:15 -0600[diff] [blame]307#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala5103a032011-01-29 15:36:10 -0600[diff] [blame]308#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]309#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
310#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
311#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
312#define CONFIG_SYS_FSL_RMU
313#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]314
Scott Wood3e978f52012-08-14 10:14:51 +0000[diff] [blame]315#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]316#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Gala1f979872011-05-13 01:16:07 -0500[diff] [blame]317#define CONFIG_MAX_CPUS 4
318#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
319#define CONFIG_SYS_FSL_NUM_LAWS 32
320#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi3e0529f2011-11-21 17:10:22 -0600[diff] [blame]321#define CONFIG_FSL_SATA_V2
Kumar Gala1f979872011-05-13 01:16:07 -0500[diff] [blame]322#define CONFIG_SYS_NUM_FMAN 1
323#define CONFIG_SYS_NUM_FM1_DTSEC 5
324#define CONFIG_SYS_NUM_FM1_10GEC 1
325#define CONFIG_NUM_DDR_CONTROLLERS 1
326#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
327#define CONFIG_SYS_FSL_TBCLK_DIV 32
328#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]329#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala1f979872011-05-13 01:16:07 -0500[diff] [blame]330#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
331#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500[diff] [blame]332#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala1f979872011-05-13 01:16:07 -0500[diff] [blame]333#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun5e23ab02012-05-07 07:26:47 +0000[diff] [blame]334#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala43f082b2011-11-22 06:51:15 -0600[diff] [blame]335#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun41085082011-11-20 10:01:35 -0800[diff] [blame]336#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]337#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
338#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
339#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000[diff] [blame]340#define CONFIG_SYS_FSL_ERRATUM_A004510
341#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
342#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
343#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000[diff] [blame]344#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Kumar Gala1f979872011-05-13 01:16:07 -0500[diff] [blame]345
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]346#elif defined(CONFIG_PPC_P3041)
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]347#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]348#define CONFIG_MAX_CPUS 4
Kumar Galab5c87532011-02-16 02:03:29 -0600[diff] [blame]349#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]350#define CONFIG_SYS_FSL_NUM_LAWS 32
351#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi3e0529f2011-11-21 17:10:22 -0600[diff] [blame]352#define CONFIG_FSL_SATA_V2
Kumar Galafbee0f72011-01-25 12:42:32 -0600[diff] [blame]353#define CONFIG_SYS_NUM_FMAN 1
354#define CONFIG_SYS_NUM_FM1_DTSEC 5
355#define CONFIG_SYS_NUM_FM1_10GEC 1
356#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]357#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600[diff] [blame]358#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]359#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]360#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang86221f02011-04-13 00:08:51 -0500[diff] [blame]361#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
362#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500[diff] [blame]363#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu30009762011-04-19 15:28:41 +0800[diff] [blame]364#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun57125f22012-08-08 18:04:53 +0000[diff] [blame]365#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala43f082b2011-11-22 06:51:15 -0600[diff] [blame]366#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun41085082011-11-20 10:01:35 -0800[diff] [blame]367#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]368#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
369#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
370#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000[diff] [blame]371#define CONFIG_SYS_FSL_ERRATUM_A004510
372#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
373#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
374#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000[diff] [blame]375#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]376
Scott Wood3e978f52012-08-14 10:14:51 +0000[diff] [blame]377#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]378#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]379#define CONFIG_MAX_CPUS 8
Kumar Galab5c87532011-02-16 02:03:29 -0600[diff] [blame]380#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]381#define CONFIG_SYS_FSL_NUM_LAWS 32
382#define CONFIG_SYS_FSL_SEC_COMPAT 4
383#define CONFIG_SYS_NUM_FMAN 2
384#define CONFIG_SYS_NUM_FM1_DTSEC 4
385#define CONFIG_SYS_NUM_FM2_DTSEC 4
386#define CONFIG_SYS_NUM_FM1_10GEC 1
387#define CONFIG_SYS_NUM_FM2_10GEC 1
388#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]389#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600[diff] [blame]390#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]391#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]392#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]393#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
394#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sunfa8d23c2011-01-10 12:03:01 +0000[diff] [blame]395#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]396#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
397#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
398#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
Zang Roy-R619114e0be342012-09-18 09:50:08 +0000[diff] [blame]399#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]400#define CONFIG_SYS_P4080_ERRATUM_CPU22
York Sun5e23ab02012-05-07 07:26:47 +0000[diff] [blame]401#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]402#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medvedf8af0b2010-08-31 22:57:38 -0500[diff] [blame]403#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabid90fdba2011-04-18 17:16:00 -0500[diff] [blame]404#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabida30b9f2011-04-01 13:19:36 -0500[diff] [blame]405#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Gala43f082b2011-11-22 06:51:15 -0600[diff] [blame]406#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun41085082011-11-20 10:01:35 -0800[diff] [blame]407#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]408#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
409#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
410#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
411#define CONFIG_SYS_FSL_RMU
412#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Scott Wood33eee332012-08-14 10:14:53 +0000[diff] [blame]413#define CONFIG_SYS_FSL_ERRATUM_A004510
414#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
415#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
Liu Gangd59c5572012-09-28 21:26:19 +0000[diff] [blame]416#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]417
Scott Wood3e978f52012-08-14 10:14:51 +0000[diff] [blame]418#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]419#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]420#define CONFIG_MAX_CPUS 2
Kumar Galab5c87532011-02-16 02:03:29 -0600[diff] [blame]421#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]422#define CONFIG_SYS_FSL_NUM_LAWS 32
423#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi3e0529f2011-11-21 17:10:22 -0600[diff] [blame]424#define CONFIG_FSL_SATA_V2
Kumar Galafbee0f72011-01-25 12:42:32 -0600[diff] [blame]425#define CONFIG_SYS_NUM_FMAN 1
426#define CONFIG_SYS_NUM_FM1_DTSEC 5
427#define CONFIG_SYS_NUM_FM1_10GEC 1
428#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]429#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600[diff] [blame]430#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]431#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]432#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang86221f02011-04-13 00:08:51 -0500[diff] [blame]433#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
434#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500[diff] [blame]435#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu30009762011-04-19 15:28:41 +0800[diff] [blame]436#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun41085082011-11-20 10:01:35 -0800[diff] [blame]437#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]438#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
439#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
440#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000[diff] [blame]441#define CONFIG_SYS_FSL_ERRATUM_A004510
442#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
443#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000[diff] [blame]444#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]445
Timur Tabi49054432012-10-05 11:09:19 +0000[diff] [blame]446#elif defined(CONFIG_PPC_P5040)
447#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
448#define CONFIG_MAX_CPUS 4
449#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
450#define CONFIG_SYS_FSL_NUM_LAWS 32
451#define CONFIG_SYS_FSL_SEC_COMPAT 4
452#define CONFIG_SYS_NUM_FMAN 2
453#define CONFIG_SYS_NUM_FM1_DTSEC 5
454#define CONFIG_SYS_NUM_FM1_10GEC 1
455#define CONFIG_SYS_NUM_FM2_DTSEC 5
456#define CONFIG_SYS_NUM_FM2_10GEC 1
457#define CONFIG_NUM_DDR_CONTROLLERS 2
458#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
459#define CONFIG_SYS_FSL_TBCLK_DIV 16
460#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
461#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
462#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
463#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
464#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
465#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
466#define CONFIG_SYS_FSL_ERRATUM_USB138
467#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
468#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
469#define CONFIG_SYS_FSL_ERRATUM_A004699
470#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
471#define CONFIG_SYS_FSL_ERRATUM_A004510
472#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
473#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
474
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000[diff] [blame]475#elif defined(CONFIG_BSC9131)
476#define CONFIG_MAX_CPUS 1
477#define CONFIG_FSL_SDHC_V2_3
478#define CONFIG_SYS_FSL_NUM_LAWS 12
479#define CONFIG_TSECV2
480#define CONFIG_SYS_FSL_SEC_COMPAT 4
481#define CONFIG_NUM_DDR_CONTROLLERS 1
482#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
483#define CONFIG_NAND_FSL_IFC
484#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
485#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
486
York Sun9e758752012-10-08 07:44:19 +0000[diff] [blame]487#elif defined(CONFIG_PPC_T4240)
488#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
489#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
490#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
491#define CONFIG_MAX_CPUS 12
492#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
493#define CONFIG_SYS_FSL_NUM_LAWS 32
494#define CONFIG_SYS_FSL_SRDS_3
495#define CONFIG_SYS_FSL_SRDS_4
496#define CONFIG_SYS_FSL_SEC_COMPAT 4
497#define CONFIG_SYS_NUM_FMAN 2
498#define CONFIG_SYS_NUM_FM1_DTSEC 8
499#define CONFIG_SYS_NUM_FM1_10GEC 2
500#define CONFIG_SYS_NUM_FM2_DTSEC 8
501#define CONFIG_SYS_NUM_FM2_10GEC 2
502#define CONFIG_NUM_DDR_CONTROLLERS 3
503#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Roy Zang111fd192012-10-08 07:44:21 +0000[diff] [blame]504#define CONFIG_SYS_FMAN_V3
York Sun9e758752012-10-08 07:44:19 +0000[diff] [blame]505#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
506#define CONFIG_SYS_FSL_TBCLK_DIV 16
507#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
508#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
509#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
510#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
511#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
512#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
513#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
514#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
515
York Sund2404142012-10-08 07:44:20 +0000[diff] [blame]516#elif defined(CONFIG_PPC_B4860)
517#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
518#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
519#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
520#define CONFIG_MAX_CPUS 4
521#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
522#define CONFIG_SYS_FSL_NUM_LAWS 32
523#define CONFIG_SYS_FSL_SEC_COMPAT 4
524#define CONFIG_SYS_NUM_FMAN 1
525#define CONFIG_SYS_NUM_FM1_DTSEC 6
526#define CONFIG_SYS_NUM_FM1_10GEC 2
527#define CONFIG_NUM_DDR_CONTROLLERS 1
528#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Roy Zang111fd192012-10-08 07:44:21 +0000[diff] [blame]529#define CONFIG_SYS_FMAN_V3
York Sund2404142012-10-08 07:44:20 +0000[diff] [blame]530#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
531#define CONFIG_SYS_FSL_TBCLK_DIV 16
532#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
533#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
534#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
535#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
536#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
537#define CONFIG_SYS_FSL_ERRATUM_A_004934
538#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
539
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]540#else
541#error Processor type not defined for this platform
542#endif
543
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]544#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
545#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
546#endif
547
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]548#endif /* _ASM_MPC85xx_CONFIG_H_ */