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gerrit.cesnet.cz / github / trini / u-boot / 3e0529f742e893653848494ffb9f7cd0d91304bf / . / arch / powerpc / include / asm / config_mpc85xx.h
blob: 8654625facc97619aec2707ecb8910f1c31e74f5 [file] [log] [blame]
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 */
20
21#ifndef _ASM_MPC85xx_CONFIG_H_
22#define _ASM_MPC85xx_CONFIG_H_
23
24/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
25
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]26#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
27#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
28#endif
29
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]30/* Number of TLB CAM entries we have on FSL Book-E chips */
31#if defined(CONFIG_E500MC)
32#define CONFIG_SYS_NUM_TLBCAMS 64
33#elif defined(CONFIG_E500)
34#define CONFIG_SYS_NUM_TLBCAMS 16
35#endif
36
37#if defined(CONFIG_MPC8536)
38#define CONFIG_MAX_CPUS 1
39#define CONFIG_SYS_FSL_NUM_LAWS 12
40#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]41#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]42
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100[diff] [blame]43#elif defined(CONFIG_MPC8540)
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]44#define CONFIG_MAX_CPUS 1
45#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]46#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]47
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100[diff] [blame]48#elif defined(CONFIG_MPC8541)
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]49#define CONFIG_MAX_CPUS 1
50#define CONFIG_SYS_FSL_NUM_LAWS 8
51#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]52#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]53
54#elif defined(CONFIG_MPC8544)
55#define CONFIG_MAX_CPUS 1
56#define CONFIG_SYS_FSL_NUM_LAWS 10
57#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]58#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]59
60#elif defined(CONFIG_MPC8548)
61#define CONFIG_MAX_CPUS 1
62#define CONFIG_SYS_FSL_NUM_LAWS 10
63#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]64#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala5ace2992011-09-16 09:54:30 -0500[diff] [blame]65#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
Kumar Gala2b3a1cd2011-10-03 08:37:57 -0500[diff] [blame]66#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
chenhui zhaoaada81d2011-10-03 08:38:50 -0500[diff] [blame]67#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]68
69#elif defined(CONFIG_MPC8555)
70#define CONFIG_MAX_CPUS 1
71#define CONFIG_SYS_FSL_NUM_LAWS 8
72#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]73#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]74
75#elif defined(CONFIG_MPC8560)
76#define CONFIG_MAX_CPUS 1
77#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]78#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]79
80#elif defined(CONFIG_MPC8568)
81#define CONFIG_MAX_CPUS 1
82#define CONFIG_SYS_FSL_NUM_LAWS 10
83#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galafdb4dad2011-01-31 23:09:25 -0600[diff] [blame]84#define QE_MURAM_SIZE 0x10000UL
85#define MAX_QE_RISC 2
86#define QE_NUM_OF_SNUM 28
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]87#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]88
89#elif defined(CONFIG_MPC8569)
90#define CONFIG_MAX_CPUS 1
91#define CONFIG_SYS_FSL_NUM_LAWS 10
92#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galafdb4dad2011-01-31 23:09:25 -0600[diff] [blame]93#define QE_MURAM_SIZE 0x20000UL
94#define MAX_QE_RISC 4
95#define QE_NUM_OF_SNUM 46
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]96#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]97
98#elif defined(CONFIG_MPC8572)
99#define CONFIG_MAX_CPUS 2
100#define CONFIG_SYS_FSL_NUM_LAWS 12
101#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]102#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Suneb0aff72011-01-25 21:51:27 -0800[diff] [blame]103#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sun91671912011-01-25 22:05:49 -0800[diff] [blame]104#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]105
106#elif defined(CONFIG_P1010)
107#define CONFIG_MAX_CPUS 1
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530[diff] [blame]108#define CONFIG_FSL_SDHC_V2_3
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]109#define CONFIG_SYS_FSL_NUM_LAWS 12
110#define CONFIG_TSECV2
111#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530[diff] [blame]112#define CONFIG_FSL_SATA_V2
113#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
114#define CONFIG_NUM_DDR_CONTROLLERS 1
115#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]116#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530[diff] [blame]117#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal42aee642011-06-30 03:00:28 -0500[diff] [blame]118#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalfb855f42011-06-29 16:32:52 +0530[diff] [blame]119#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwalbc6bbd62011-07-07 20:36:47 +0530[diff] [blame]120#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]121
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]122/* P1011 is single core version of P1020 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]123#elif defined(CONFIG_P1011)
124#define CONFIG_MAX_CPUS 1
125#define CONFIG_SYS_FSL_NUM_LAWS 12
126#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000[diff] [blame]127#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]128#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]129#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]130#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
131#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]132
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]133/* P1012 is single core version of P1021 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]134#elif defined(CONFIG_P1012)
135#define CONFIG_MAX_CPUS 1
136#define CONFIG_SYS_FSL_NUM_LAWS 12
137#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000[diff] [blame]138#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]139#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]140#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]141#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
142#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600[diff] [blame]143#define QE_MURAM_SIZE 0x6000UL
144#define MAX_QE_RISC 1
145#define QE_NUM_OF_SNUM 28
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]146
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]147/* P1013 is single core version of P1022 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]148#elif defined(CONFIG_P1013)
149#define CONFIG_MAX_CPUS 1
150#define CONFIG_SYS_FSL_NUM_LAWS 12
151#define CONFIG_TSECV2
152#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi3e0529f2011-11-21 17:10:22 -0600[diff] [blame^]153#define CONFIG_FSL_SATA_V2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]154#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang2d7534a2011-01-30 17:06:20 -0600[diff] [blame]155#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
156#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
157#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]158
159#elif defined(CONFIG_P1014)
160#define CONFIG_MAX_CPUS 1
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530[diff] [blame]161#define CONFIG_FSL_SDHC_V2_3
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]162#define CONFIG_SYS_FSL_NUM_LAWS 12
163#define CONFIG_TSECV2
164#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530[diff] [blame]165#define CONFIG_FSL_SATA_V2
166#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
167#define CONFIG_NUM_DDR_CONTROLLERS 1
168#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530[diff] [blame]169#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal42aee642011-06-30 03:00:28 -0500[diff] [blame]170#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalfb855f42011-06-29 16:32:52 +0530[diff] [blame]171#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwalbc6bbd62011-07-07 20:36:47 +0530[diff] [blame]172#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]173
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]174/* P1015 is single core version of P1024 */
175#elif defined(CONFIG_P1015)
176#define CONFIG_MAX_CPUS 1
177#define CONFIG_SYS_FSL_NUM_LAWS 12
178#define CONFIG_TSECV2
179#define CONFIG_FSL_PCIE_DISABLE_ASPM
180#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]181#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]182#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
183#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
184
185/* P1016 is single core version of P1025 */
186#elif defined(CONFIG_P1016)
187#define CONFIG_MAX_CPUS 1
188#define CONFIG_SYS_FSL_NUM_LAWS 12
189#define CONFIG_TSECV2
190#define CONFIG_FSL_PCIE_DISABLE_ASPM
191#define CONFIG_SYS_FSL_SEC_COMPAT 2
192#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
193#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600[diff] [blame]194#define QE_MURAM_SIZE 0x6000UL
195#define MAX_QE_RISC 1
196#define QE_NUM_OF_SNUM 28
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]197#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]198
199/* P1017 is single core version of P1023 */
Roy Zang67a719d2011-02-03 22:14:19 -0600[diff] [blame]200#elif defined(CONFIG_P1017)
201#define CONFIG_MAX_CPUS 1
202#define CONFIG_SYS_FSL_NUM_LAWS 12
203#define CONFIG_SYS_FSL_SEC_COMPAT 4
204#define CONFIG_SYS_NUM_FMAN 1
205#define CONFIG_SYS_NUM_FM1_DTSEC 2
206#define CONFIG_NUM_DDR_CONTROLLERS 1
207#define CONFIG_SYS_QMAN_NUM_PORTALS 3
208#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]209#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]210#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]211#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang67a719d2011-02-03 22:14:19 -0600[diff] [blame]212
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]213#elif defined(CONFIG_P1020)
214#define CONFIG_MAX_CPUS 2
215#define CONFIG_SYS_FSL_NUM_LAWS 12
216#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000[diff] [blame]217#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]218#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]219#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]220#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
221#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]222
223#elif defined(CONFIG_P1021)
224#define CONFIG_MAX_CPUS 2
225#define CONFIG_SYS_FSL_NUM_LAWS 12
226#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000[diff] [blame]227#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]228#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]229#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]230#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
231#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600[diff] [blame]232#define QE_MURAM_SIZE 0x6000UL
233#define MAX_QE_RISC 1
234#define QE_NUM_OF_SNUM 28
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]235
236#elif defined(CONFIG_P1022)
237#define CONFIG_MAX_CPUS 2
238#define CONFIG_SYS_FSL_NUM_LAWS 12
239#define CONFIG_TSECV2
240#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi3e0529f2011-11-21 17:10:22 -0600[diff] [blame^]241#define CONFIG_FSL_SATA_V2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]242#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang2d7534a2011-01-30 17:06:20 -0600[diff] [blame]243#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
244#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
245#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]246
Roy Zang67a719d2011-02-03 22:14:19 -0600[diff] [blame]247#elif defined(CONFIG_P1023)
248#define CONFIG_MAX_CPUS 2
249#define CONFIG_SYS_FSL_NUM_LAWS 12
250#define CONFIG_SYS_FSL_SEC_COMPAT 4
251#define CONFIG_SYS_NUM_FMAN 1
252#define CONFIG_SYS_NUM_FM1_DTSEC 2
253#define CONFIG_NUM_DDR_CONTROLLERS 1
254#define CONFIG_SYS_QMAN_NUM_PORTALS 3
255#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]256#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]257#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]258#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang67a719d2011-02-03 22:14:19 -0600[diff] [blame]259
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]260/* P1024 is lower end variant of P1020 */
261#elif defined(CONFIG_P1024)
262#define CONFIG_MAX_CPUS 2
263#define CONFIG_SYS_FSL_NUM_LAWS 12
264#define CONFIG_TSECV2
265#define CONFIG_FSL_PCIE_DISABLE_ASPM
266#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]267#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]268#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
269#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
270
271/* P1025 is lower end variant of P1021 */
272#elif defined(CONFIG_P1025)
273#define CONFIG_MAX_CPUS 2
274#define CONFIG_SYS_FSL_NUM_LAWS 12
275#define CONFIG_TSECV2
276#define CONFIG_FSL_PCIE_DISABLE_ASPM
277#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]278#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]279#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
280#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600[diff] [blame]281#define QE_MURAM_SIZE 0x6000UL
282#define MAX_QE_RISC 1
283#define QE_NUM_OF_SNUM 28
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]284
285/* P2010 is single core version of P2020 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]286#elif defined(CONFIG_P2010)
287#define CONFIG_MAX_CPUS 1
288#define CONFIG_SYS_FSL_NUM_LAWS 12
289#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]290#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala6e7f0bc02011-01-26 01:43:15 -0600[diff] [blame]291#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala5103a032011-01-29 15:36:10 -0600[diff] [blame]292#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]293
294#elif defined(CONFIG_P2020)
295#define CONFIG_MAX_CPUS 2
296#define CONFIG_SYS_FSL_NUM_LAWS 12
297#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]298#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala6e7f0bc02011-01-26 01:43:15 -0600[diff] [blame]299#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala5103a032011-01-29 15:36:10 -0600[diff] [blame]300#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]301
302#elif defined(CONFIG_PPC_P2040)
303#define CONFIG_MAX_CPUS 4
Kumar Galab5c87532011-02-16 02:03:29 -0600[diff] [blame]304#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]305#define CONFIG_SYS_FSL_NUM_LAWS 32
306#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galafbee0f72011-01-25 12:42:32 -0600[diff] [blame]307#define CONFIG_SYS_NUM_FMAN 1
308#define CONFIG_SYS_NUM_FM1_DTSEC 5
309#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]310#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600[diff] [blame]311#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]312#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]313#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang86221f02011-04-13 00:08:51 -0500[diff] [blame]314#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
315#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500[diff] [blame]316#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu30009762011-04-19 15:28:41 +0800[diff] [blame]317#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala43f082b2011-11-22 06:51:15 -0600[diff] [blame]318#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun41085082011-11-20 10:01:35 -0800[diff] [blame]319#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]320
Kumar Gala1f979872011-05-13 01:16:07 -0500[diff] [blame]321#elif defined(CONFIG_PPC_P2041)
322#define CONFIG_MAX_CPUS 4
323#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
324#define CONFIG_SYS_FSL_NUM_LAWS 32
325#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi3e0529f2011-11-21 17:10:22 -0600[diff] [blame^]326#define CONFIG_FSL_SATA_V2
Kumar Gala1f979872011-05-13 01:16:07 -0500[diff] [blame]327#define CONFIG_SYS_NUM_FMAN 1
328#define CONFIG_SYS_NUM_FM1_DTSEC 5
329#define CONFIG_SYS_NUM_FM1_10GEC 1
330#define CONFIG_NUM_DDR_CONTROLLERS 1
331#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
332#define CONFIG_SYS_FSL_TBCLK_DIV 32
333#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]334#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala1f979872011-05-13 01:16:07 -0500[diff] [blame]335#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
336#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500[diff] [blame]337#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala1f979872011-05-13 01:16:07 -0500[diff] [blame]338#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala43f082b2011-11-22 06:51:15 -0600[diff] [blame]339#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun41085082011-11-20 10:01:35 -0800[diff] [blame]340#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Kumar Gala1f979872011-05-13 01:16:07 -0500[diff] [blame]341
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]342#elif defined(CONFIG_PPC_P3041)
343#define CONFIG_MAX_CPUS 4
Kumar Galab5c87532011-02-16 02:03:29 -0600[diff] [blame]344#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]345#define CONFIG_SYS_FSL_NUM_LAWS 32
346#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi3e0529f2011-11-21 17:10:22 -0600[diff] [blame^]347#define CONFIG_FSL_SATA_V2
Kumar Galafbee0f72011-01-25 12:42:32 -0600[diff] [blame]348#define CONFIG_SYS_NUM_FMAN 1
349#define CONFIG_SYS_NUM_FM1_DTSEC 5
350#define CONFIG_SYS_NUM_FM1_10GEC 1
351#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]352#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600[diff] [blame]353#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]354#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]355#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang86221f02011-04-13 00:08:51 -0500[diff] [blame]356#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
357#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500[diff] [blame]358#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu30009762011-04-19 15:28:41 +0800[diff] [blame]359#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala43f082b2011-11-22 06:51:15 -0600[diff] [blame]360#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun41085082011-11-20 10:01:35 -0800[diff] [blame]361#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]362
Shengzhou Liu6d7b0612011-08-31 17:48:18 +0800[diff] [blame]363#elif defined(CONFIG_PPC_P3060)
364#define CONFIG_MAX_CPUS 8
365#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
366#define CONFIG_SYS_FSL_NUM_LAWS 32
367#define CONFIG_SYS_FSL_SEC_COMPAT 4
368#define CONFIG_SYS_NUM_FMAN 2
369#define CONFIG_SYS_NUM_FM1_DTSEC 4
370#define CONFIG_SYS_NUM_FM2_DTSEC 4
371#define CONFIG_NUM_DDR_CONTROLLERS 1
372#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
373#define CONFIG_SYS_FSL_TBCLK_DIV 16
374#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
375#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
376#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Gala43f082b2011-11-22 06:51:15 -0600[diff] [blame]377#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
Shengzhou Liu6d7b0612011-08-31 17:48:18 +0800[diff] [blame]378
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]379#elif defined(CONFIG_PPC_P4040)
380#define CONFIG_MAX_CPUS 4
Kumar Galab5c87532011-02-16 02:03:29 -0600[diff] [blame]381#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]382#define CONFIG_SYS_FSL_NUM_LAWS 32
383#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]384#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600[diff] [blame]385#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]386#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]387#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala43f082b2011-11-22 06:51:15 -0600[diff] [blame]388#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun41085082011-11-20 10:01:35 -0800[diff] [blame]389#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]390
391#elif defined(CONFIG_PPC_P4080)
392#define CONFIG_MAX_CPUS 8
Kumar Galab5c87532011-02-16 02:03:29 -0600[diff] [blame]393#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]394#define CONFIG_SYS_FSL_NUM_LAWS 32
395#define CONFIG_SYS_FSL_SEC_COMPAT 4
396#define CONFIG_SYS_NUM_FMAN 2
397#define CONFIG_SYS_NUM_FM1_DTSEC 4
398#define CONFIG_SYS_NUM_FM2_DTSEC 4
399#define CONFIG_SYS_NUM_FM1_10GEC 1
400#define CONFIG_SYS_NUM_FM2_10GEC 1
401#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]402#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600[diff] [blame]403#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]404#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]405#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]406#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
407#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sunfa8d23c2011-01-10 12:03:01 +0000[diff] [blame]408#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]409#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
410#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
411#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
412#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
413#define CONFIG_SYS_P4080_ERRATUM_CPU22
414#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medvedf8af0b2010-08-31 22:57:38 -0500[diff] [blame]415#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabid90fdba2011-04-18 17:16:00 -0500[diff] [blame]416#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabida30b9f2011-04-01 13:19:36 -0500[diff] [blame]417#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Gala43f082b2011-11-22 06:51:15 -0600[diff] [blame]418#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun41085082011-11-20 10:01:35 -0800[diff] [blame]419#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]420
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]421/* P5010 is single core version of P5020 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]422#elif defined(CONFIG_PPC_P5010)
423#define CONFIG_MAX_CPUS 1
Kumar Galab5c87532011-02-16 02:03:29 -0600[diff] [blame]424#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]425#define CONFIG_SYS_FSL_NUM_LAWS 32
426#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi3e0529f2011-11-21 17:10:22 -0600[diff] [blame^]427#define CONFIG_FSL_SATA_V2
Kumar Galafbee0f72011-01-25 12:42:32 -0600[diff] [blame]428#define CONFIG_SYS_NUM_FMAN 1
429#define CONFIG_SYS_NUM_FM1_DTSEC 5
430#define CONFIG_SYS_NUM_FM1_10GEC 1
431#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]432#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600[diff] [blame]433#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]434#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]435#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang86221f02011-04-13 00:08:51 -0500[diff] [blame]436#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
437#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500[diff] [blame]438#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu30009762011-04-19 15:28:41 +0800[diff] [blame]439#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun41085082011-11-20 10:01:35 -0800[diff] [blame]440#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]441
442#elif defined(CONFIG_PPC_P5020)
443#define CONFIG_MAX_CPUS 2
Kumar Galab5c87532011-02-16 02:03:29 -0600[diff] [blame]444#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]445#define CONFIG_SYS_FSL_NUM_LAWS 32
446#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi3e0529f2011-11-21 17:10:22 -0600[diff] [blame^]447#define CONFIG_FSL_SATA_V2
Kumar Galafbee0f72011-01-25 12:42:32 -0600[diff] [blame]448#define CONFIG_SYS_NUM_FMAN 1
449#define CONFIG_SYS_NUM_FM1_DTSEC 5
450#define CONFIG_SYS_NUM_FM1_10GEC 1
451#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]452#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600[diff] [blame]453#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]454#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]455#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang86221f02011-04-13 00:08:51 -0500[diff] [blame]456#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
457#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500[diff] [blame]458#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu30009762011-04-19 15:28:41 +0800[diff] [blame]459#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun41085082011-11-20 10:01:35 -0800[diff] [blame]460#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]461
462#else
463#error Processor type not defined for this platform
464#endif
465
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]466#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
467#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
468#endif
469
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]470#endif /* _ASM_MPC85xx_CONFIG_H_ */