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Kumar Gala243be8e2011-01-19 03:05:26 -06001/*
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +00002 * Copyright 2011-2012 Freescale Semiconductor, Inc.
Kumar Gala243be8e2011-01-19 03:05:26 -06003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala243be8e2011-01-19 03:05:26 -06005 */
6
7#ifndef _ASM_MPC85xx_CONFIG_H_
8#define _ASM_MPC85xx_CONFIG_H_
9
10/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
11
Timur Tabie46fedf2011-08-04 18:03:41 -050012#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
13#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
14#endif
15
York Sun2a5fcb82012-10-28 08:12:54 +000016/*
17 * This macro should be removed when we no longer care about backwards
18 * compatibility with older operating systems.
19 */
20#define CONFIG_PPC_SPINTABLE_COMPATIBLE
21
York Sun34e026f2014-03-27 17:54:47 -070022#include <fsl_ddrc_version.h>
23#define CONFIG_SYS_FSL_DDR_BE
York Sun57495e42012-10-08 07:44:22 +000024
Prabhakar Kushwaha1b4175d2014-01-18 12:28:30 +053025/* IP endianness */
26#define CONFIG_SYS_FSL_IFC_BE
27
Kumar Gala243be8e2011-01-19 03:05:26 -060028/* Number of TLB CAM entries we have on FSL Book-E chips */
29#if defined(CONFIG_E500MC)
30#define CONFIG_SYS_NUM_TLBCAMS 64
31#elif defined(CONFIG_E500)
32#define CONFIG_SYS_NUM_TLBCAMS 16
33#endif
34
35#if defined(CONFIG_MPC8536)
36#define CONFIG_MAX_CPUS 1
37#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +000038#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
Kumar Gala243be8e2011-01-19 03:05:26 -060039#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -050040#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun954a1a42013-08-20 15:09:43 -070041#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -060042
Wolfgang Denkd1a24f02011-02-02 22:36:10 +010043#elif defined(CONFIG_MPC8540)
Kumar Gala243be8e2011-01-19 03:05:26 -060044#define CONFIG_MAX_CPUS 1
45#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -070046#define CONFIG_SYS_FSL_DDRC_GEN1
Timur Tabie46fedf2011-08-04 18:03:41 -050047#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -060048
Wolfgang Denkd1a24f02011-02-02 22:36:10 +010049#elif defined(CONFIG_MPC8541)
Kumar Gala243be8e2011-01-19 03:05:26 -060050#define CONFIG_MAX_CPUS 1
51#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -070052#define CONFIG_SYS_FSL_DDRC_GEN1
Kumar Gala243be8e2011-01-19 03:05:26 -060053#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -050054#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -060055
56#elif defined(CONFIG_MPC8544)
57#define CONFIG_MAX_CPUS 1
58#define CONFIG_SYS_FSL_NUM_LAWS 10
York Sun5614e712013-09-30 09:22:09 -070059#define CONFIG_SYS_FSL_DDRC_GEN2
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +000060#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala243be8e2011-01-19 03:05:26 -060061#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -050062#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun954a1a42013-08-20 15:09:43 -070063#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -060064
65#elif defined(CONFIG_MPC8548)
66#define CONFIG_MAX_CPUS 1
67#define CONFIG_SYS_FSL_NUM_LAWS 10
York Sun5614e712013-09-30 09:22:09 -070068#define CONFIG_SYS_FSL_DDRC_GEN2
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +000069#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala243be8e2011-01-19 03:05:26 -060070#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -050071#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala5ace2992011-09-16 09:54:30 -050072#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
Kumar Gala2b3a1cd2011-10-03 08:37:57 -050073#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
chenhui zhaoaada81d2011-10-03 08:38:50 -050074#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
Liu Gang7d67ed52012-03-08 00:33:14 +000075#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
76#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
77#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
78#define CONFIG_SYS_FSL_RMU
79#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun954a1a42013-08-20 15:09:43 -070080#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan9c3f77e2013-08-16 15:10:37 +080081#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
82#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
Kumar Gala243be8e2011-01-19 03:05:26 -060083
84#elif defined(CONFIG_MPC8555)
85#define CONFIG_MAX_CPUS 1
86#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -070087#define CONFIG_SYS_FSL_DDRC_GEN1
Kumar Gala243be8e2011-01-19 03:05:26 -060088#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -050089#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -060090
91#elif defined(CONFIG_MPC8560)
92#define CONFIG_MAX_CPUS 1
93#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -070094#define CONFIG_SYS_FSL_DDRC_GEN1
Timur Tabie46fedf2011-08-04 18:03:41 -050095#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -060096
97#elif defined(CONFIG_MPC8568)
98#define CONFIG_MAX_CPUS 1
99#define CONFIG_SYS_FSL_NUM_LAWS 10
York Sun5614e712013-09-30 09:22:09 -0700100#define CONFIG_SYS_FSL_DDRC_GEN2
Kumar Gala243be8e2011-01-19 03:05:26 -0600101#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galafdb4dad2011-01-31 23:09:25 -0600102#define QE_MURAM_SIZE 0x10000UL
103#define MAX_QE_RISC 2
104#define QE_NUM_OF_SNUM 28
Timur Tabie46fedf2011-08-04 18:03:41 -0500105#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang7d67ed52012-03-08 00:33:14 +0000106#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
107#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
108#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
109#define CONFIG_SYS_FSL_RMU
110#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600111
112#elif defined(CONFIG_MPC8569)
113#define CONFIG_MAX_CPUS 1
114#define CONFIG_SYS_FSL_NUM_LAWS 10
115#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galafdb4dad2011-01-31 23:09:25 -0600116#define QE_MURAM_SIZE 0x20000UL
117#define MAX_QE_RISC 4
118#define QE_NUM_OF_SNUM 46
Timur Tabie46fedf2011-08-04 18:03:41 -0500119#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang7d67ed52012-03-08 00:33:14 +0000120#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
121#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
122#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
123#define CONFIG_SYS_FSL_RMU
124#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun954a1a42013-08-20 15:09:43 -0700125#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600126
127#elif defined(CONFIG_MPC8572)
128#define CONFIG_MAX_CPUS 2
129#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +0000130#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600131#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500132#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Suneb0aff72011-01-25 21:51:27 -0800133#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sun91671912011-01-25 22:05:49 -0800134#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
York Sun954a1a42013-08-20 15:09:43 -0700135#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600136
137#elif defined(CONFIG_P1010)
138#define CONFIG_MAX_CPUS 1
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530139#define CONFIG_FSL_SDHC_V2_3
Kumar Gala243be8e2011-01-19 03:05:26 -0600140#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000141#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala243be8e2011-01-19 03:05:26 -0600142#define CONFIG_TSECV2
143#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530144#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
145#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530146#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Mingkai Hu362ee042013-05-16 10:18:13 +0800147#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530148#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala8f290842011-05-20 00:39:21 -0500149#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530150#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal42aee642011-06-30 03:00:28 -0500151#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalfb855f42011-06-29 16:32:52 +0530152#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Shengzhou Liu424bf942013-08-15 09:31:47 +0800153#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
Poonam Aggrwalbc6bbd62011-07-07 20:36:47 +0530154#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
York Sun954a1a42013-08-20 15:09:43 -0700155#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800156#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Suresh Gupta9c641a82014-02-26 14:29:12 +0530157#define CONFIG_SYS_FSL_ERRATUM_A006261
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800158#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
Haijun.Zhangf28bea02014-01-10 13:52:19 +0800159#define CONFIG_ESDHC_HC_BLK_ADDR
Kumar Gala243be8e2011-01-19 03:05:26 -0600160
Kumar Gala093cffb2011-02-05 13:45:07 -0600161/* P1011 is single core version of P1020 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600162#elif defined(CONFIG_P1011)
163#define CONFIG_MAX_CPUS 1
164#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000165#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600166#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000167#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600168#define CONFIG_SYS_FSL_SEC_COMPAT 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530169#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500170#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600171#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
172#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun954a1a42013-08-20 15:09:43 -0700173#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600174
Kumar Gala093cffb2011-02-05 13:45:07 -0600175/* P1012 is single core version of P1021 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600176#elif defined(CONFIG_P1012)
177#define CONFIG_MAX_CPUS 1
178#define CONFIG_SYS_FSL_NUM_LAWS 12
ramneek mehreshf1810d82013-10-18 17:40:17 +0530179#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000180#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600181#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000182#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600183#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500184#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600185#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
186#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600187#define QE_MURAM_SIZE 0x6000UL
188#define MAX_QE_RISC 1
189#define QE_NUM_OF_SNUM 28
York Sun954a1a42013-08-20 15:09:43 -0700190#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600191
Kumar Gala093cffb2011-02-05 13:45:07 -0600192/* P1013 is single core version of P1022 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600193#elif defined(CONFIG_P1013)
194#define CONFIG_MAX_CPUS 1
195#define CONFIG_SYS_FSL_NUM_LAWS 12
ramneek mehreshf1810d82013-10-18 17:40:17 +0530196#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000197#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600198#define CONFIG_TSECV2
199#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500200#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang2d7534a2011-01-30 17:06:20 -0600201#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
202#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
203#define CONFIG_FSL_SATA_ERRATUM_A001
York Sun954a1a42013-08-20 15:09:43 -0700204#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600205
206#elif defined(CONFIG_P1014)
207#define CONFIG_MAX_CPUS 1
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530208#define CONFIG_FSL_SDHC_V2_3
Kumar Gala243be8e2011-01-19 03:05:26 -0600209#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000210#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala243be8e2011-01-19 03:05:26 -0600211#define CONFIG_TSECV2
212#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530213#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
214#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530215#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530216#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530217#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal42aee642011-06-30 03:00:28 -0500218#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalfb855f42011-06-29 16:32:52 +0530219#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwalbc6bbd62011-07-07 20:36:47 +0530220#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Gala243be8e2011-01-19 03:05:26 -0600221
Kumar Gala093cffb2011-02-05 13:45:07 -0600222/* P1017 is single core version of P1023 */
Roy Zang67a719d2011-02-03 22:14:19 -0600223#elif defined(CONFIG_P1017)
224#define CONFIG_MAX_CPUS 1
225#define CONFIG_SYS_FSL_NUM_LAWS 12
226#define CONFIG_SYS_FSL_SEC_COMPAT 4
227#define CONFIG_SYS_NUM_FMAN 1
228#define CONFIG_SYS_NUM_FM1_DTSEC 2
229#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530230#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Roy Zang67a719d2011-02-03 22:14:19 -0600231#define CONFIG_SYS_QMAN_NUM_PORTALS 3
232#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galac657d892011-02-04 00:43:34 -0600233#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala8f290842011-05-20 00:39:21 -0500234#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500235#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
York Sun954a1a42013-08-20 15:09:43 -0700236#define CONFIG_SYS_FSL_ERRATUM_A005125
Roy Zang67a719d2011-02-03 22:14:19 -0600237
Kumar Gala243be8e2011-01-19 03:05:26 -0600238#elif defined(CONFIG_P1020)
239#define CONFIG_MAX_CPUS 2
240#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000241#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600242#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000243#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600244#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500245#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600246#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
247#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun954a1a42013-08-20 15:09:43 -0700248#define CONFIG_SYS_FSL_ERRATUM_A005125
ramneek mehreshf1810d82013-10-18 17:40:17 +0530249#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600250
251#elif defined(CONFIG_P1021)
252#define CONFIG_MAX_CPUS 2
253#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000254#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600255#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000256#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600257#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500258#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600259#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
260#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600261#define QE_MURAM_SIZE 0x6000UL
262#define MAX_QE_RISC 1
263#define QE_NUM_OF_SNUM 28
York Sun954a1a42013-08-20 15:09:43 -0700264#define CONFIG_SYS_FSL_ERRATUM_A005125
ramneek mehreshf1810d82013-10-18 17:40:17 +0530265#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Kumar Gala243be8e2011-01-19 03:05:26 -0600266
267#elif defined(CONFIG_P1022)
268#define CONFIG_MAX_CPUS 2
269#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000270#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600271#define CONFIG_TSECV2
272#define CONFIG_SYS_FSL_SEC_COMPAT 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530273#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500274#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang2d7534a2011-01-30 17:06:20 -0600275#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
276#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
277#define CONFIG_FSL_SATA_ERRATUM_A001
York Sun954a1a42013-08-20 15:09:43 -0700278#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600279
Roy Zang67a719d2011-02-03 22:14:19 -0600280#elif defined(CONFIG_P1023)
281#define CONFIG_MAX_CPUS 2
282#define CONFIG_SYS_FSL_NUM_LAWS 12
283#define CONFIG_SYS_FSL_SEC_COMPAT 4
284#define CONFIG_SYS_NUM_FMAN 1
285#define CONFIG_SYS_NUM_FM1_DTSEC 2
286#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530287#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Roy Zang67a719d2011-02-03 22:14:19 -0600288#define CONFIG_SYS_QMAN_NUM_PORTALS 3
289#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galac657d892011-02-04 00:43:34 -0600290#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala8f290842011-05-20 00:39:21 -0500291#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500292#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
York Sun954a1a42013-08-20 15:09:43 -0700293#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800294#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
295#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Roy Zang67a719d2011-02-03 22:14:19 -0600296
Kumar Gala093cffb2011-02-05 13:45:07 -0600297/* P1024 is lower end variant of P1020 */
298#elif defined(CONFIG_P1024)
299#define CONFIG_MAX_CPUS 2
300#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000301#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala093cffb2011-02-05 13:45:07 -0600302#define CONFIG_TSECV2
303#define CONFIG_FSL_PCIE_DISABLE_ASPM
304#define CONFIG_SYS_FSL_SEC_COMPAT 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530305#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500306#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600307#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
308#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun954a1a42013-08-20 15:09:43 -0700309#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala093cffb2011-02-05 13:45:07 -0600310
311/* P1025 is lower end variant of P1021 */
312#elif defined(CONFIG_P1025)
313#define CONFIG_MAX_CPUS 2
314#define CONFIG_SYS_FSL_NUM_LAWS 12
ramneek mehreshf1810d82013-10-18 17:40:17 +0530315#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000316#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala093cffb2011-02-05 13:45:07 -0600317#define CONFIG_TSECV2
318#define CONFIG_FSL_PCIE_DISABLE_ASPM
319#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500320#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600321#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
322#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600323#define QE_MURAM_SIZE 0x6000UL
324#define MAX_QE_RISC 1
325#define QE_NUM_OF_SNUM 28
York Sun954a1a42013-08-20 15:09:43 -0700326#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala093cffb2011-02-05 13:45:07 -0600327
328/* P2010 is single core version of P2020 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600329#elif defined(CONFIG_P2010)
330#define CONFIG_MAX_CPUS 1
331#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000332#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600333#define CONFIG_SYS_FSL_SEC_COMPAT 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530334#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Timur Tabie46fedf2011-08-04 18:03:41 -0500335#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala6e7f0bc02011-01-26 01:43:15 -0600336#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala5103a032011-01-29 15:36:10 -0600337#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
York Sun954a1a42013-08-20 15:09:43 -0700338#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600339
340#elif defined(CONFIG_P2020)
341#define CONFIG_MAX_CPUS 2
342#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000343#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600344#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500345#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala6e7f0bc02011-01-26 01:43:15 -0600346#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala5103a032011-01-29 15:36:10 -0600347#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Liu Gang7d67ed52012-03-08 00:33:14 +0000348#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
349#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
350#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
351#define CONFIG_SYS_FSL_RMU
352#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun954a1a42013-08-20 15:09:43 -0700353#define CONFIG_SYS_FSL_ERRATUM_A005125
ramneek mehreshf1810d82013-10-18 17:40:17 +0530354#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Scott Wood3e978f52012-08-14 10:14:51 +0000355#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
York Sund1001e32012-10-08 07:44:15 +0000356#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700357#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala1f979872011-05-13 01:16:07 -0500358#define CONFIG_MAX_CPUS 4
359#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
360#define CONFIG_SYS_FSL_NUM_LAWS 32
361#define CONFIG_SYS_FSL_SEC_COMPAT 4
362#define CONFIG_SYS_NUM_FMAN 1
363#define CONFIG_SYS_NUM_FM1_DTSEC 5
364#define CONFIG_SYS_NUM_FM1_10GEC 1
365#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530366#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Kumar Gala1f979872011-05-13 01:16:07 -0500367#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
368#define CONFIG_SYS_FSL_TBCLK_DIV 32
369#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500370#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala1f979872011-05-13 01:16:07 -0500371#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
372#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500373#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala1f979872011-05-13 01:16:07 -0500374#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun5e23ab02012-05-07 07:26:47 +0000375#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei99d7b0a2013-03-11 17:56:34 +0000376#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala43f082b2011-11-22 06:51:15 -0600377#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sune22be772013-03-25 07:30:11 +0000378#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun41085082011-11-20 10:01:35 -0800379#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000380#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
381#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
382#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000383#define CONFIG_SYS_FSL_ERRATUM_A004510
384#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
385#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
386#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000387#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi01180332012-10-25 12:40:00 +0000388#define CONFIG_SYS_FSL_ERRATUM_A004849
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800389#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Suresh Gupta9c641a82014-02-26 14:29:12 +0530390#define CONFIG_SYS_FSL_ERRATUM_A006261
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800391#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Kumar Gala1f979872011-05-13 01:16:07 -0500392
Kumar Gala243be8e2011-01-19 03:05:26 -0600393#elif defined(CONFIG_PPC_P3041)
York Sund1001e32012-10-08 07:44:15 +0000394#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700395#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala243be8e2011-01-19 03:05:26 -0600396#define CONFIG_MAX_CPUS 4
Kumar Galab5c87532011-02-16 02:03:29 -0600397#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600398#define CONFIG_SYS_FSL_NUM_LAWS 32
399#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galafbee0f72011-01-25 12:42:32 -0600400#define CONFIG_SYS_NUM_FMAN 1
401#define CONFIG_SYS_NUM_FM1_DTSEC 5
402#define CONFIG_SYS_NUM_FM1_10GEC 1
403#define CONFIG_NUM_DDR_CONTROLLERS 1
York Sun34e026f2014-03-27 17:54:47 -0700404#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
Kumar Galac657d892011-02-04 00:43:34 -0600405#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600406#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala8f290842011-05-20 00:39:21 -0500407#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500408#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang86221f02011-04-13 00:08:51 -0500409#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
410#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500411#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
ramneek mehreshf1810d82013-10-18 17:40:17 +0530412#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Lei Xu30009762011-04-19 15:28:41 +0800413#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun57125f22012-08-08 18:04:53 +0000414#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei99d7b0a2013-03-11 17:56:34 +0000415#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala43f082b2011-11-22 06:51:15 -0600416#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sune22be772013-03-25 07:30:11 +0000417#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun41085082011-11-20 10:01:35 -0800418#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000419#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
420#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
421#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000422#define CONFIG_SYS_FSL_ERRATUM_A004510
423#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
424#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
425#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000426#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi01180332012-10-25 12:40:00 +0000427#define CONFIG_SYS_FSL_ERRATUM_A004849
York Sund217a9a2013-06-25 11:37:49 -0700428#define CONFIG_SYS_FSL_ERRATUM_A005812
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800429#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Suresh Gupta9c641a82014-02-26 14:29:12 +0530430#define CONFIG_SYS_FSL_ERRATUM_A006261
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800431#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala243be8e2011-01-19 03:05:26 -0600432
Scott Wood3e978f52012-08-14 10:14:51 +0000433#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
York Sund1001e32012-10-08 07:44:15 +0000434#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700435#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala243be8e2011-01-19 03:05:26 -0600436#define CONFIG_MAX_CPUS 8
Kumar Galab5c87532011-02-16 02:03:29 -0600437#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Gala243be8e2011-01-19 03:05:26 -0600438#define CONFIG_SYS_FSL_NUM_LAWS 32
439#define CONFIG_SYS_FSL_SEC_COMPAT 4
440#define CONFIG_SYS_NUM_FMAN 2
441#define CONFIG_SYS_NUM_FM1_DTSEC 4
442#define CONFIG_SYS_NUM_FM2_DTSEC 4
443#define CONFIG_SYS_NUM_FM1_10GEC 1
444#define CONFIG_SYS_NUM_FM2_10GEC 1
445#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700446#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530447#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Kumar Galac657d892011-02-04 00:43:34 -0600448#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600449#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala8f290842011-05-20 00:39:21 -0500450#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabie46fedf2011-08-04 18:03:41 -0500451#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala243be8e2011-01-19 03:05:26 -0600452#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
453#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sunfa8d23c2011-01-10 12:03:01 +0000454#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Gala243be8e2011-01-19 03:05:26 -0600455#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
456#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
457#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
Zang Roy-R619114e0be342012-09-18 09:50:08 +0000458#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
Kumar Gala243be8e2011-01-19 03:05:26 -0600459#define CONFIG_SYS_P4080_ERRATUM_CPU22
York Sun5e23ab02012-05-07 07:26:47 +0000460#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala243be8e2011-01-19 03:05:26 -0600461#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medvedf8af0b2010-08-31 22:57:38 -0500462#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabid90fdba2011-04-18 17:16:00 -0500463#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabida30b9f2011-04-01 13:19:36 -0500464#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Gala43f082b2011-11-22 06:51:15 -0600465#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun41085082011-11-20 10:01:35 -0800466#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000467#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
468#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
469#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
470#define CONFIG_SYS_FSL_RMU
471#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Scott Wood33eee332012-08-14 10:14:53 +0000472#define CONFIG_SYS_FSL_ERRATUM_A004510
473#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
474#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
Liu Gangd59c5572012-09-28 21:26:19 +0000475#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi01180332012-10-25 12:40:00 +0000476#define CONFIG_SYS_FSL_ERRATUM_A004849
Timur Tabid607b962012-11-01 08:20:23 +0000477#define CONFIG_SYS_FSL_ERRATUM_A004580
Yuanquan Chenc0a4e6b2012-11-26 23:49:45 +0000478#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
York Sund217a9a2013-06-25 11:37:49 -0700479#define CONFIG_SYS_FSL_ERRATUM_A005812
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800480#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
481#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala243be8e2011-01-19 03:05:26 -0600482
Scott Wood3e978f52012-08-14 10:14:51 +0000483#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
York Sunffd06e02012-10-08 07:44:30 +0000484#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sund1001e32012-10-08 07:44:15 +0000485#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700486#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala243be8e2011-01-19 03:05:26 -0600487#define CONFIG_MAX_CPUS 2
Kumar Galab5c87532011-02-16 02:03:29 -0600488#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600489#define CONFIG_SYS_FSL_NUM_LAWS 32
490#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galafbee0f72011-01-25 12:42:32 -0600491#define CONFIG_SYS_NUM_FMAN 1
492#define CONFIG_SYS_NUM_FM1_DTSEC 5
493#define CONFIG_SYS_NUM_FM1_10GEC 1
494#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700495#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530496#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Kumar Galac657d892011-02-04 00:43:34 -0600497#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600498#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala8f290842011-05-20 00:39:21 -0500499#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500500#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang86221f02011-04-13 00:08:51 -0500501#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
502#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500503#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu30009762011-04-19 15:28:41 +0800504#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei99d7b0a2013-03-11 17:56:34 +0000505#define CONFIG_SYS_FSL_ERRATUM_USB14
York Sune22be772013-03-25 07:30:11 +0000506#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun41085082011-11-20 10:01:35 -0800507#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000508#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
509#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
510#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000511#define CONFIG_SYS_FSL_ERRATUM_A004510
512#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
513#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000514#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800515#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Suresh Gupta9c641a82014-02-26 14:29:12 +0530516#define CONFIG_SYS_FSL_ERRATUM_A006261
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800517#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala243be8e2011-01-19 03:05:26 -0600518
Timur Tabi49054432012-10-05 11:09:19 +0000519#elif defined(CONFIG_PPC_P5040)
Timur Tabi1956e432012-10-23 10:48:09 +0000520#define CONFIG_SYS_PPC64
Timur Tabi49054432012-10-05 11:09:19 +0000521#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700522#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Timur Tabi49054432012-10-05 11:09:19 +0000523#define CONFIG_MAX_CPUS 4
524#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
525#define CONFIG_SYS_FSL_NUM_LAWS 32
526#define CONFIG_SYS_FSL_SEC_COMPAT 4
527#define CONFIG_SYS_NUM_FMAN 2
528#define CONFIG_SYS_NUM_FM1_DTSEC 5
529#define CONFIG_SYS_NUM_FM1_10GEC 1
530#define CONFIG_SYS_NUM_FM2_DTSEC 5
531#define CONFIG_SYS_NUM_FM2_10GEC 1
532#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700533#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530534#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Timur Tabi49054432012-10-05 11:09:19 +0000535#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
536#define CONFIG_SYS_FSL_TBCLK_DIV 16
537#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
538#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
539#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
540#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
541#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
542#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei99d7b0a2013-03-11 17:56:34 +0000543#define CONFIG_SYS_FSL_ERRATUM_USB14
Timur Tabi49054432012-10-05 11:09:19 +0000544#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
545#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
546#define CONFIG_SYS_FSL_ERRATUM_A004699
Timur Tabi49054432012-10-05 11:09:19 +0000547#define CONFIG_SYS_FSL_ERRATUM_A004510
548#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
Suresh Gupta9c641a82014-02-26 14:29:12 +0530549#define CONFIG_SYS_FSL_ERRATUM_A006261
Timur Tabi49054432012-10-05 11:09:19 +0000550#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
York Sund217a9a2013-06-25 11:37:49 -0700551#define CONFIG_SYS_FSL_ERRATUM_A005812
Timur Tabi49054432012-10-05 11:09:19 +0000552
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000553#elif defined(CONFIG_BSC9131)
554#define CONFIG_MAX_CPUS 1
555#define CONFIG_FSL_SDHC_V2_3
556#define CONFIG_SYS_FSL_NUM_LAWS 12
557#define CONFIG_TSECV2
558#define CONFIG_SYS_FSL_SEC_COMPAT 4
559#define CONFIG_NUM_DDR_CONTROLLERS 1
York Sun34e026f2014-03-27 17:54:47 -0700560#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530561#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Priyanka Jain765b0bd2013-04-04 09:31:54 +0530562#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
563#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
Mingkai Hu362ee042013-05-16 10:18:13 +0800564#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000565#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
566#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000567#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun954a1a42013-08-20 15:09:43 -0700568#define CONFIG_SYS_FSL_ERRATUM_A005125
Haijun.Zhangf28bea02014-01-10 13:52:19 +0800569#define CONFIG_ESDHC_HC_BLK_ADDR
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000570
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000571#elif defined(CONFIG_BSC9132)
572#define CONFIG_MAX_CPUS 2
573#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
574#define CONFIG_FSL_SDHC_V2_3
575#define CONFIG_SYS_FSL_NUM_LAWS 12
576#define CONFIG_TSECV2
577#define CONFIG_SYS_FSL_SEC_COMPAT 4
578#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700579#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
ramneek mehreshf1810d82013-10-18 17:40:17 +0530580#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Priyanka Jain64501c62013-07-02 09:21:04 +0530581#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
582#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
583#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
584#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
York Sun061ffed2013-04-18 19:31:01 -0700585#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000586#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
587#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000588#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
589#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
590#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
York Sun954a1a42013-08-20 15:09:43 -0700591#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800592#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
593#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Haijun.Zhangf28bea02014-01-10 13:52:19 +0800594#define CONFIG_ESDHC_HC_BLK_ADDR
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000595
York Sun3d2972f2013-03-25 07:40:05 +0000596#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
597#define CONFIG_E6500
York Sunffd06e02012-10-08 07:44:30 +0000598#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun9e758752012-10-08 07:44:19 +0000599#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
600#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
York Sunf6981432013-03-25 07:40:07 +0000601#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
York Sun9e758752012-10-08 07:44:19 +0000602#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
York Sun3d2972f2013-03-25 07:40:05 +0000603#ifdef CONFIG_PPC_T4240
York Sun9e758752012-10-08 07:44:19 +0000604#define CONFIG_MAX_CPUS 12
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530605#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
York Sun9e758752012-10-08 07:44:19 +0000606#define CONFIG_SYS_NUM_FM1_DTSEC 8
607#define CONFIG_SYS_NUM_FM1_10GEC 2
608#define CONFIG_SYS_NUM_FM2_DTSEC 8
609#define CONFIG_SYS_NUM_FM2_10GEC 2
610#define CONFIG_NUM_DDR_CONTROLLERS 3
York Sun3d2972f2013-03-25 07:40:05 +0000611#else
York Sunb6240842013-03-25 07:33:29 +0000612#define CONFIG_MAX_CPUS 8
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530613#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
York Sun3d2972f2013-03-25 07:40:05 +0000614#define CONFIG_SYS_NUM_FM1_DTSEC 7
615#define CONFIG_SYS_NUM_FM1_10GEC 1
616#define CONFIG_SYS_NUM_FM2_DTSEC 7
617#define CONFIG_SYS_NUM_FM2_10GEC 1
618#define CONFIG_NUM_DDR_CONTROLLERS 2
619#endif
York Sunb6240842013-03-25 07:33:29 +0000620#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
621#define CONFIG_SYS_FSL_NUM_LAWS 32
Prabhakar Kushwahaa4c955b2013-07-31 16:56:41 +0530622#define CONFIG_SYS_FSL_SRDS_1
623#define CONFIG_SYS_FSL_SRDS_2
York Sunb6240842013-03-25 07:33:29 +0000624#define CONFIG_SYS_FSL_SRDS_3
625#define CONFIG_SYS_FSL_SRDS_4
626#define CONFIG_SYS_FSL_SEC_COMPAT 4
627#define CONFIG_SYS_NUM_FMAN 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530628#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530629#define CONFIG_SYS_PME_CLK 0
York Sunb6240842013-03-25 07:33:29 +0000630#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Mingkai Hu362ee042013-05-16 10:18:13 +0800631#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
York Sunb6240842013-03-25 07:33:29 +0000632#define CONFIG_SYS_FMAN_V3
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530633#define CONFIG_SYS_FM1_CLK 3
634#define CONFIG_SYS_FM2_CLK 3
York Sunb6240842013-03-25 07:33:29 +0000635#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
636#define CONFIG_SYS_FSL_TBCLK_DIV 16
637#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
638#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
639#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
640#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Liu Gang08047932013-06-25 18:12:14 +0800641#define CONFIG_SYS_FSL_SRIO_LIODN
York Sunb6240842013-03-25 07:33:29 +0000642#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
643#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
644#define CONFIG_SYS_FSL_ERRATUM_A004468
645#define CONFIG_SYS_FSL_ERRATUM_A_004934
646#define CONFIG_SYS_FSL_ERRATUM_A005871
Suresh Gupta9c641a82014-02-26 14:29:12 +0530647#define CONFIG_SYS_FSL_ERRATUM_A006261
York Sun133fbfa2013-09-16 12:49:31 -0700648#define CONFIG_SYS_FSL_ERRATUM_A006379
Scott Wood82125192013-05-15 17:50:13 -0500649#define CONFIG_SYS_FSL_ERRATUM_A006593
York Sunb6240842013-03-25 07:33:29 +0000650#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
651#define CONFIG_SYS_FSL_PCI_VER_3_X
652
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000653#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
654#define CONFIG_E6500
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000655#define CONFIG_SYS_PPC64 /* 64-bit core */
656#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
657#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
658#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000659#define CONFIG_SYS_FSL_NUM_LAWS 32
Prabhakar Kushwahaa4c955b2013-07-31 16:56:41 +0530660#define CONFIG_SYS_FSL_SRDS_1
661#define CONFIG_SYS_FSL_SRDS_2
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000662#define CONFIG_SYS_FSL_SEC_COMPAT 4
663#define CONFIG_SYS_NUM_FMAN 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530664#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530665#define CONFIG_SYS_FM1_CLK 0
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000666#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Mingkai Hu362ee042013-05-16 10:18:13 +0800667#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000668#define CONFIG_SYS_FMAN_V3
669#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
670#define CONFIG_SYS_FSL_TBCLK_DIV 16
671#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
672#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
673#define CONFIG_SYS_FSL_ERRATUM_A_004934
Shengzhou Liu04feb572013-02-27 21:56:54 +0000674#define CONFIG_SYS_FSL_ERRATUM_A005871
York Sun133fbfa2013-09-16 12:49:31 -0700675#define CONFIG_SYS_FSL_ERRATUM_A006379
Scott Wood82125192013-05-15 17:50:13 -0500676#define CONFIG_SYS_FSL_ERRATUM_A006593
Shaveta Leekha7af9a072014-02-26 16:08:22 +0530677#define CONFIG_SYS_FSL_ERRATUM_A006475
678#define CONFIG_SYS_FSL_ERRATUM_A006384
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000679#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
680
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000681#ifdef CONFIG_PPC_B4860
York Sunf6981432013-03-25 07:40:07 +0000682#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
York Sund2404142012-10-08 07:44:20 +0000683#define CONFIG_MAX_CPUS 4
Shaveta Leekha6df82e32014-02-26 16:07:37 +0530684#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
York Sund2404142012-10-08 07:44:20 +0000685#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530686#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
York Sund2404142012-10-08 07:44:20 +0000687#define CONFIG_SYS_NUM_FM1_DTSEC 6
688#define CONFIG_SYS_NUM_FM1_10GEC 2
Poonam Aggrwale394ceb2012-12-23 19:22:33 +0000689#define CONFIG_NUM_DDR_CONTROLLERS 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530690#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
York Sund2404142012-10-08 07:44:20 +0000691#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
692#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
693#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Liu Gang32f38ee2013-06-25 18:12:13 +0800694#define CONFIG_SYS_FSL_SRIO_LIODN
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000695#else
696#define CONFIG_MAX_CPUS 2
Shaveta Leekha6df82e32014-02-26 16:07:37 +0530697#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000698#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
699#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530700#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000701#define CONFIG_SYS_NUM_FM1_DTSEC 4
702#define CONFIG_SYS_NUM_FM1_10GEC 0
703#define CONFIG_NUM_DDR_CONTROLLERS 1
704#endif
York Sund2404142012-10-08 07:44:20 +0000705
Priyanka Jain2967af62013-10-18 12:30:21 +0530706#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
707defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
York Sun5f208d12013-03-25 07:40:06 +0000708#define CONFIG_E5500
709#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
710#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
York Sunf6981432013-03-25 07:40:07 +0000711#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
York Sun5f208d12013-03-25 07:40:06 +0000712#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
York Sun34e026f2014-03-27 17:54:47 -0700713#ifdef CONFIG_SYS_FSL_DDR4
714#define CONFIG_SYS_FSL_DDRC_GEN4
715#endif
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530716#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
York Sun5f208d12013-03-25 07:40:06 +0000717#define CONFIG_MAX_CPUS 4
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530718#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
719#define CONFIG_MAX_CPUS 2
720#endif
721#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530722#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
723#define CONFIG_SYS_SDHC_CLOCK 0
York Sun5f208d12013-03-25 07:40:06 +0000724#define CONFIG_SYS_FSL_NUM_LAWS 16
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530725#define CONFIG_SYS_FSL_SRDS_1
726#define CONFIG_SYS_FSL_SEC_COMPAT 5
York Sun5f208d12013-03-25 07:40:06 +0000727#define CONFIG_SYS_NUM_FMAN 1
728#define CONFIG_SYS_NUM_FM1_DTSEC 5
729#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530730#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530731#define CONFIG_PME_PLAT_CLK_DIV 2
732#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530733#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
734#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
York Sun5f208d12013-03-25 07:40:06 +0000735#define CONFIG_SYS_FMAN_V3
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530736#define CONFIG_FM_PLAT_CLK_DIV 1
737#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530738#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
Priyanka Jainb1359912013-12-17 14:25:52 +0530739#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
Prabhakar Kushwahae03c76c2013-12-11 12:49:13 +0530740#define CONFIG_SYS_FSL_TBCLK_DIV 16
York Sun5f208d12013-03-25 07:40:06 +0000741#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
Nikhil Badolaa4f7cba2014-01-27 15:21:58 +0530742#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
York Sun5f208d12013-03-25 07:40:06 +0000743#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Suresh Gupta9c641a82014-02-26 14:29:12 +0530744#define CONFIG_SYS_FSL_ERRATUM_A006261
York Sun5f208d12013-03-25 07:40:06 +0000745#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Haijun.Zhang1336e2d2014-03-18 17:04:23 +0800746#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
747#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
Zhao Qiang2a44efe2014-03-21 16:21:45 +0800748#define QE_MURAM_SIZE 0x6000UL
749#define MAX_QE_RISC 1
750#define QE_NUM_OF_SNUM 28
York Sun5f208d12013-03-25 07:40:06 +0000751
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800752#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
753#define CONFIG_E6500
754#define CONFIG_SYS_PPC64 /* 64-bit core */
755#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
756#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
757#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
758#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
759#define CONFIG_SYS_FSL_QMAN_V3
760#define CONFIG_MAX_CPUS 4
761#define CONFIG_SYS_FSL_NUM_LAWS 32
762#define CONFIG_SYS_FSL_SEC_COMPAT 4
763#define CONFIG_SYS_NUM_FMAN 1
764#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
765#define CONFIG_SYS_FSL_SRDS_1
766#define CONFIG_SYS_FSL_PCI_VER_3_X
767#if defined(CONFIG_PPC_T2080)
768#define CONFIG_SYS_NUM_FM1_DTSEC 8
769#define CONFIG_SYS_NUM_FM1_10GEC 4
770#define CONFIG_SYS_FSL_SRDS_2
771#define CONFIG_SYS_FSL_SRIO_LIODN
772#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
773#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
774#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
775#elif defined(CONFIG_PPC_T2081)
776#define CONFIG_SYS_NUM_FM1_DTSEC 6
777#define CONFIG_SYS_NUM_FM1_10GEC 2
778#endif
Shengzhou Liu2ffa96d2013-12-18 10:27:55 +0800779#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800780#define CONFIG_NUM_DDR_CONTROLLERS 1
781#define CONFIG_PME_PLAT_CLK_DIV 1
782#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
783#define CONFIG_SYS_FM1_CLK 0
784#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
785#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
786#define CONFIG_SYS_FMAN_V3
787#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
788#define CONFIG_SYS_FSL_TBCLK_DIV 16
789#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
790#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
791#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
792#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
793#define CONFIG_SYS_FSL_SFP_VER_3_0
794#define CONFIG_SYS_FSL_ISBC_VER 2
Haijun.Zhang1336e2d2014-03-18 17:04:23 +0800795#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
796#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
797
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800798
Mingkai Hu3b75e982013-07-04 17:30:36 +0800799#elif defined(CONFIG_PPC_C29X)
800#define CONFIG_MAX_CPUS 1
801#define CONFIG_FSL_SDHC_V2_3
802#define CONFIG_SYS_FSL_NUM_LAWS 12
803#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
804#define CONFIG_TSECV2_1
805#define CONFIG_SYS_FSL_SEC_COMPAT 6
806#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
807#define CONFIG_NUM_DDR_CONTROLLERS 1
York Sun34e026f2014-03-27 17:54:47 -0700808#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
Mingkai Hu3b75e982013-07-04 17:30:36 +0800809#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
810#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun954a1a42013-08-20 15:09:43 -0700811#define CONFIG_SYS_FSL_ERRATUM_A005125
Mingkai Hu3b75e982013-07-04 17:30:36 +0800812
Alexander Graffa08d392014-04-11 17:09:45 +0200813#elif defined(CONFIG_QEMU_E500)
814#define CONFIG_MAX_CPUS 1
815#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
816
Kumar Gala243be8e2011-01-19 03:05:26 -0600817#else
818#error Processor type not defined for this platform
819#endif
820
Timur Tabie46fedf2011-08-04 18:03:41 -0500821#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
822#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
823#endif
824
York Sunf6981432013-03-25 07:40:07 +0000825#ifdef CONFIG_E6500
826#define CONFIG_SYS_FSL_THREADS_PER_CORE 2
827#else
828#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
829#endif
830
York Sun5614e712013-09-30 09:22:09 -0700831#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
832 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
York Sun34e026f2014-03-27 17:54:47 -0700833 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
834 !defined(CONFIG_SYS_FSL_DDRC_GEN4)
York Sun5614e712013-09-30 09:22:09 -0700835#define CONFIG_SYS_FSL_DDRC_GEN3
836#endif
837
Kumar Gala243be8e2011-01-19 03:05:26 -0600838#endif /* _ASM_MPC85xx_CONFIG_H_ */