Blame - arch/powerpc/include/asm/config_mpc85xx.h - github/trini/u-boot

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Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	1	/*
Prabhakar Kushwaha	19a8dbd	2012-04-24 20:16:49 +0000	[diff] [blame]	2	* Copyright 2011-2012 Freescale Semiconductor, Inc.
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	3	*
Wolfgang Denk	1a45966	2013-07-08 09:37:19 +0200	[diff] [blame]	4	* SPDX-License-Identifier: GPL-2.0+
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	5	*/
				6
				7	#ifndef _ASM_MPC85xx_CONFIG_H_
				8	#define _ASM_MPC85xx_CONFIG_H_
				9
				10	/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
				11
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	12	#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
				13	#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
				14	#endif
				15
York Sun	2a5fcb8	2012-10-28 08:12:54 +0000	[diff] [blame]	16	/*
				17	* This macro should be removed when we no longer care about backwards
				18	* compatibility with older operating systems.
				19	*/
				20	#define CONFIG_PPC_SPINTABLE_COMPATIBLE
				21
York Sun	57495e4	2012-10-08 07:44:22 +0000	[diff] [blame]	22	#define FSL_DDR_VER_4_7 47
Prabhakar Kushwaha	1d384ec	2013-09-03 11:19:54 +0530	[diff] [blame^]	23	#define FSL_DDR_VER_5_0 50
York Sun	57495e4	2012-10-08 07:44:22 +0000	[diff] [blame]	24
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	25	/* Number of TLB CAM entries we have on FSL Book-E chips */
				26	#if defined(CONFIG_E500MC)
				27	#define CONFIG_SYS_NUM_TLBCAMS 64
				28	#elif defined(CONFIG_E500)
				29	#define CONFIG_SYS_NUM_TLBCAMS 16
				30	#endif
				31
				32	#if defined(CONFIG_MPC8536)
				33	#define CONFIG_MAX_CPUS 1
				34	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	e4879af	2012-08-15 04:12:43 +0000	[diff] [blame]	35	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	36	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	37	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	38	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	39
Wolfgang Denk	d1a24f0	2011-02-02 22:36:10 +0100	[diff] [blame]	40	#elif defined(CONFIG_MPC8540)
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	41	#define CONFIG_MAX_CPUS 1
				42	#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	43	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	44
Wolfgang Denk	d1a24f0	2011-02-02 22:36:10 +0100	[diff] [blame]	45	#elif defined(CONFIG_MPC8541)
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	46	#define CONFIG_MAX_CPUS 1
				47	#define CONFIG_SYS_FSL_NUM_LAWS 8
				48	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	49	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	50
				51	#elif defined(CONFIG_MPC8544)
				52	#define CONFIG_MAX_CPUS 1
				53	#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwaha	e4879af	2012-08-15 04:12:43 +0000	[diff] [blame]	54	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	55	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	56	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	57	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	58
				59	#elif defined(CONFIG_MPC8548)
				60	#define CONFIG_MAX_CPUS 1
				61	#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwaha	e4879af	2012-08-15 04:12:43 +0000	[diff] [blame]	62	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	63	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	64	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	5ace299	2011-09-16 09:54:30 -0500	[diff] [blame]	65	#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
Kumar Gala	2b3a1cd	2011-10-03 08:37:57 -0500	[diff] [blame]	66	#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
chenhui zhao	aada81d	2011-10-03 08:38:50 -0500	[diff] [blame]	67	#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	68	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
				69	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				70	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				71	#define CONFIG_SYS_FSL_RMU
				72	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	73	#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan	9c3f77e	2013-08-16 15:10:37 +0800	[diff] [blame]	74	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
				75	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	76
				77	#elif defined(CONFIG_MPC8555)
				78	#define CONFIG_MAX_CPUS 1
				79	#define CONFIG_SYS_FSL_NUM_LAWS 8
				80	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	81	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	82
				83	#elif defined(CONFIG_MPC8560)
				84	#define CONFIG_MAX_CPUS 1
				85	#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	86	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	87
				88	#elif defined(CONFIG_MPC8568)
				89	#define CONFIG_MAX_CPUS 1
				90	#define CONFIG_SYS_FSL_NUM_LAWS 10
				91	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala	fdb4dad	2011-01-31 23:09:25 -0600	[diff] [blame]	92	#define QE_MURAM_SIZE 0x10000UL
				93	#define MAX_QE_RISC 2
				94	#define QE_NUM_OF_SNUM 28
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	95	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	96	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
				97	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				98	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				99	#define CONFIG_SYS_FSL_RMU
				100	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	101
				102	#elif defined(CONFIG_MPC8569)
				103	#define CONFIG_MAX_CPUS 1
				104	#define CONFIG_SYS_FSL_NUM_LAWS 10
				105	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala	fdb4dad	2011-01-31 23:09:25 -0600	[diff] [blame]	106	#define QE_MURAM_SIZE 0x20000UL
				107	#define MAX_QE_RISC 4
				108	#define QE_NUM_OF_SNUM 46
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	109	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	110	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
				111	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				112	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				113	#define CONFIG_SYS_FSL_RMU
				114	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	115	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	116
				117	#elif defined(CONFIG_MPC8572)
				118	#define CONFIG_MAX_CPUS 2
				119	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	e4879af	2012-08-15 04:12:43 +0000	[diff] [blame]	120	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	121	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	122	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun	eb0aff7	2011-01-25 21:51:27 -0800	[diff] [blame]	123	#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sun	9167191	2011-01-25 22:05:49 -0800	[diff] [blame]	124	#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	125	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	126
				127	#elif defined(CONFIG_P1010)
				128	#define CONFIG_MAX_CPUS 1
Priyanka Jain	32c8cfb	2011-02-09 09:24:10 +0530	[diff] [blame]	129	#define CONFIG_FSL_SDHC_V2_3
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	130	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	131	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	132	#define CONFIG_TSECV2
				133	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal	1fbf348	2011-02-06 11:31:44 +0530	[diff] [blame]	134	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				135	#define CONFIG_NUM_DDR_CONTROLLERS 1
Mingkai Hu	362ee04	2013-05-16 10:18:13 +0800	[diff] [blame]	136	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
Poonam Aggrwal	1fbf348	2011-02-06 11:31:44 +0530	[diff] [blame]	137	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	8f29084	2011-05-20 00:39:21 -0500	[diff] [blame]	138	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh	1b719e6	2011-03-23 15:20:43 +0530	[diff] [blame]	139	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal	42aee64	2011-06-30 03:00:28 -0500	[diff] [blame]	140	#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwal	fb855f4	2011-06-29 16:32:52 +0530	[diff] [blame]	141	#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Shengzhou Liu	424bf94	2013-08-15 09:31:47 +0800	[diff] [blame]	142	#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
Poonam Aggrwal	bc6bbd6	2011-07-07 20:36:47 +0530	[diff] [blame]	143	#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	144	#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan	9c3f77e	2013-08-16 15:10:37 +0800	[diff] [blame]	145	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
				146	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	147
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	148	/* P1011 is single core version of P1020 */
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	149	#elif defined(CONFIG_P1011)
				150	#define CONFIG_MAX_CPUS 1
				151	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	152	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	153	#define CONFIG_TSECV2
Prabhakar Kushwaha	b03a466	2011-02-01 15:55:58 +0000	[diff] [blame]	154	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	155	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	156	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	157	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				158	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	159	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	160
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	161	/* P1012 is single core version of P1021 */
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	162	#elif defined(CONFIG_P1012)
				163	#define CONFIG_MAX_CPUS 1
				164	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	165	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	166	#define CONFIG_TSECV2
Prabhakar Kushwaha	b03a466	2011-02-01 15:55:58 +0000	[diff] [blame]	167	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	168	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	169	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	170	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				171	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang	a52d2f8	2011-02-11 01:25:30 -0600	[diff] [blame]	172	#define QE_MURAM_SIZE 0x6000UL
				173	#define MAX_QE_RISC 1
				174	#define QE_NUM_OF_SNUM 28
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	175	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	176
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	177	/* P1013 is single core version of P1022 */
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	178	#elif defined(CONFIG_P1013)
				179	#define CONFIG_MAX_CPUS 1
				180	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	181	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	182	#define CONFIG_TSECV2
				183	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	184	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang	2d7534a	2011-01-30 17:06:20 -0600	[diff] [blame]	185	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				186	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				187	#define CONFIG_FSL_SATA_ERRATUM_A001
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	188	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	189
				190	#elif defined(CONFIG_P1014)
				191	#define CONFIG_MAX_CPUS 1
Priyanka Jain	32c8cfb	2011-02-09 09:24:10 +0530	[diff] [blame]	192	#define CONFIG_FSL_SDHC_V2_3
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	193	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	194	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	195	#define CONFIG_TSECV2
				196	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal	1fbf348	2011-02-06 11:31:44 +0530	[diff] [blame]	197	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				198	#define CONFIG_NUM_DDR_CONTROLLERS 1
				199	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Ramneek Mehresh	1b719e6	2011-03-23 15:20:43 +0530	[diff] [blame]	200	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal	42aee64	2011-06-30 03:00:28 -0500	[diff] [blame]	201	#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwal	fb855f4	2011-06-29 16:32:52 +0530	[diff] [blame]	202	#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwal	bc6bbd6	2011-07-07 20:36:47 +0530	[diff] [blame]	203	#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	204
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	205	/* P1017 is single core version of P1023 */
Roy Zang	67a719d	2011-02-03 22:14:19 -0600	[diff] [blame]	206	#elif defined(CONFIG_P1017)
				207	#define CONFIG_MAX_CPUS 1
				208	#define CONFIG_SYS_FSL_NUM_LAWS 12
				209	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				210	#define CONFIG_SYS_NUM_FMAN 1
				211	#define CONFIG_SYS_NUM_FM1_DTSEC 2
				212	#define CONFIG_NUM_DDR_CONTROLLERS 1
				213	#define CONFIG_SYS_QMAN_NUM_PORTALS 3
				214	#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Gala	c657d89	2011-02-04 00:43:34 -0600	[diff] [blame]	215	#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala	8f29084	2011-05-20 00:39:21 -0500	[diff] [blame]	216	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	217	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	218	#define CONFIG_SYS_FSL_ERRATUM_A005125
Roy Zang	67a719d	2011-02-03 22:14:19 -0600	[diff] [blame]	219
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	220	#elif defined(CONFIG_P1020)
				221	#define CONFIG_MAX_CPUS 2
				222	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	223	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	224	#define CONFIG_TSECV2
Prabhakar Kushwaha	b03a466	2011-02-01 15:55:58 +0000	[diff] [blame]	225	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	226	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	227	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	228	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				229	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	230	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	231
				232	#elif defined(CONFIG_P1021)
				233	#define CONFIG_MAX_CPUS 2
				234	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	235	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	236	#define CONFIG_TSECV2
Prabhakar Kushwaha	b03a466	2011-02-01 15:55:58 +0000	[diff] [blame]	237	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	238	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	239	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	240	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				241	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang	a52d2f8	2011-02-11 01:25:30 -0600	[diff] [blame]	242	#define QE_MURAM_SIZE 0x6000UL
				243	#define MAX_QE_RISC 1
				244	#define QE_NUM_OF_SNUM 28
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	245	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	246
				247	#elif defined(CONFIG_P1022)
				248	#define CONFIG_MAX_CPUS 2
				249	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	250	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	251	#define CONFIG_TSECV2
				252	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	253	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang	2d7534a	2011-01-30 17:06:20 -0600	[diff] [blame]	254	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				255	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				256	#define CONFIG_FSL_SATA_ERRATUM_A001
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	257	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	258
Roy Zang	67a719d	2011-02-03 22:14:19 -0600	[diff] [blame]	259	#elif defined(CONFIG_P1023)
				260	#define CONFIG_MAX_CPUS 2
				261	#define CONFIG_SYS_FSL_NUM_LAWS 12
				262	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				263	#define CONFIG_SYS_NUM_FMAN 1
				264	#define CONFIG_SYS_NUM_FM1_DTSEC 2
				265	#define CONFIG_NUM_DDR_CONTROLLERS 1
				266	#define CONFIG_SYS_QMAN_NUM_PORTALS 3
				267	#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Gala	c657d89	2011-02-04 00:43:34 -0600	[diff] [blame]	268	#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala	8f29084	2011-05-20 00:39:21 -0500	[diff] [blame]	269	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	270	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	271	#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan	9c3f77e	2013-08-16 15:10:37 +0800	[diff] [blame]	272	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
				273	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Roy Zang	67a719d	2011-02-03 22:14:19 -0600	[diff] [blame]	274
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	275	/* P1024 is lower end variant of P1020 */
				276	#elif defined(CONFIG_P1024)
				277	#define CONFIG_MAX_CPUS 2
				278	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	279	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	280	#define CONFIG_TSECV2
				281	#define CONFIG_FSL_PCIE_DISABLE_ASPM
				282	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	283	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	284	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				285	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	286	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	287
				288	/* P1025 is lower end variant of P1021 */
				289	#elif defined(CONFIG_P1025)
				290	#define CONFIG_MAX_CPUS 2
				291	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	292	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	293	#define CONFIG_TSECV2
				294	#define CONFIG_FSL_PCIE_DISABLE_ASPM
				295	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	296	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	297	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				298	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang	a52d2f8	2011-02-11 01:25:30 -0600	[diff] [blame]	299	#define QE_MURAM_SIZE 0x6000UL
				300	#define MAX_QE_RISC 1
				301	#define QE_NUM_OF_SNUM 28
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	302	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	303
				304	/* P2010 is single core version of P2020 */
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	305	#elif defined(CONFIG_P2010)
				306	#define CONFIG_MAX_CPUS 1
				307	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	308	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	309	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	310	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	6e7f0bc0	2011-01-26 01:43:15 -0600	[diff] [blame]	311	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala	5103a03	2011-01-29 15:36:10 -0600	[diff] [blame]	312	#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	313	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	314
				315	#elif defined(CONFIG_P2020)
				316	#define CONFIG_MAX_CPUS 2
				317	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	318	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	319	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	320	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	6e7f0bc0	2011-01-26 01:43:15 -0600	[diff] [blame]	321	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala	5103a03	2011-01-29 15:36:10 -0600	[diff] [blame]	322	#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	323	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				324	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				325	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				326	#define CONFIG_SYS_FSL_RMU
				327	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	328	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	329
Scott Wood	3e978f5	2012-08-14 10:14:51 +0000	[diff] [blame]	330	#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
York Sun	d1001e3	2012-10-08 07:44:15 +0000	[diff] [blame]	331	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sun	d2ab4bb	2013-06-25 11:37:39 -0700	[diff] [blame]	332	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala	1f97987	2011-05-13 01:16:07 -0500	[diff] [blame]	333	#define CONFIG_MAX_CPUS 4
				334	#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
				335	#define CONFIG_SYS_FSL_NUM_LAWS 32
				336	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				337	#define CONFIG_SYS_NUM_FMAN 1
				338	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				339	#define CONFIG_SYS_NUM_FM1_10GEC 1
				340	#define CONFIG_NUM_DDR_CONTROLLERS 1
				341	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
				342	#define CONFIG_SYS_FSL_TBCLK_DIV 32
				343	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	344	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala	1f97987	2011-05-13 01:16:07 -0500	[diff] [blame]	345	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				346	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Gala	b6c3722	2011-04-13 00:19:10 -0500	[diff] [blame]	347	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala	1f97987	2011-05-13 01:16:07 -0500	[diff] [blame]	348	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun	5e23ab0	2012-05-07 07:26:47 +0000	[diff] [blame]	349	#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei	99d7b0a	2013-03-11 17:56:34 +0000	[diff] [blame]	350	#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala	43f082b	2011-11-22 06:51:15 -0600	[diff] [blame]	351	#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun	e22be77	2013-03-25 07:30:11 +0000	[diff] [blame]	352	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun	4108508	2011-11-20 10:01:35 -0800	[diff] [blame]	353	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	354	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				355	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				356	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood	33eee33	2012-08-14 10:14:53 +0000	[diff] [blame]	357	#define CONFIG_SYS_FSL_ERRATUM_A004510
				358	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				359	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
				360	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gang	d59c557	2012-09-28 21:26:19 +0000	[diff] [blame]	361	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi	0118033	2012-10-25 12:40:00 +0000	[diff] [blame]	362	#define CONFIG_SYS_FSL_ERRATUM_A004849
Chunhe Lan	9c3f77e	2013-08-16 15:10:37 +0800	[diff] [blame]	363	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
				364	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Kumar Gala	1f97987	2011-05-13 01:16:07 -0500	[diff] [blame]	365
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	366	#elif defined(CONFIG_PPC_P3041)
York Sun	d1001e3	2012-10-08 07:44:15 +0000	[diff] [blame]	367	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sun	d2ab4bb	2013-06-25 11:37:39 -0700	[diff] [blame]	368	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	369	#define CONFIG_MAX_CPUS 4
Kumar Gala	b5c8753	2011-02-16 02:03:29 -0600	[diff] [blame]	370	#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	371	#define CONFIG_SYS_FSL_NUM_LAWS 32
				372	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala	fbee0f7	2011-01-25 12:42:32 -0600	[diff] [blame]	373	#define CONFIG_SYS_NUM_FMAN 1
				374	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				375	#define CONFIG_SYS_NUM_FM1_10GEC 1
				376	#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Gala	c657d89	2011-02-04 00:43:34 -0600	[diff] [blame]	377	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala	66412c6	2011-02-18 05:40:54 -0600	[diff] [blame]	378	#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala	8f29084	2011-05-20 00:39:21 -0500	[diff] [blame]	379	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	380	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang	86221f0	2011-04-13 00:08:51 -0500	[diff] [blame]	381	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				382	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Gala	b6c3722	2011-04-13 00:19:10 -0500	[diff] [blame]	383	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu	3000976	2011-04-19 15:28:41 +0800	[diff] [blame]	384	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun	57125f2	2012-08-08 18:04:53 +0000	[diff] [blame]	385	#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei	99d7b0a	2013-03-11 17:56:34 +0000	[diff] [blame]	386	#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala	43f082b	2011-11-22 06:51:15 -0600	[diff] [blame]	387	#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun	e22be77	2013-03-25 07:30:11 +0000	[diff] [blame]	388	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun	4108508	2011-11-20 10:01:35 -0800	[diff] [blame]	389	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	390	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				391	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				392	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood	33eee33	2012-08-14 10:14:53 +0000	[diff] [blame]	393	#define CONFIG_SYS_FSL_ERRATUM_A004510
				394	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				395	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
				396	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gang	d59c557	2012-09-28 21:26:19 +0000	[diff] [blame]	397	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi	0118033	2012-10-25 12:40:00 +0000	[diff] [blame]	398	#define CONFIG_SYS_FSL_ERRATUM_A004849
York Sun	d217a9a	2013-06-25 11:37:49 -0700	[diff] [blame]	399	#define CONFIG_SYS_FSL_ERRATUM_A005812
Chunhe Lan	9c3f77e	2013-08-16 15:10:37 +0800	[diff] [blame]	400	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
				401	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	402
Scott Wood	3e978f5	2012-08-14 10:14:51 +0000	[diff] [blame]	403	#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
York Sun	d1001e3	2012-10-08 07:44:15 +0000	[diff] [blame]	404	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sun	d2ab4bb	2013-06-25 11:37:39 -0700	[diff] [blame]	405	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	406	#define CONFIG_MAX_CPUS 8
Kumar Gala	b5c8753	2011-02-16 02:03:29 -0600	[diff] [blame]	407	#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	408	#define CONFIG_SYS_FSL_NUM_LAWS 32
				409	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				410	#define CONFIG_SYS_NUM_FMAN 2
				411	#define CONFIG_SYS_NUM_FM1_DTSEC 4
				412	#define CONFIG_SYS_NUM_FM2_DTSEC 4
				413	#define CONFIG_SYS_NUM_FM1_10GEC 1
				414	#define CONFIG_SYS_NUM_FM2_10GEC 1
				415	#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Gala	c657d89	2011-02-04 00:43:34 -0600	[diff] [blame]	416	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala	66412c6	2011-02-18 05:40:54 -0600	[diff] [blame]	417	#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala	8f29084	2011-05-20 00:39:21 -0500	[diff] [blame]	418	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	419	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	420	#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
				421	#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sun	fa8d23c	2011-01-10 12:03:01 +0000	[diff] [blame]	422	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	423	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				424	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				425	#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
Zang Roy-R61911	4e0be34	2012-09-18 09:50:08 +0000	[diff] [blame]	426	#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	427	#define CONFIG_SYS_P4080_ERRATUM_CPU22
York Sun	5e23ab0	2012-05-07 07:26:47 +0000	[diff] [blame]	428	#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	429	#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medve	df8af0b	2010-08-31 22:57:38 -0500	[diff] [blame]	430	#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabi	d90fdba	2011-04-18 17:16:00 -0500	[diff] [blame]	431	#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabi	da30b9f	2011-04-01 13:19:36 -0500	[diff] [blame]	432	#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Gala	43f082b	2011-11-22 06:51:15 -0600	[diff] [blame]	433	#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun	4108508	2011-11-20 10:01:35 -0800	[diff] [blame]	434	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	435	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				436	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				437	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				438	#define CONFIG_SYS_FSL_RMU
				439	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Scott Wood	33eee33	2012-08-14 10:14:53 +0000	[diff] [blame]	440	#define CONFIG_SYS_FSL_ERRATUM_A004510
				441	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
				442	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
Liu Gang	d59c557	2012-09-28 21:26:19 +0000	[diff] [blame]	443	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi	0118033	2012-10-25 12:40:00 +0000	[diff] [blame]	444	#define CONFIG_SYS_FSL_ERRATUM_A004849
Timur Tabi	d607b96	2012-11-01 08:20:23 +0000	[diff] [blame]	445	#define CONFIG_SYS_FSL_ERRATUM_A004580
Yuanquan Chen	c0a4e6b	2012-11-26 23:49:45 +0000	[diff] [blame]	446	#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
York Sun	d217a9a	2013-06-25 11:37:49 -0700	[diff] [blame]	447	#define CONFIG_SYS_FSL_ERRATUM_A005812
Chunhe Lan	9c3f77e	2013-08-16 15:10:37 +0800	[diff] [blame]	448	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
				449	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	450
Scott Wood	3e978f5	2012-08-14 10:14:51 +0000	[diff] [blame]	451	#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
York Sun	ffd06e0	2012-10-08 07:44:30 +0000	[diff] [blame]	452	#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun	d1001e3	2012-10-08 07:44:15 +0000	[diff] [blame]	453	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sun	d2ab4bb	2013-06-25 11:37:39 -0700	[diff] [blame]	454	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	455	#define CONFIG_MAX_CPUS 2
Kumar Gala	b5c8753	2011-02-16 02:03:29 -0600	[diff] [blame]	456	#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	457	#define CONFIG_SYS_FSL_NUM_LAWS 32
				458	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala	fbee0f7	2011-01-25 12:42:32 -0600	[diff] [blame]	459	#define CONFIG_SYS_NUM_FMAN 1
				460	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				461	#define CONFIG_SYS_NUM_FM1_10GEC 1
				462	#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Gala	c657d89	2011-02-04 00:43:34 -0600	[diff] [blame]	463	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala	66412c6	2011-02-18 05:40:54 -0600	[diff] [blame]	464	#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala	8f29084	2011-05-20 00:39:21 -0500	[diff] [blame]	465	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	466	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang	86221f0	2011-04-13 00:08:51 -0500	[diff] [blame]	467	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				468	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Gala	b6c3722	2011-04-13 00:19:10 -0500	[diff] [blame]	469	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu	3000976	2011-04-19 15:28:41 +0800	[diff] [blame]	470	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei	99d7b0a	2013-03-11 17:56:34 +0000	[diff] [blame]	471	#define CONFIG_SYS_FSL_ERRATUM_USB14
York Sun	e22be77	2013-03-25 07:30:11 +0000	[diff] [blame]	472	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun	4108508	2011-11-20 10:01:35 -0800	[diff] [blame]	473	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	474	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				475	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				476	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood	33eee33	2012-08-14 10:14:53 +0000	[diff] [blame]	477	#define CONFIG_SYS_FSL_ERRATUM_A004510
				478	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				479	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
Liu Gang	d59c557	2012-09-28 21:26:19 +0000	[diff] [blame]	480	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Chunhe Lan	9c3f77e	2013-08-16 15:10:37 +0800	[diff] [blame]	481	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
				482	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	483
Timur Tabi	4905443	2012-10-05 11:09:19 +0000	[diff] [blame]	484	#elif defined(CONFIG_PPC_P5040)
Timur Tabi	1956e43	2012-10-23 10:48:09 +0000	[diff] [blame]	485	#define CONFIG_SYS_PPC64
Timur Tabi	4905443	2012-10-05 11:09:19 +0000	[diff] [blame]	486	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sun	d2ab4bb	2013-06-25 11:37:39 -0700	[diff] [blame]	487	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Timur Tabi	4905443	2012-10-05 11:09:19 +0000	[diff] [blame]	488	#define CONFIG_MAX_CPUS 4
				489	#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
				490	#define CONFIG_SYS_FSL_NUM_LAWS 32
				491	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				492	#define CONFIG_SYS_NUM_FMAN 2
				493	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				494	#define CONFIG_SYS_NUM_FM1_10GEC 1
				495	#define CONFIG_SYS_NUM_FM2_DTSEC 5
				496	#define CONFIG_SYS_NUM_FM2_10GEC 1
				497	#define CONFIG_NUM_DDR_CONTROLLERS 2
				498	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
				499	#define CONFIG_SYS_FSL_TBCLK_DIV 16
				500	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
				501	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				502	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				503	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
				504	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
				505	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei	99d7b0a	2013-03-11 17:56:34 +0000	[diff] [blame]	506	#define CONFIG_SYS_FSL_ERRATUM_USB14
Timur Tabi	4905443	2012-10-05 11:09:19 +0000	[diff] [blame]	507	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
				508	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
				509	#define CONFIG_SYS_FSL_ERRATUM_A004699
Timur Tabi	4905443	2012-10-05 11:09:19 +0000	[diff] [blame]	510	#define CONFIG_SYS_FSL_ERRATUM_A004510
				511	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				512	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
York Sun	d217a9a	2013-06-25 11:37:49 -0700	[diff] [blame]	513	#define CONFIG_SYS_FSL_ERRATUM_A005812
Timur Tabi	4905443	2012-10-05 11:09:19 +0000	[diff] [blame]	514
Prabhakar Kushwaha	19a8dbd	2012-04-24 20:16:49 +0000	[diff] [blame]	515	#elif defined(CONFIG_BSC9131)
				516	#define CONFIG_MAX_CPUS 1
				517	#define CONFIG_FSL_SDHC_V2_3
				518	#define CONFIG_SYS_FSL_NUM_LAWS 12
				519	#define CONFIG_TSECV2
				520	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				521	#define CONFIG_NUM_DDR_CONTROLLERS 1
Priyanka Jain	765b0bd	2013-04-04 09:31:54 +0530	[diff] [blame]	522	#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
				523	#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
Mingkai Hu	362ee04	2013-05-16 10:18:13 +0800	[diff] [blame]	524	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
Prabhakar Kushwaha	19a8dbd	2012-04-24 20:16:49 +0000	[diff] [blame]	525	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
				526	#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha	19a8dbd	2012-04-24 20:16:49 +0000	[diff] [blame]	527	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	528	#define CONFIG_SYS_FSL_ERRATUM_A005125
Prabhakar Kushwaha	19a8dbd	2012-04-24 20:16:49 +0000	[diff] [blame]	529
Prabhakar Kushwaha	35fe948	2013-01-23 17:59:57 +0000	[diff] [blame]	530	#elif defined(CONFIG_BSC9132)
				531	#define CONFIG_MAX_CPUS 2
				532	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
				533	#define CONFIG_FSL_SDHC_V2_3
				534	#define CONFIG_SYS_FSL_NUM_LAWS 12
				535	#define CONFIG_TSECV2
				536	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				537	#define CONFIG_NUM_DDR_CONTROLLERS 2
Priyanka Jain	64501c6	2013-07-02 09:21:04 +0530	[diff] [blame]	538	#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
				539	#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
				540	#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
				541	#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
York Sun	061ffed	2013-04-18 19:31:01 -0700	[diff] [blame]	542	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
Prabhakar Kushwaha	35fe948	2013-01-23 17:59:57 +0000	[diff] [blame]	543	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
				544	#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha	35fe948	2013-01-23 17:59:57 +0000	[diff] [blame]	545	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				546	#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
				547	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	548	#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan	9c3f77e	2013-08-16 15:10:37 +0800	[diff] [blame]	549	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
				550	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Prabhakar Kushwaha	35fe948	2013-01-23 17:59:57 +0000	[diff] [blame]	551
York Sun	3d2972f	2013-03-25 07:40:05 +0000	[diff] [blame]	552	#elif defined(CONFIG_PPC_T4240) \|\| defined(CONFIG_PPC_T4160)
				553	#define CONFIG_E6500
York Sun	ffd06e0	2012-10-08 07:44:30 +0000	[diff] [blame]	554	#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun	9e75875	2012-10-08 07:44:19 +0000	[diff] [blame]	555	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
				556	#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
York Sun	f698143	2013-03-25 07:40:07 +0000	[diff] [blame]	557	#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
York Sun	9e75875	2012-10-08 07:44:19 +0000	[diff] [blame]	558	#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
York Sun	3d2972f	2013-03-25 07:40:05 +0000	[diff] [blame]	559	#ifdef CONFIG_PPC_T4240
York Sun	9e75875	2012-10-08 07:44:19 +0000	[diff] [blame]	560	#define CONFIG_MAX_CPUS 12
York Sun	9e75875	2012-10-08 07:44:19 +0000	[diff] [blame]	561	#define CONFIG_SYS_NUM_FM1_DTSEC 8
				562	#define CONFIG_SYS_NUM_FM1_10GEC 2
				563	#define CONFIG_SYS_NUM_FM2_DTSEC 8
				564	#define CONFIG_SYS_NUM_FM2_10GEC 2
				565	#define CONFIG_NUM_DDR_CONTROLLERS 3
York Sun	3d2972f	2013-03-25 07:40:05 +0000	[diff] [blame]	566	#else
York Sun	b624084	2013-03-25 07:33:29 +0000	[diff] [blame]	567	#define CONFIG_MAX_CPUS 8
York Sun	3d2972f	2013-03-25 07:40:05 +0000	[diff] [blame]	568	#define CONFIG_SYS_NUM_FM1_DTSEC 7
				569	#define CONFIG_SYS_NUM_FM1_10GEC 1
				570	#define CONFIG_SYS_NUM_FM2_DTSEC 7
				571	#define CONFIG_SYS_NUM_FM2_10GEC 1
				572	#define CONFIG_NUM_DDR_CONTROLLERS 2
				573	#endif
York Sun	b624084	2013-03-25 07:33:29 +0000	[diff] [blame]	574	#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
				575	#define CONFIG_SYS_FSL_NUM_LAWS 32
Prabhakar Kushwaha	a4c955b	2013-07-31 16:56:41 +0530	[diff] [blame]	576	#define CONFIG_SYS_FSL_SRDS_1
				577	#define CONFIG_SYS_FSL_SRDS_2
York Sun	b624084	2013-03-25 07:33:29 +0000	[diff] [blame]	578	#define CONFIG_SYS_FSL_SRDS_3
				579	#define CONFIG_SYS_FSL_SRDS_4
				580	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				581	#define CONFIG_SYS_NUM_FMAN 2
York Sun	b624084	2013-03-25 07:33:29 +0000	[diff] [blame]	582	#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Mingkai Hu	362ee04	2013-05-16 10:18:13 +0800	[diff] [blame]	583	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
York Sun	b624084	2013-03-25 07:33:29 +0000	[diff] [blame]	584	#define CONFIG_SYS_FMAN_V3
				585	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
				586	#define CONFIG_SYS_FSL_TBCLK_DIV 16
				587	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
				588	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				589	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				590	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Liu Gang	0804793	2013-06-25 18:12:14 +0800	[diff] [blame]	591	#define CONFIG_SYS_FSL_SRIO_LIODN
York Sun	b624084	2013-03-25 07:33:29 +0000	[diff] [blame]	592	#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
				593	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
				594	#define CONFIG_SYS_FSL_ERRATUM_A004468
				595	#define CONFIG_SYS_FSL_ERRATUM_A_004934
				596	#define CONFIG_SYS_FSL_ERRATUM_A005871
Scott Wood	8212519	2013-05-15 17:50:13 -0500	[diff] [blame]	597	#define CONFIG_SYS_FSL_ERRATUM_A006593
York Sun	b624084	2013-03-25 07:33:29 +0000	[diff] [blame]	598	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				599	#define CONFIG_SYS_FSL_PCI_VER_3_X
				600
Poonam Aggrwal	8fa0102	2013-03-25 07:40:20 +0000	[diff] [blame]	601	#elif defined(CONFIG_PPC_B4860) \|\| defined(CONFIG_PPC_B4420)
				602	#define CONFIG_E6500
Poonam Aggrwal	e1dbdd8	2012-12-23 19:24:16 +0000	[diff] [blame]	603	#define CONFIG_SYS_PPC64 /* 64-bit core */
				604	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
				605	#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
				606	#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
Poonam Aggrwal	e1dbdd8	2012-12-23 19:24:16 +0000	[diff] [blame]	607	#define CONFIG_SYS_FSL_NUM_LAWS 32
Prabhakar Kushwaha	a4c955b	2013-07-31 16:56:41 +0530	[diff] [blame]	608	#define CONFIG_SYS_FSL_SRDS_1
				609	#define CONFIG_SYS_FSL_SRDS_2
Poonam Aggrwal	e1dbdd8	2012-12-23 19:24:16 +0000	[diff] [blame]	610	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				611	#define CONFIG_SYS_NUM_FMAN 1
Poonam Aggrwal	e1dbdd8	2012-12-23 19:24:16 +0000	[diff] [blame]	612	#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Mingkai Hu	362ee04	2013-05-16 10:18:13 +0800	[diff] [blame]	613	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
Poonam Aggrwal	e1dbdd8	2012-12-23 19:24:16 +0000	[diff] [blame]	614	#define CONFIG_SYS_FMAN_V3
				615	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
				616	#define CONFIG_SYS_FSL_TBCLK_DIV 16
				617	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
				618	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				619	#define CONFIG_SYS_FSL_ERRATUM_A_004934
Shengzhou Liu	04feb57	2013-02-27 21:56:54 +0000	[diff] [blame]	620	#define CONFIG_SYS_FSL_ERRATUM_A005871
Scott Wood	8212519	2013-05-15 17:50:13 -0500	[diff] [blame]	621	#define CONFIG_SYS_FSL_ERRATUM_A006593
Poonam Aggrwal	e1dbdd8	2012-12-23 19:24:16 +0000	[diff] [blame]	622	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				623
Poonam Aggrwal	8fa0102	2013-03-25 07:40:20 +0000	[diff] [blame]	624	#ifdef CONFIG_PPC_B4860
York Sun	f698143	2013-03-25 07:40:07 +0000	[diff] [blame]	625	#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
York Sun	d240414	2012-10-08 07:44:20 +0000	[diff] [blame]	626	#define CONFIG_MAX_CPUS 4
				627	#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
York Sun	d240414	2012-10-08 07:44:20 +0000	[diff] [blame]	628	#define CONFIG_SYS_NUM_FM1_DTSEC 6
				629	#define CONFIG_SYS_NUM_FM1_10GEC 2
Poonam Aggrwal	e394ceb	2012-12-23 19:22:33 +0000	[diff] [blame]	630	#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun	d240414	2012-10-08 07:44:20 +0000	[diff] [blame]	631	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				632	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				633	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Liu Gang	32f38ee	2013-06-25 18:12:13 +0800	[diff] [blame]	634	#define CONFIG_SYS_FSL_SRIO_LIODN
Poonam Aggrwal	8fa0102	2013-03-25 07:40:20 +0000	[diff] [blame]	635	#else
				636	#define CONFIG_MAX_CPUS 2
				637	#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
				638	#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
				639	#define CONFIG_SYS_NUM_FM1_DTSEC 4
				640	#define CONFIG_SYS_NUM_FM1_10GEC 0
				641	#define CONFIG_NUM_DDR_CONTROLLERS 1
				642	#endif
York Sun	d240414	2012-10-08 07:44:20 +0000	[diff] [blame]	643
York Sun	5f208d1	2013-03-25 07:40:06 +0000	[diff] [blame]	644	#elif defined(CONFIG_PPC_T1040)
				645	#define CONFIG_E5500
				646	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
				647	#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
York Sun	f698143	2013-03-25 07:40:07 +0000	[diff] [blame]	648	#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
York Sun	5f208d1	2013-03-25 07:40:06 +0000	[diff] [blame]	649	#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
Prabhakar Kushwaha	1d384ec	2013-09-03 11:19:54 +0530	[diff] [blame^]	650	#if defined(CONFIG_PPC_T1040) \|\| defined(CONFIG_PPC_T1042)
York Sun	5f208d1	2013-03-25 07:40:06 +0000	[diff] [blame]	651	#define CONFIG_MAX_CPUS 4
Prabhakar Kushwaha	1d384ec	2013-09-03 11:19:54 +0530	[diff] [blame^]	652	#elif defined(CONFIG_PPC_T1020) \|\| defined(CONFIG_PPC_T1022)
				653	#define CONFIG_MAX_CPUS 2
				654	#endif
				655	#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
York Sun	5f208d1	2013-03-25 07:40:06 +0000	[diff] [blame]	656	#define CONFIG_SYS_FSL_NUM_LAWS 16
Prabhakar Kushwaha	1d384ec	2013-09-03 11:19:54 +0530	[diff] [blame^]	657	#define CONFIG_SYS_FSL_SRDS_1
				658	#define CONFIG_SYS_FSL_SEC_COMPAT 5
York Sun	5f208d1	2013-03-25 07:40:06 +0000	[diff] [blame]	659	#define CONFIG_SYS_NUM_FMAN 1
				660	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				661	#define CONFIG_NUM_DDR_CONTROLLERS 1
Prabhakar Kushwaha	1d384ec	2013-09-03 11:19:54 +0530	[diff] [blame^]	662	#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
				663	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
York Sun	5f208d1	2013-03-25 07:40:06 +0000	[diff] [blame]	664	#define CONFIG_SYS_FMAN_V3
Prabhakar Kushwaha	1d384ec	2013-09-03 11:19:54 +0530	[diff] [blame^]	665	#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
York Sun	5f208d1	2013-03-25 07:40:06 +0000	[diff] [blame]	666	#define CONFIG_SYS_FSL_TBCLK_DIV 32
				667	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
York Sun	5f208d1	2013-03-25 07:40:06 +0000	[diff] [blame]	668	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				669	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
				670	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
				671	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				672
Mingkai Hu	3b75e98	2013-07-04 17:30:36 +0800	[diff] [blame]	673	#elif defined(CONFIG_PPC_C29X)
				674	#define CONFIG_MAX_CPUS 1
				675	#define CONFIG_FSL_SDHC_V2_3
				676	#define CONFIG_SYS_FSL_NUM_LAWS 12
				677	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
				678	#define CONFIG_TSECV2_1
				679	#define CONFIG_SYS_FSL_SEC_COMPAT 6
				680	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				681	#define CONFIG_NUM_DDR_CONTROLLERS 1
				682	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
				683	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun	954a1a4	2013-08-20 15:09:43 -0700	[diff] [blame]	684	#define CONFIG_SYS_FSL_ERRATUM_A005125
Mingkai Hu	3b75e98	2013-07-04 17:30:36 +0800	[diff] [blame]	685
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	686	#else
				687	#error Processor type not defined for this platform
				688	#endif
				689
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	690	#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
				691	#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
				692	#endif
				693
York Sun	f698143	2013-03-25 07:40:07 +0000	[diff] [blame]	694	#ifdef CONFIG_E6500
				695	#define CONFIG_SYS_FSL_THREADS_PER_CORE 2
				696	#else
				697	#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
				698	#endif
				699
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	700	#endif /* _ASM_MPC85xx_CONFIG_H_ */