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Kumar Gala243be8e2011-01-19 03:05:26 -06001/*
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +00002 * Copyright 2011-2012 Freescale Semiconductor, Inc.
Kumar Gala243be8e2011-01-19 03:05:26 -06003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala243be8e2011-01-19 03:05:26 -06005 */
6
7#ifndef _ASM_MPC85xx_CONFIG_H_
8#define _ASM_MPC85xx_CONFIG_H_
9
10/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
11
Timur Tabie46fedf2011-08-04 18:03:41 -050012#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
13#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
14#endif
15
York Sun2a5fcb82012-10-28 08:12:54 +000016/*
17 * This macro should be removed when we no longer care about backwards
18 * compatibility with older operating systems.
19 */
20#define CONFIG_PPC_SPINTABLE_COMPATIBLE
21
York Sun34e026f2014-03-27 17:54:47 -070022#include <fsl_ddrc_version.h>
23#define CONFIG_SYS_FSL_DDR_BE
York Sun57495e42012-10-08 07:44:22 +000024
Prabhakar Kushwaha1b4175d2014-01-18 12:28:30 +053025/* IP endianness */
26#define CONFIG_SYS_FSL_IFC_BE
Ruchika Gupta028dbb82014-09-09 11:50:31 +053027#define CONFIG_SYS_FSL_SEC_BE
gaurav ranaa2e225e2015-02-27 09:43:49 +053028#define CONFIG_SYS_FSL_SFP_BE
gaurav ranae04916a2015-02-27 09:46:17 +053029#define CONFIG_SYS_FSL_SEC_MON_BE
Prabhakar Kushwaha1b4175d2014-01-18 12:28:30 +053030
Kumar Gala243be8e2011-01-19 03:05:26 -060031/* Number of TLB CAM entries we have on FSL Book-E chips */
32#if defined(CONFIG_E500MC)
33#define CONFIG_SYS_NUM_TLBCAMS 64
34#elif defined(CONFIG_E500)
35#define CONFIG_SYS_NUM_TLBCAMS 16
36#endif
37
38#if defined(CONFIG_MPC8536)
39#define CONFIG_MAX_CPUS 1
40#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +000041#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
Kumar Gala243be8e2011-01-19 03:05:26 -060042#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -050043#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun9855b3b2014-05-23 13:15:00 -070044#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -070045#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -060046
Wolfgang Denkd1a24f02011-02-02 22:36:10 +010047#elif defined(CONFIG_MPC8540)
Kumar Gala243be8e2011-01-19 03:05:26 -060048#define CONFIG_MAX_CPUS 1
49#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -070050#define CONFIG_SYS_FSL_DDRC_GEN1
Timur Tabie46fedf2011-08-04 18:03:41 -050051#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -060052
Wolfgang Denkd1a24f02011-02-02 22:36:10 +010053#elif defined(CONFIG_MPC8541)
Kumar Gala243be8e2011-01-19 03:05:26 -060054#define CONFIG_MAX_CPUS 1
55#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -070056#define CONFIG_SYS_FSL_DDRC_GEN1
Kumar Gala243be8e2011-01-19 03:05:26 -060057#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -050058#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -060059
60#elif defined(CONFIG_MPC8544)
61#define CONFIG_MAX_CPUS 1
62#define CONFIG_SYS_FSL_NUM_LAWS 10
York Sun5614e712013-09-30 09:22:09 -070063#define CONFIG_SYS_FSL_DDRC_GEN2
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +000064#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala243be8e2011-01-19 03:05:26 -060065#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -050066#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun954a1a42013-08-20 15:09:43 -070067#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -060068
69#elif defined(CONFIG_MPC8548)
70#define CONFIG_MAX_CPUS 1
71#define CONFIG_SYS_FSL_NUM_LAWS 10
York Sun5614e712013-09-30 09:22:09 -070072#define CONFIG_SYS_FSL_DDRC_GEN2
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +000073#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala243be8e2011-01-19 03:05:26 -060074#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -050075#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala5ace2992011-09-16 09:54:30 -050076#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
Kumar Gala2b3a1cd2011-10-03 08:37:57 -050077#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
chenhui zhaoaada81d2011-10-03 08:38:50 -050078#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
Liu Gang7d67ed52012-03-08 00:33:14 +000079#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
80#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
81#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
82#define CONFIG_SYS_FSL_RMU
83#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun954a1a42013-08-20 15:09:43 -070084#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan9c3f77e2013-08-16 15:10:37 +080085#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
86#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
Kumar Gala243be8e2011-01-19 03:05:26 -060087
88#elif defined(CONFIG_MPC8555)
89#define CONFIG_MAX_CPUS 1
90#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -070091#define CONFIG_SYS_FSL_DDRC_GEN1
Kumar Gala243be8e2011-01-19 03:05:26 -060092#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -050093#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -060094
95#elif defined(CONFIG_MPC8560)
96#define CONFIG_MAX_CPUS 1
97#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -070098#define CONFIG_SYS_FSL_DDRC_GEN1
Timur Tabie46fedf2011-08-04 18:03:41 -050099#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600100
101#elif defined(CONFIG_MPC8568)
102#define CONFIG_MAX_CPUS 1
103#define CONFIG_SYS_FSL_NUM_LAWS 10
York Sun5614e712013-09-30 09:22:09 -0700104#define CONFIG_SYS_FSL_DDRC_GEN2
Kumar Gala243be8e2011-01-19 03:05:26 -0600105#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galafdb4dad2011-01-31 23:09:25 -0600106#define QE_MURAM_SIZE 0x10000UL
107#define MAX_QE_RISC 2
108#define QE_NUM_OF_SNUM 28
Timur Tabie46fedf2011-08-04 18:03:41 -0500109#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang7d67ed52012-03-08 00:33:14 +0000110#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
111#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
112#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
113#define CONFIG_SYS_FSL_RMU
114#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600115
116#elif defined(CONFIG_MPC8569)
117#define CONFIG_MAX_CPUS 1
118#define CONFIG_SYS_FSL_NUM_LAWS 10
119#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galafdb4dad2011-01-31 23:09:25 -0600120#define QE_MURAM_SIZE 0x20000UL
121#define MAX_QE_RISC 4
122#define QE_NUM_OF_SNUM 46
Timur Tabie46fedf2011-08-04 18:03:41 -0500123#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang7d67ed52012-03-08 00:33:14 +0000124#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
125#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
126#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
127#define CONFIG_SYS_FSL_RMU
128#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun9855b3b2014-05-23 13:15:00 -0700129#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700130#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600131
132#elif defined(CONFIG_MPC8572)
133#define CONFIG_MAX_CPUS 2
134#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +0000135#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600136#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500137#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Suneb0aff72011-01-25 21:51:27 -0800138#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sun91671912011-01-25 22:05:49 -0800139#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
York Sun9855b3b2014-05-23 13:15:00 -0700140#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700141#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600142
143#elif defined(CONFIG_P1010)
144#define CONFIG_MAX_CPUS 1
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530145#define CONFIG_FSL_SDHC_V2_3
Kumar Gala243be8e2011-01-19 03:05:26 -0600146#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000147#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala243be8e2011-01-19 03:05:26 -0600148#define CONFIG_TSECV2
149#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530150#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
151#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530152#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Mingkai Hu362ee042013-05-16 10:18:13 +0800153#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530154#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala8f290842011-05-20 00:39:21 -0500155#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530156#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal42aee642011-06-30 03:00:28 -0500157#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalfb855f42011-06-29 16:32:52 +0530158#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Shengzhou Liu424bf942013-08-15 09:31:47 +0800159#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
Poonam Aggrwalbc6bbd62011-07-07 20:36:47 +0530160#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
York Sun954a1a42013-08-20 15:09:43 -0700161#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800162#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
York Sun9855b3b2014-05-23 13:15:00 -0700163#define CONFIG_SYS_FSL_ERRATUM_A004508
Nikhil Badola11856912014-02-26 17:43:15 +0530164#define CONFIG_SYS_FSL_ERRATUM_A007075
Suresh Gupta9c641a82014-02-26 14:29:12 +0530165#define CONFIG_SYS_FSL_ERRATUM_A006261
Nikhil Badola0dc78ff2014-11-21 17:25:21 +0530166#define CONFIG_SYS_FSL_ERRATUM_A004477
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800167#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
Haijun.Zhangf28bea02014-01-10 13:52:19 +0800168#define CONFIG_ESDHC_HC_BLK_ADDR
Kumar Gala243be8e2011-01-19 03:05:26 -0600169
Kumar Gala093cffb2011-02-05 13:45:07 -0600170/* P1011 is single core version of P1020 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600171#elif defined(CONFIG_P1011)
172#define CONFIG_MAX_CPUS 1
173#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000174#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600175#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000176#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600177#define CONFIG_SYS_FSL_SEC_COMPAT 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530178#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500179#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600180#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
181#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun9855b3b2014-05-23 13:15:00 -0700182#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700183#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600184
Kumar Gala093cffb2011-02-05 13:45:07 -0600185/* P1012 is single core version of P1021 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600186#elif defined(CONFIG_P1012)
187#define CONFIG_MAX_CPUS 1
188#define CONFIG_SYS_FSL_NUM_LAWS 12
ramneek mehreshf1810d82013-10-18 17:40:17 +0530189#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000190#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600191#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000192#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600193#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500194#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600195#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
196#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600197#define QE_MURAM_SIZE 0x6000UL
198#define MAX_QE_RISC 1
199#define QE_NUM_OF_SNUM 28
York Sun9855b3b2014-05-23 13:15:00 -0700200#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700201#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600202
Kumar Gala093cffb2011-02-05 13:45:07 -0600203/* P1013 is single core version of P1022 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600204#elif defined(CONFIG_P1013)
205#define CONFIG_MAX_CPUS 1
206#define CONFIG_SYS_FSL_NUM_LAWS 12
Ying Zhang703f5682015-01-30 14:52:11 +0800207#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000208#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600209#define CONFIG_TSECV2
210#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500211#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang2d7534a2011-01-30 17:06:20 -0600212#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
213#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
214#define CONFIG_FSL_SATA_ERRATUM_A001
York Sun9855b3b2014-05-23 13:15:00 -0700215#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700216#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600217
218#elif defined(CONFIG_P1014)
219#define CONFIG_MAX_CPUS 1
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530220#define CONFIG_FSL_SDHC_V2_3
Kumar Gala243be8e2011-01-19 03:05:26 -0600221#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000222#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala243be8e2011-01-19 03:05:26 -0600223#define CONFIG_TSECV2
224#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530225#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
226#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530227#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530228#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530229#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal42aee642011-06-30 03:00:28 -0500230#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalfb855f42011-06-29 16:32:52 +0530231#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwalbc6bbd62011-07-07 20:36:47 +0530232#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
York Sun9855b3b2014-05-23 13:15:00 -0700233#define CONFIG_SYS_FSL_ERRATUM_A004508
Kumar Gala243be8e2011-01-19 03:05:26 -0600234
Kumar Gala093cffb2011-02-05 13:45:07 -0600235/* P1017 is single core version of P1023 */
Roy Zang67a719d2011-02-03 22:14:19 -0600236#elif defined(CONFIG_P1017)
237#define CONFIG_MAX_CPUS 1
238#define CONFIG_SYS_FSL_NUM_LAWS 12
239#define CONFIG_SYS_FSL_SEC_COMPAT 4
240#define CONFIG_SYS_NUM_FMAN 1
241#define CONFIG_SYS_NUM_FM1_DTSEC 2
242#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530243#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Roy Zang67a719d2011-02-03 22:14:19 -0600244#define CONFIG_SYS_QMAN_NUM_PORTALS 3
245#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galac657d892011-02-04 00:43:34 -0600246#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala8f290842011-05-20 00:39:21 -0500247#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500248#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
York Sun9855b3b2014-05-23 13:15:00 -0700249#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700250#define CONFIG_SYS_FSL_ERRATUM_A005125
Roy Zang67a719d2011-02-03 22:14:19 -0600251
Kumar Gala243be8e2011-01-19 03:05:26 -0600252#elif defined(CONFIG_P1020)
253#define CONFIG_MAX_CPUS 2
254#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000255#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600256#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000257#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600258#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500259#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600260#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
261#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun9855b3b2014-05-23 13:15:00 -0700262#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700263#define CONFIG_SYS_FSL_ERRATUM_A005125
ramneek mehresh80ba6a62014-05-13 15:36:07 +0530264#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
ramneek mehreshf1810d82013-10-18 17:40:17 +0530265#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
ramneek mehresh80ba6a62014-05-13 15:36:07 +0530266#endif
Kumar Gala243be8e2011-01-19 03:05:26 -0600267
268#elif defined(CONFIG_P1021)
269#define CONFIG_MAX_CPUS 2
270#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000271#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600272#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000273#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600274#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500275#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600276#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
277#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600278#define QE_MURAM_SIZE 0x6000UL
279#define MAX_QE_RISC 1
280#define QE_NUM_OF_SNUM 28
York Sun9855b3b2014-05-23 13:15:00 -0700281#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700282#define CONFIG_SYS_FSL_ERRATUM_A005125
ramneek mehreshf1810d82013-10-18 17:40:17 +0530283#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Kumar Gala243be8e2011-01-19 03:05:26 -0600284
285#elif defined(CONFIG_P1022)
286#define CONFIG_MAX_CPUS 2
287#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000288#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600289#define CONFIG_TSECV2
290#define CONFIG_SYS_FSL_SEC_COMPAT 2
Ying Zhang703f5682015-01-30 14:52:11 +0800291#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Timur Tabie46fedf2011-08-04 18:03:41 -0500292#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang2d7534a2011-01-30 17:06:20 -0600293#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
294#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
295#define CONFIG_FSL_SATA_ERRATUM_A001
York Sun9855b3b2014-05-23 13:15:00 -0700296#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700297#define CONFIG_SYS_FSL_ERRATUM_A005125
Nikhil Badola0dc78ff2014-11-21 17:25:21 +0530298#define CONFIG_SYS_FSL_ERRATUM_A004477
Kumar Gala243be8e2011-01-19 03:05:26 -0600299
Roy Zang67a719d2011-02-03 22:14:19 -0600300#elif defined(CONFIG_P1023)
301#define CONFIG_MAX_CPUS 2
302#define CONFIG_SYS_FSL_NUM_LAWS 12
303#define CONFIG_SYS_FSL_SEC_COMPAT 4
304#define CONFIG_SYS_NUM_FMAN 1
305#define CONFIG_SYS_NUM_FM1_DTSEC 2
306#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530307#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Roy Zang67a719d2011-02-03 22:14:19 -0600308#define CONFIG_SYS_QMAN_NUM_PORTALS 3
309#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galac657d892011-02-04 00:43:34 -0600310#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala8f290842011-05-20 00:39:21 -0500311#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500312#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
York Sun9855b3b2014-05-23 13:15:00 -0700313#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700314#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800315#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
316#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Roy Zang67a719d2011-02-03 22:14:19 -0600317
Kumar Gala093cffb2011-02-05 13:45:07 -0600318/* P1024 is lower end variant of P1020 */
319#elif defined(CONFIG_P1024)
320#define CONFIG_MAX_CPUS 2
321#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000322#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala093cffb2011-02-05 13:45:07 -0600323#define CONFIG_TSECV2
324#define CONFIG_FSL_PCIE_DISABLE_ASPM
325#define CONFIG_SYS_FSL_SEC_COMPAT 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530326#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500327#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600328#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
329#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun9855b3b2014-05-23 13:15:00 -0700330#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700331#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala093cffb2011-02-05 13:45:07 -0600332
333/* P1025 is lower end variant of P1021 */
334#elif defined(CONFIG_P1025)
335#define CONFIG_MAX_CPUS 2
336#define CONFIG_SYS_FSL_NUM_LAWS 12
ramneek mehreshf1810d82013-10-18 17:40:17 +0530337#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000338#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala093cffb2011-02-05 13:45:07 -0600339#define CONFIG_TSECV2
340#define CONFIG_FSL_PCIE_DISABLE_ASPM
341#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500342#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600343#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
344#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600345#define QE_MURAM_SIZE 0x6000UL
346#define MAX_QE_RISC 1
347#define QE_NUM_OF_SNUM 28
York Sun9855b3b2014-05-23 13:15:00 -0700348#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700349#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala093cffb2011-02-05 13:45:07 -0600350
351/* P2010 is single core version of P2020 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600352#elif defined(CONFIG_P2010)
353#define CONFIG_MAX_CPUS 1
354#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000355#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600356#define CONFIG_SYS_FSL_SEC_COMPAT 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530357#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Timur Tabie46fedf2011-08-04 18:03:41 -0500358#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala6e7f0bc02011-01-26 01:43:15 -0600359#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala5103a032011-01-29 15:36:10 -0600360#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
York Sun9855b3b2014-05-23 13:15:00 -0700361#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700362#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600363
364#elif defined(CONFIG_P2020)
365#define CONFIG_MAX_CPUS 2
366#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000367#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600368#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500369#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala6e7f0bc02011-01-26 01:43:15 -0600370#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala5103a032011-01-29 15:36:10 -0600371#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Liu Gang7d67ed52012-03-08 00:33:14 +0000372#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
373#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
374#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
375#define CONFIG_SYS_FSL_RMU
376#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun9855b3b2014-05-23 13:15:00 -0700377#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700378#define CONFIG_SYS_FSL_ERRATUM_A005125
Nikhil Badola0dc78ff2014-11-21 17:25:21 +0530379#define CONFIG_SYS_FSL_ERRATUM_A004477
ramneek mehreshf1810d82013-10-18 17:40:17 +0530380#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
York Sun9855b3b2014-05-23 13:15:00 -0700381
Scott Wood3e978f52012-08-14 10:14:51 +0000382#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
York Sund1001e32012-10-08 07:44:15 +0000383#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700384#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala1f979872011-05-13 01:16:07 -0500385#define CONFIG_MAX_CPUS 4
386#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
387#define CONFIG_SYS_FSL_NUM_LAWS 32
388#define CONFIG_SYS_FSL_SEC_COMPAT 4
389#define CONFIG_SYS_NUM_FMAN 1
390#define CONFIG_SYS_NUM_FM1_DTSEC 5
391#define CONFIG_SYS_NUM_FM1_10GEC 1
392#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530393#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Kumar Gala1f979872011-05-13 01:16:07 -0500394#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
395#define CONFIG_SYS_FSL_TBCLK_DIV 32
396#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500397#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala1f979872011-05-13 01:16:07 -0500398#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
399#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500400#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala1f979872011-05-13 01:16:07 -0500401#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun5e23ab02012-05-07 07:26:47 +0000402#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei99d7b0a2013-03-11 17:56:34 +0000403#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala43f082b2011-11-22 06:51:15 -0600404#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sune22be772013-03-25 07:30:11 +0000405#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun41085082011-11-20 10:01:35 -0800406#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000407#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
408#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
409#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000410#define CONFIG_SYS_FSL_ERRATUM_A004510
411#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
412#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
413#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000414#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi01180332012-10-25 12:40:00 +0000415#define CONFIG_SYS_FSL_ERRATUM_A004849
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800416#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Suresh Gupta9c641a82014-02-26 14:29:12 +0530417#define CONFIG_SYS_FSL_ERRATUM_A006261
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800418#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Kumar Gala1f979872011-05-13 01:16:07 -0500419
Kumar Gala243be8e2011-01-19 03:05:26 -0600420#elif defined(CONFIG_PPC_P3041)
York Sund1001e32012-10-08 07:44:15 +0000421#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700422#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala243be8e2011-01-19 03:05:26 -0600423#define CONFIG_MAX_CPUS 4
Kumar Galab5c87532011-02-16 02:03:29 -0600424#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600425#define CONFIG_SYS_FSL_NUM_LAWS 32
426#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galafbee0f72011-01-25 12:42:32 -0600427#define CONFIG_SYS_NUM_FMAN 1
428#define CONFIG_SYS_NUM_FM1_DTSEC 5
429#define CONFIG_SYS_NUM_FM1_10GEC 1
430#define CONFIG_NUM_DDR_CONTROLLERS 1
York Sun34e026f2014-03-27 17:54:47 -0700431#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
Kumar Galac657d892011-02-04 00:43:34 -0600432#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600433#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala8f290842011-05-20 00:39:21 -0500434#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500435#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang86221f02011-04-13 00:08:51 -0500436#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
437#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500438#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
ramneek mehreshf1810d82013-10-18 17:40:17 +0530439#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Lei Xu30009762011-04-19 15:28:41 +0800440#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun57125f22012-08-08 18:04:53 +0000441#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei99d7b0a2013-03-11 17:56:34 +0000442#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala43f082b2011-11-22 06:51:15 -0600443#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sune22be772013-03-25 07:30:11 +0000444#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun41085082011-11-20 10:01:35 -0800445#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000446#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
447#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
448#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000449#define CONFIG_SYS_FSL_ERRATUM_A004510
450#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
451#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
452#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000453#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi01180332012-10-25 12:40:00 +0000454#define CONFIG_SYS_FSL_ERRATUM_A004849
York Sund217a9a2013-06-25 11:37:49 -0700455#define CONFIG_SYS_FSL_ERRATUM_A005812
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800456#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Suresh Gupta9c641a82014-02-26 14:29:12 +0530457#define CONFIG_SYS_FSL_ERRATUM_A006261
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800458#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala243be8e2011-01-19 03:05:26 -0600459
Scott Wood3e978f52012-08-14 10:14:51 +0000460#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
York Sund1001e32012-10-08 07:44:15 +0000461#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700462#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala243be8e2011-01-19 03:05:26 -0600463#define CONFIG_MAX_CPUS 8
Kumar Galab5c87532011-02-16 02:03:29 -0600464#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Gala243be8e2011-01-19 03:05:26 -0600465#define CONFIG_SYS_FSL_NUM_LAWS 32
466#define CONFIG_SYS_FSL_SEC_COMPAT 4
467#define CONFIG_SYS_NUM_FMAN 2
468#define CONFIG_SYS_NUM_FM1_DTSEC 4
469#define CONFIG_SYS_NUM_FM2_DTSEC 4
470#define CONFIG_SYS_NUM_FM1_10GEC 1
471#define CONFIG_SYS_NUM_FM2_10GEC 1
472#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700473#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530474#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Kumar Galac657d892011-02-04 00:43:34 -0600475#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600476#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala8f290842011-05-20 00:39:21 -0500477#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabie46fedf2011-08-04 18:03:41 -0500478#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala243be8e2011-01-19 03:05:26 -0600479#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
480#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sunfa8d23c2011-01-10 12:03:01 +0000481#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Gala243be8e2011-01-19 03:05:26 -0600482#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
483#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
484#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
Zang Roy-R619114e0be342012-09-18 09:50:08 +0000485#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
Kumar Gala243be8e2011-01-19 03:05:26 -0600486#define CONFIG_SYS_P4080_ERRATUM_CPU22
York Sun5e23ab02012-05-07 07:26:47 +0000487#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala243be8e2011-01-19 03:05:26 -0600488#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medvedf8af0b2010-08-31 22:57:38 -0500489#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabid90fdba2011-04-18 17:16:00 -0500490#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabida30b9f2011-04-01 13:19:36 -0500491#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Gala43f082b2011-11-22 06:51:15 -0600492#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun41085082011-11-20 10:01:35 -0800493#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000494#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
495#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
496#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
497#define CONFIG_SYS_FSL_RMU
498#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Scott Wood33eee332012-08-14 10:14:53 +0000499#define CONFIG_SYS_FSL_ERRATUM_A004510
500#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
501#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
Liu Gangd59c5572012-09-28 21:26:19 +0000502#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi01180332012-10-25 12:40:00 +0000503#define CONFIG_SYS_FSL_ERRATUM_A004849
Timur Tabid607b962012-11-01 08:20:23 +0000504#define CONFIG_SYS_FSL_ERRATUM_A004580
Yuanquan Chenc0a4e6b2012-11-26 23:49:45 +0000505#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
York Sund217a9a2013-06-25 11:37:49 -0700506#define CONFIG_SYS_FSL_ERRATUM_A005812
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800507#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Nikhil Badola11856912014-02-26 17:43:15 +0530508#define CONFIG_SYS_FSL_ERRATUM_A007075
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800509#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala243be8e2011-01-19 03:05:26 -0600510
Scott Wood3e978f52012-08-14 10:14:51 +0000511#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
York Sunffd06e02012-10-08 07:44:30 +0000512#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sund1001e32012-10-08 07:44:15 +0000513#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700514#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala243be8e2011-01-19 03:05:26 -0600515#define CONFIG_MAX_CPUS 2
Kumar Galab5c87532011-02-16 02:03:29 -0600516#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600517#define CONFIG_SYS_FSL_NUM_LAWS 32
518#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galafbee0f72011-01-25 12:42:32 -0600519#define CONFIG_SYS_NUM_FMAN 1
520#define CONFIG_SYS_NUM_FM1_DTSEC 5
521#define CONFIG_SYS_NUM_FM1_10GEC 1
522#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700523#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530524#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Kumar Galac657d892011-02-04 00:43:34 -0600525#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600526#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala8f290842011-05-20 00:39:21 -0500527#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500528#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang86221f02011-04-13 00:08:51 -0500529#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
530#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500531#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu30009762011-04-19 15:28:41 +0800532#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei99d7b0a2013-03-11 17:56:34 +0000533#define CONFIG_SYS_FSL_ERRATUM_USB14
York Sune22be772013-03-25 07:30:11 +0000534#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun41085082011-11-20 10:01:35 -0800535#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000536#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
537#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
538#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000539#define CONFIG_SYS_FSL_ERRATUM_A004510
540#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
541#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000542#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800543#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Suresh Gupta9c641a82014-02-26 14:29:12 +0530544#define CONFIG_SYS_FSL_ERRATUM_A006261
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800545#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala243be8e2011-01-19 03:05:26 -0600546
Timur Tabi49054432012-10-05 11:09:19 +0000547#elif defined(CONFIG_PPC_P5040)
Timur Tabi1956e432012-10-23 10:48:09 +0000548#define CONFIG_SYS_PPC64
Timur Tabi49054432012-10-05 11:09:19 +0000549#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700550#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Timur Tabi49054432012-10-05 11:09:19 +0000551#define CONFIG_MAX_CPUS 4
552#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
553#define CONFIG_SYS_FSL_NUM_LAWS 32
554#define CONFIG_SYS_FSL_SEC_COMPAT 4
555#define CONFIG_SYS_NUM_FMAN 2
556#define CONFIG_SYS_NUM_FM1_DTSEC 5
557#define CONFIG_SYS_NUM_FM1_10GEC 1
558#define CONFIG_SYS_NUM_FM2_DTSEC 5
559#define CONFIG_SYS_NUM_FM2_10GEC 1
560#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700561#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530562#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Timur Tabi49054432012-10-05 11:09:19 +0000563#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
564#define CONFIG_SYS_FSL_TBCLK_DIV 16
565#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
566#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
567#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
568#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
569#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
570#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei99d7b0a2013-03-11 17:56:34 +0000571#define CONFIG_SYS_FSL_ERRATUM_USB14
Timur Tabi49054432012-10-05 11:09:19 +0000572#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
573#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
574#define CONFIG_SYS_FSL_ERRATUM_A004699
Timur Tabi49054432012-10-05 11:09:19 +0000575#define CONFIG_SYS_FSL_ERRATUM_A004510
576#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
Suresh Gupta9c641a82014-02-26 14:29:12 +0530577#define CONFIG_SYS_FSL_ERRATUM_A006261
Timur Tabi49054432012-10-05 11:09:19 +0000578#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
York Sund217a9a2013-06-25 11:37:49 -0700579#define CONFIG_SYS_FSL_ERRATUM_A005812
Timur Tabi49054432012-10-05 11:09:19 +0000580
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000581#elif defined(CONFIG_BSC9131)
582#define CONFIG_MAX_CPUS 1
583#define CONFIG_FSL_SDHC_V2_3
584#define CONFIG_SYS_FSL_NUM_LAWS 12
585#define CONFIG_TSECV2
586#define CONFIG_SYS_FSL_SEC_COMPAT 4
587#define CONFIG_NUM_DDR_CONTROLLERS 1
York Sun34e026f2014-03-27 17:54:47 -0700588#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530589#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Priyanka Jain765b0bd2013-04-04 09:31:54 +0530590#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
591#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
Mingkai Hu362ee042013-05-16 10:18:13 +0800592#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000593#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
594#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000595#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun954a1a42013-08-20 15:09:43 -0700596#define CONFIG_SYS_FSL_ERRATUM_A005125
Nikhil Badola0dc78ff2014-11-21 17:25:21 +0530597#define CONFIG_SYS_FSL_ERRATUM_A004477
Haijun.Zhangf28bea02014-01-10 13:52:19 +0800598#define CONFIG_ESDHC_HC_BLK_ADDR
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000599
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000600#elif defined(CONFIG_BSC9132)
601#define CONFIG_MAX_CPUS 2
602#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
603#define CONFIG_FSL_SDHC_V2_3
604#define CONFIG_SYS_FSL_NUM_LAWS 12
605#define CONFIG_TSECV2
606#define CONFIG_SYS_FSL_SEC_COMPAT 4
607#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700608#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
ramneek mehreshf1810d82013-10-18 17:40:17 +0530609#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Priyanka Jain64501c62013-07-02 09:21:04 +0530610#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
611#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
612#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
613#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
York Sun061ffed2013-04-18 19:31:01 -0700614#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000615#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
616#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000617#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
618#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
619#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
York Sun954a1a42013-08-20 15:09:43 -0700620#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lanf1a96ec2014-05-07 10:50:20 +0800621#define CONFIG_SYS_FSL_ERRATUM_A005434
Nikhil Badola0dc78ff2014-11-21 17:25:21 +0530622#define CONFIG_SYS_FSL_ERRATUM_A004477
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800623#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
624#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Haijun.Zhangf28bea02014-01-10 13:52:19 +0800625#define CONFIG_ESDHC_HC_BLK_ADDR
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000626
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800627#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
628 defined(CONFIG_PPC_T4080)
York Sun3d2972f2013-03-25 07:40:05 +0000629#define CONFIG_E6500
York Sunffd06e02012-10-08 07:44:30 +0000630#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun9e758752012-10-08 07:44:19 +0000631#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
632#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
York Sunf6981432013-03-25 07:40:07 +0000633#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
York Sun9e758752012-10-08 07:44:19 +0000634#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
York Sun3d2972f2013-03-25 07:40:05 +0000635#ifdef CONFIG_PPC_T4240
York Sun9e758752012-10-08 07:44:19 +0000636#define CONFIG_MAX_CPUS 12
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530637#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
York Sun9e758752012-10-08 07:44:19 +0000638#define CONFIG_SYS_NUM_FM1_DTSEC 8
639#define CONFIG_SYS_NUM_FM1_10GEC 2
640#define CONFIG_SYS_NUM_FM2_DTSEC 8
641#define CONFIG_SYS_NUM_FM2_10GEC 2
642#define CONFIG_NUM_DDR_CONTROLLERS 3
York Sun3d2972f2013-03-25 07:40:05 +0000643#else
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800644#define CONFIG_SYS_NUM_FM1_DTSEC 6
York Sun3d2972f2013-03-25 07:40:05 +0000645#define CONFIG_SYS_NUM_FM1_10GEC 1
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800646#define CONFIG_SYS_NUM_FM2_DTSEC 8
York Sun3d2972f2013-03-25 07:40:05 +0000647#define CONFIG_SYS_NUM_FM2_10GEC 1
648#define CONFIG_NUM_DDR_CONTROLLERS 2
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800649#if defined(CONFIG_PPC_T4160)
650#define CONFIG_MAX_CPUS 8
651#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
652#elif defined(CONFIG_PPC_T4080)
653#define CONFIG_MAX_CPUS 4
654#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 }
655#endif
York Sun3d2972f2013-03-25 07:40:05 +0000656#endif
York Sunb6240842013-03-25 07:33:29 +0000657#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
658#define CONFIG_SYS_FSL_NUM_LAWS 32
Prabhakar Kushwahaa4c955b2013-07-31 16:56:41 +0530659#define CONFIG_SYS_FSL_SRDS_1
660#define CONFIG_SYS_FSL_SRDS_2
York Sunb6240842013-03-25 07:33:29 +0000661#define CONFIG_SYS_FSL_SRDS_3
662#define CONFIG_SYS_FSL_SRDS_4
663#define CONFIG_SYS_FSL_SEC_COMPAT 4
664#define CONFIG_SYS_NUM_FMAN 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530665#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530666#define CONFIG_SYS_PME_CLK 0
York Sunb6240842013-03-25 07:33:29 +0000667#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Mingkai Hu362ee042013-05-16 10:18:13 +0800668#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
York Sunb6240842013-03-25 07:33:29 +0000669#define CONFIG_SYS_FMAN_V3
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530670#define CONFIG_SYS_FM1_CLK 3
671#define CONFIG_SYS_FM2_CLK 3
York Sunb6240842013-03-25 07:33:29 +0000672#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
673#define CONFIG_SYS_FSL_TBCLK_DIV 16
674#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
675#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
676#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
677#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Liu Gang08047932013-06-25 18:12:14 +0800678#define CONFIG_SYS_FSL_SRIO_LIODN
York Sunb6240842013-03-25 07:33:29 +0000679#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
680#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
681#define CONFIG_SYS_FSL_ERRATUM_A004468
682#define CONFIG_SYS_FSL_ERRATUM_A_004934
683#define CONFIG_SYS_FSL_ERRATUM_A005871
Suresh Gupta9c641a82014-02-26 14:29:12 +0530684#define CONFIG_SYS_FSL_ERRATUM_A006261
York Sun133fbfa2013-09-16 12:49:31 -0700685#define CONFIG_SYS_FSL_ERRATUM_A006379
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530686#define CONFIG_SYS_FSL_ERRATUM_A007186
Scott Wood82125192013-05-15 17:50:13 -0500687#define CONFIG_SYS_FSL_ERRATUM_A006593
Nikhil Badolaf3dff692014-10-17 09:12:07 +0530688#define CONFIG_SYS_FSL_ERRATUM_A007798
York Sunb6240842013-03-25 07:33:29 +0000689#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530690#define CONFIG_SYS_FSL_SFP_VER_3_0
York Sunb6240842013-03-25 07:33:29 +0000691#define CONFIG_SYS_FSL_PCI_VER_3_X
692
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000693#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
694#define CONFIG_E6500
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000695#define CONFIG_SYS_PPC64 /* 64-bit core */
696#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
697#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
698#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530699#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
700#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
701#define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000702#define CONFIG_SYS_FSL_NUM_LAWS 32
Prabhakar Kushwahaa4c955b2013-07-31 16:56:41 +0530703#define CONFIG_SYS_FSL_SRDS_1
704#define CONFIG_SYS_FSL_SRDS_2
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530705#define CONFIG_SYS_MAPLE
706#define CONFIG_SYS_CPRI
707#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000708#define CONFIG_SYS_FSL_SEC_COMPAT 4
709#define CONFIG_SYS_NUM_FMAN 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530710#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530711#define CONFIG_SYS_FM1_CLK 0
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530712#define CONFIG_SYS_CPRI_CLK 3
713#define CONFIG_SYS_ULB_CLK 4
714#define CONFIG_SYS_ETVPE_CLK 1
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000715#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Mingkai Hu362ee042013-05-16 10:18:13 +0800716#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000717#define CONFIG_SYS_FMAN_V3
718#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
719#define CONFIG_SYS_FSL_TBCLK_DIV 16
720#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
721#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
722#define CONFIG_SYS_FSL_ERRATUM_A_004934
Shengzhou Liu04feb572013-02-27 21:56:54 +0000723#define CONFIG_SYS_FSL_ERRATUM_A005871
York Sun133fbfa2013-09-16 12:49:31 -0700724#define CONFIG_SYS_FSL_ERRATUM_A006379
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530725#define CONFIG_SYS_FSL_ERRATUM_A007186
Scott Wood82125192013-05-15 17:50:13 -0500726#define CONFIG_SYS_FSL_ERRATUM_A006593
Nikhil Badola11856912014-02-26 17:43:15 +0530727#define CONFIG_SYS_FSL_ERRATUM_A007075
Shaveta Leekha7af9a072014-02-26 16:08:22 +0530728#define CONFIG_SYS_FSL_ERRATUM_A006475
729#define CONFIG_SYS_FSL_ERRATUM_A006384
York Sunc3678b02014-03-28 15:07:27 -0700730#define CONFIG_SYS_FSL_ERRATUM_A007212
Nikhil Badola0dc78ff2014-11-21 17:25:21 +0530731#define CONFIG_SYS_FSL_ERRATUM_A004477
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000732#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530733#define CONFIG_SYS_FSL_SFP_VER_3_0
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000734
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000735#ifdef CONFIG_PPC_B4860
York Sunf6981432013-03-25 07:40:07 +0000736#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
York Sund2404142012-10-08 07:44:20 +0000737#define CONFIG_MAX_CPUS 4
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530738#define CONFIG_MAX_DSP_CPUS 12
739#define CONFIG_NUM_DSP_CPUS 6
Shaveta Leekha6df82e32014-02-26 16:07:37 +0530740#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530741#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
York Sund2404142012-10-08 07:44:20 +0000742#define CONFIG_SYS_NUM_FM1_DTSEC 6
743#define CONFIG_SYS_NUM_FM1_10GEC 2
Poonam Aggrwale394ceb2012-12-23 19:22:33 +0000744#define CONFIG_NUM_DDR_CONTROLLERS 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530745#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
York Sund2404142012-10-08 07:44:20 +0000746#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
747#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
748#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Liu Gang32f38ee2013-06-25 18:12:13 +0800749#define CONFIG_SYS_FSL_SRIO_LIODN
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000750#else
751#define CONFIG_MAX_CPUS 2
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530752#define CONFIG_MAX_DSP_CPUS 2
Shaveta Leekha6df82e32014-02-26 16:07:37 +0530753#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000754#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530755#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000756#define CONFIG_SYS_NUM_FM1_DTSEC 4
757#define CONFIG_SYS_NUM_FM1_10GEC 0
758#define CONFIG_NUM_DDR_CONTROLLERS 1
759#endif
York Sund2404142012-10-08 07:44:20 +0000760
Priyanka Jain2967af62013-10-18 12:30:21 +0530761#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
762defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
York Sun5f208d12013-03-25 07:40:06 +0000763#define CONFIG_E5500
764#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
765#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
York Sunf6981432013-03-25 07:40:07 +0000766#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
York Sun5f208d12013-03-25 07:40:06 +0000767#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
York Sun34e026f2014-03-27 17:54:47 -0700768#ifdef CONFIG_SYS_FSL_DDR4
769#define CONFIG_SYS_FSL_DDRC_GEN4
770#endif
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530771#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
York Sun5f208d12013-03-25 07:40:06 +0000772#define CONFIG_MAX_CPUS 4
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530773#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
774#define CONFIG_MAX_CPUS 2
775#endif
776#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530777#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
York Sun5f208d12013-03-25 07:40:06 +0000778#define CONFIG_SYS_FSL_NUM_LAWS 16
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530779#define CONFIG_SYS_FSL_SRDS_1
780#define CONFIG_SYS_FSL_SEC_COMPAT 5
York Sun5f208d12013-03-25 07:40:06 +0000781#define CONFIG_SYS_NUM_FMAN 1
782#define CONFIG_SYS_NUM_FM1_DTSEC 5
783#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530784#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530785#define CONFIG_PME_PLAT_CLK_DIV 2
786#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530787#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
788#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
Prabhakar Kushwaha9f074e62014-10-29 22:33:09 +0530789#define CONFIG_SYS_FSL_ERRATUM_A008044
York Sun5f208d12013-03-25 07:40:06 +0000790#define CONFIG_SYS_FMAN_V3
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530791#define CONFIG_FM_PLAT_CLK_DIV 1
792#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +0800793#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
794 per rcw field value */
795#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530796#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
Priyanka Jainb1359912013-12-17 14:25:52 +0530797#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
Prabhakar Kushwahae03c76c2013-12-11 12:49:13 +0530798#define CONFIG_SYS_FSL_TBCLK_DIV 16
York Sun5f208d12013-03-25 07:40:06 +0000799#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
Nikhil Badolaa4f7cba2014-01-27 15:21:58 +0530800#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
York Sun5f208d12013-03-25 07:40:06 +0000801#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Suresh Gupta9c641a82014-02-26 14:29:12 +0530802#define CONFIG_SYS_FSL_ERRATUM_A006261
York Sun5f208d12013-03-25 07:40:06 +0000803#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Haijun.Zhang1336e2d2014-03-18 17:04:23 +0800804#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
805#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
Zhao Qiang2a44efe2014-03-21 16:21:45 +0800806#define QE_MURAM_SIZE 0x6000UL
807#define MAX_QE_RISC 1
808#define QE_NUM_OF_SNUM 28
York Sun5f208d12013-03-25 07:40:06 +0000809
Shengzhou Liuf6050792014-11-24 17:11:54 +0800810#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
811defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
812#define CONFIG_E5500
813#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
814#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
815#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
816#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
817#define CONFIG_SYS_FMAN_V3
818#ifdef CONFIG_SYS_FSL_DDR4
819#define CONFIG_SYS_FSL_DDRC_GEN4
820#endif
821#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
822#define CONFIG_MAX_CPUS 2
823#elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
824#define CONFIG_MAX_CPUS 1
825#endif
826#define CONFIG_SYS_FSL_NUM_CC_PLL 2
827#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
Shengzhou Liuf6050792014-11-24 17:11:54 +0800828#define CONFIG_SYS_FSL_NUM_LAWS 16
829#define CONFIG_SYS_FSL_SRDS_1
830#define CONFIG_SYS_FSL_SEC_COMPAT 5
831#define CONFIG_SYS_NUM_FMAN 1
832#define CONFIG_SYS_NUM_FM1_DTSEC 4
833#define CONFIG_SYS_NUM_FM1_10GEC 1
Shengzhou Liucc19c252014-11-24 17:11:57 +0800834#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
Shengzhou Liuf6050792014-11-24 17:11:54 +0800835#define CONFIG_NUM_DDR_CONTROLLERS 1
836#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
837#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
838#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
839#define CONFIG_SYS_FM1_CLK 0
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +0800840#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
841 per rcw field value */
Shengzhou Liuf6050792014-11-24 17:11:54 +0800842#define CONFIG_QBMAN_CLK_DIV 1
843#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
844#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
845#define CONFIG_SYS_FSL_TBCLK_DIV 16
846#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
847#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
848#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
849#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
850#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
851#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
852#define QE_MURAM_SIZE 0x6000UL
853#define MAX_QE_RISC 1
854#define QE_NUM_OF_SNUM 28
855#define CONFIG_SYS_FSL_SFP_VER_3_0
856
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800857#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
858#define CONFIG_E6500
859#define CONFIG_SYS_PPC64 /* 64-bit core */
860#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
861#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
862#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
863#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
864#define CONFIG_SYS_FSL_QMAN_V3
865#define CONFIG_MAX_CPUS 4
866#define CONFIG_SYS_FSL_NUM_LAWS 32
867#define CONFIG_SYS_FSL_SEC_COMPAT 4
868#define CONFIG_SYS_NUM_FMAN 1
869#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
870#define CONFIG_SYS_FSL_SRDS_1
871#define CONFIG_SYS_FSL_PCI_VER_3_X
872#if defined(CONFIG_PPC_T2080)
873#define CONFIG_SYS_NUM_FM1_DTSEC 8
874#define CONFIG_SYS_NUM_FM1_10GEC 4
875#define CONFIG_SYS_FSL_SRDS_2
876#define CONFIG_SYS_FSL_SRIO_LIODN
877#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
878#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
879#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
880#elif defined(CONFIG_PPC_T2081)
881#define CONFIG_SYS_NUM_FM1_DTSEC 6
882#define CONFIG_SYS_NUM_FM1_10GEC 2
883#endif
Shengzhou Liu2ffa96d2013-12-18 10:27:55 +0800884#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800885#define CONFIG_NUM_DDR_CONTROLLERS 1
886#define CONFIG_PME_PLAT_CLK_DIV 1
887#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
888#define CONFIG_SYS_FM1_CLK 0
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +0800889#define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
890 per rcw field value */
891#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800892#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
893#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
894#define CONFIG_SYS_FMAN_V3
895#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
896#define CONFIG_SYS_FSL_TBCLK_DIV 16
897#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
898#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
899#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
York Sunc3678b02014-03-28 15:07:27 -0700900#define CONFIG_SYS_FSL_ERRATUM_A007212
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800901#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
902#define CONFIG_SYS_FSL_SFP_VER_3_0
903#define CONFIG_SYS_FSL_ISBC_VER 2
Haijun.Zhang1336e2d2014-03-18 17:04:23 +0800904#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Shengzhou Liuc665c472014-04-24 11:10:09 +0800905#define CONFIG_SYS_FSL_ERRATUM_A006261
906#define CONFIG_SYS_FSL_ERRATUM_A006593
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530907#define CONFIG_SYS_FSL_ERRATUM_A007186
Shengzhou Liuc665c472014-04-24 11:10:09 +0800908#define CONFIG_SYS_FSL_ERRATUM_A006379
Haijun.Zhang1336e2d2014-03-18 17:04:23 +0800909#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530910#define CONFIG_SYS_FSL_SFP_VER_3_0
Haijun.Zhang1336e2d2014-03-18 17:04:23 +0800911
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800912
Mingkai Hu3b75e982013-07-04 17:30:36 +0800913#elif defined(CONFIG_PPC_C29X)
914#define CONFIG_MAX_CPUS 1
915#define CONFIG_FSL_SDHC_V2_3
916#define CONFIG_SYS_FSL_NUM_LAWS 12
917#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
918#define CONFIG_TSECV2_1
919#define CONFIG_SYS_FSL_SEC_COMPAT 6
920#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
921#define CONFIG_NUM_DDR_CONTROLLERS 1
York Sun34e026f2014-03-27 17:54:47 -0700922#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
Mingkai Hu3b75e982013-07-04 17:30:36 +0800923#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
924#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun954a1a42013-08-20 15:09:43 -0700925#define CONFIG_SYS_FSL_ERRATUM_A005125
Mingkai Hu3b75e982013-07-04 17:30:36 +0800926
Alexander Graffa08d392014-04-11 17:09:45 +0200927#elif defined(CONFIG_QEMU_E500)
928#define CONFIG_MAX_CPUS 1
929#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
930
Kumar Gala243be8e2011-01-19 03:05:26 -0600931#else
932#error Processor type not defined for this platform
933#endif
934
Timur Tabie46fedf2011-08-04 18:03:41 -0500935#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
936#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
937#endif
938
York Sunf6981432013-03-25 07:40:07 +0000939#ifdef CONFIG_E6500
940#define CONFIG_SYS_FSL_THREADS_PER_CORE 2
941#else
942#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
943#endif
944
York Sun5614e712013-09-30 09:22:09 -0700945#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
946 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
York Sun34e026f2014-03-27 17:54:47 -0700947 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
948 !defined(CONFIG_SYS_FSL_DDRC_GEN4)
York Sun5614e712013-09-30 09:22:09 -0700949#define CONFIG_SYS_FSL_DDRC_GEN3
950#endif
951
Kumar Gala243be8e2011-01-19 03:05:26 -0600952#endif /* _ASM_MPC85xx_CONFIG_H_ */