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Kumar Gala243be8e2011-01-19 03:05:26 -06001/*
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +00002 * Copyright 2011-2012 Freescale Semiconductor, Inc.
Kumar Gala243be8e2011-01-19 03:05:26 -06003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala243be8e2011-01-19 03:05:26 -06005 */
6
7#ifndef _ASM_MPC85xx_CONFIG_H_
8#define _ASM_MPC85xx_CONFIG_H_
9
10/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
11
Timur Tabie46fedf2011-08-04 18:03:41 -050012#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
13#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
14#endif
15
York Sun2a5fcb82012-10-28 08:12:54 +000016/*
17 * This macro should be removed when we no longer care about backwards
18 * compatibility with older operating systems.
19 */
20#define CONFIG_PPC_SPINTABLE_COMPATIBLE
21
York Sun34e026f2014-03-27 17:54:47 -070022#include <fsl_ddrc_version.h>
23#define CONFIG_SYS_FSL_DDR_BE
York Sun57495e42012-10-08 07:44:22 +000024
Prabhakar Kushwaha1b4175d2014-01-18 12:28:30 +053025/* IP endianness */
26#define CONFIG_SYS_FSL_IFC_BE
Ruchika Gupta028dbb82014-09-09 11:50:31 +053027#define CONFIG_SYS_FSL_SEC_BE
gaurav ranaa2e225e2015-02-27 09:43:49 +053028#define CONFIG_SYS_FSL_SFP_BE
gaurav ranae04916a2015-02-27 09:46:17 +053029#define CONFIG_SYS_FSL_SEC_MON_BE
Prabhakar Kushwaha1b4175d2014-01-18 12:28:30 +053030
Kumar Gala243be8e2011-01-19 03:05:26 -060031/* Number of TLB CAM entries we have on FSL Book-E chips */
32#if defined(CONFIG_E500MC)
33#define CONFIG_SYS_NUM_TLBCAMS 64
34#elif defined(CONFIG_E500)
35#define CONFIG_SYS_NUM_TLBCAMS 16
36#endif
37
York Sun24ad75a2016-11-16 11:06:47 -080038#if defined(CONFIG_ARCH_MPC8536)
Kumar Gala243be8e2011-01-19 03:05:26 -060039#define CONFIG_MAX_CPUS 1
40#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +000041#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
Kumar Gala243be8e2011-01-19 03:05:26 -060042#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -050043#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun9855b3b2014-05-23 13:15:00 -070044#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -070045#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -060046
York Sun7f825212016-11-16 11:13:06 -080047#elif defined(CONFIG_ARCH_MPC8540)
Kumar Gala243be8e2011-01-19 03:05:26 -060048#define CONFIG_MAX_CPUS 1
49#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -070050#define CONFIG_SYS_FSL_DDRC_GEN1
Timur Tabie46fedf2011-08-04 18:03:41 -050051#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -060052
York Sun3aff3082016-11-16 11:18:31 -080053#elif defined(CONFIG_ARCH_MPC8541)
Kumar Gala243be8e2011-01-19 03:05:26 -060054#define CONFIG_MAX_CPUS 1
55#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -070056#define CONFIG_SYS_FSL_DDRC_GEN1
Kumar Gala243be8e2011-01-19 03:05:26 -060057#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -050058#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -060059
York Sun25cb74b2016-11-15 13:57:15 -080060#elif defined(CONFIG_ARCH_MPC8544)
Kumar Gala243be8e2011-01-19 03:05:26 -060061#define CONFIG_MAX_CPUS 1
62#define CONFIG_SYS_FSL_NUM_LAWS 10
York Sun5614e712013-09-30 09:22:09 -070063#define CONFIG_SYS_FSL_DDRC_GEN2
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +000064#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala243be8e2011-01-19 03:05:26 -060065#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -050066#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun954a1a42013-08-20 15:09:43 -070067#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -060068
York Sun281ed4c2016-11-15 13:52:34 -080069#elif defined(CONFIG_ARCH_MPC8548)
Kumar Gala243be8e2011-01-19 03:05:26 -060070#define CONFIG_MAX_CPUS 1
71#define CONFIG_SYS_FSL_NUM_LAWS 10
York Sun5614e712013-09-30 09:22:09 -070072#define CONFIG_SYS_FSL_DDRC_GEN2
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +000073#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala243be8e2011-01-19 03:05:26 -060074#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -050075#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala5ace2992011-09-16 09:54:30 -050076#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
Kumar Gala2b3a1cd2011-10-03 08:37:57 -050077#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
chenhui zhaoaada81d2011-10-03 08:38:50 -050078#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
Liu Gang7d67ed52012-03-08 00:33:14 +000079#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
80#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
81#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
82#define CONFIG_SYS_FSL_RMU
83#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun954a1a42013-08-20 15:09:43 -070084#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan9c3f77e2013-08-16 15:10:37 +080085#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
86#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
Kumar Gala243be8e2011-01-19 03:05:26 -060087
York Sun3c3d8ab2016-11-16 11:23:23 -080088#elif defined(CONFIG_ARCH_MPC8555)
Kumar Gala243be8e2011-01-19 03:05:26 -060089#define CONFIG_MAX_CPUS 1
90#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -070091#define CONFIG_SYS_FSL_DDRC_GEN1
Kumar Gala243be8e2011-01-19 03:05:26 -060092#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -050093#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -060094
York Sun99d0a312016-11-16 11:26:45 -080095#elif defined(CONFIG_ARCH_MPC8560)
Kumar Gala243be8e2011-01-19 03:05:26 -060096#define CONFIG_MAX_CPUS 1
97#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -070098#define CONFIG_SYS_FSL_DDRC_GEN1
Timur Tabie46fedf2011-08-04 18:03:41 -050099#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600100
York Sund07c3842016-11-16 11:32:17 -0800101#elif defined(CONFIG_ARCH_MPC8568)
Kumar Gala243be8e2011-01-19 03:05:26 -0600102#define CONFIG_MAX_CPUS 1
103#define CONFIG_SYS_FSL_NUM_LAWS 10
York Sun5614e712013-09-30 09:22:09 -0700104#define CONFIG_SYS_FSL_DDRC_GEN2
Kumar Gala243be8e2011-01-19 03:05:26 -0600105#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galafdb4dad2011-01-31 23:09:25 -0600106#define QE_MURAM_SIZE 0x10000UL
107#define MAX_QE_RISC 2
108#define QE_NUM_OF_SNUM 28
Timur Tabie46fedf2011-08-04 18:03:41 -0500109#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang7d67ed52012-03-08 00:33:14 +0000110#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
111#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
112#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
113#define CONFIG_SYS_FSL_RMU
114#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600115
York Sun23b36a72016-11-16 11:34:52 -0800116#elif defined(CONFIG_ARCH_MPC8569)
Kumar Gala243be8e2011-01-19 03:05:26 -0600117#define CONFIG_MAX_CPUS 1
118#define CONFIG_SYS_FSL_NUM_LAWS 10
119#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galafdb4dad2011-01-31 23:09:25 -0600120#define QE_MURAM_SIZE 0x20000UL
121#define MAX_QE_RISC 4
122#define QE_NUM_OF_SNUM 46
Timur Tabie46fedf2011-08-04 18:03:41 -0500123#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang7d67ed52012-03-08 00:33:14 +0000124#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
125#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
126#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
127#define CONFIG_SYS_FSL_RMU
128#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun9855b3b2014-05-23 13:15:00 -0700129#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700130#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600131
York Sunc8f48472016-11-16 11:39:20 -0800132#elif defined(CONFIG_ARCH_MPC8572)
Kumar Gala243be8e2011-01-19 03:05:26 -0600133#define CONFIG_MAX_CPUS 2
134#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +0000135#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600136#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500137#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Suneb0aff72011-01-25 21:51:27 -0800138#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sun91671912011-01-25 22:05:49 -0800139#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
York Sun9855b3b2014-05-23 13:15:00 -0700140#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700141#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600142
York Sun7d5f9f82016-11-16 13:08:52 -0800143#elif defined(CONFIG_ARCH_P1010)
Kumar Gala243be8e2011-01-19 03:05:26 -0600144#define CONFIG_MAX_CPUS 1
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530145#define CONFIG_FSL_SDHC_V2_3
Kumar Gala243be8e2011-01-19 03:05:26 -0600146#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000147#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala243be8e2011-01-19 03:05:26 -0600148#define CONFIG_TSECV2
149#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530150#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
151#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530152#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Mingkai Hu362ee042013-05-16 10:18:13 +0800153#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530154#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala8f290842011-05-20 00:39:21 -0500155#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530156#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal42aee642011-06-30 03:00:28 -0500157#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalfb855f42011-06-29 16:32:52 +0530158#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Shengzhou Liu424bf942013-08-15 09:31:47 +0800159#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
Poonam Aggrwalbc6bbd62011-07-07 20:36:47 +0530160#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
York Sun954a1a42013-08-20 15:09:43 -0700161#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800162#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
York Sun9855b3b2014-05-23 13:15:00 -0700163#define CONFIG_SYS_FSL_ERRATUM_A004508
Nikhil Badola11856912014-02-26 17:43:15 +0530164#define CONFIG_SYS_FSL_ERRATUM_A007075
Sriram Dash15a6d492016-08-17 11:47:53 +0530165#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
Suresh Gupta9c641a82014-02-26 14:29:12 +0530166#define CONFIG_SYS_FSL_ERRATUM_A006261
Nikhil Badola0dc78ff2014-11-21 17:25:21 +0530167#define CONFIG_SYS_FSL_ERRATUM_A004477
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800168#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
Haijun.Zhangf28bea02014-01-10 13:52:19 +0800169#define CONFIG_ESDHC_HC_BLK_ADDR
Kumar Gala243be8e2011-01-19 03:05:26 -0600170
Kumar Gala093cffb2011-02-05 13:45:07 -0600171/* P1011 is single core version of P1020 */
York Sun1cdd96f2016-11-16 15:54:15 -0800172#elif defined(CONFIG_ARCH_P1011)
Kumar Gala243be8e2011-01-19 03:05:26 -0600173#define CONFIG_MAX_CPUS 1
174#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000175#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600176#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000177#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600178#define CONFIG_SYS_FSL_SEC_COMPAT 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530179#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500180#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600181#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
182#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun9855b3b2014-05-23 13:15:00 -0700183#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700184#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600185
York Sun484fff62016-11-18 10:02:14 -0800186#elif defined(CONFIG_ARCH_P1020)
Kumar Gala243be8e2011-01-19 03:05:26 -0600187#define CONFIG_MAX_CPUS 2
188#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000189#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600190#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000191#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600192#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500193#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600194#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
195#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun9855b3b2014-05-23 13:15:00 -0700196#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700197#define CONFIG_SYS_FSL_ERRATUM_A005125
ramneek mehresh80ba6a62014-05-13 15:36:07 +0530198#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
ramneek mehreshf1810d82013-10-18 17:40:17 +0530199#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
ramneek mehresh80ba6a62014-05-13 15:36:07 +0530200#endif
Kumar Gala243be8e2011-01-19 03:05:26 -0600201
York Suna9907992016-11-18 10:59:02 -0800202#elif defined(CONFIG_ARCH_P1021)
Kumar Gala243be8e2011-01-19 03:05:26 -0600203#define CONFIG_MAX_CPUS 2
204#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000205#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600206#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000207#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600208#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500209#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600210#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
211#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600212#define QE_MURAM_SIZE 0x6000UL
213#define MAX_QE_RISC 1
214#define QE_NUM_OF_SNUM 28
York Sun9855b3b2014-05-23 13:15:00 -0700215#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700216#define CONFIG_SYS_FSL_ERRATUM_A005125
ramneek mehreshf1810d82013-10-18 17:40:17 +0530217#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Kumar Gala243be8e2011-01-19 03:05:26 -0600218
York Sunfeb9e252016-11-16 15:23:52 -0800219#elif defined(CONFIG_ARCH_P1022)
Kumar Gala243be8e2011-01-19 03:05:26 -0600220#define CONFIG_MAX_CPUS 2
221#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000222#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600223#define CONFIG_TSECV2
224#define CONFIG_SYS_FSL_SEC_COMPAT 2
Ying Zhang703f5682015-01-30 14:52:11 +0800225#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Timur Tabie46fedf2011-08-04 18:03:41 -0500226#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang2d7534a2011-01-30 17:06:20 -0600227#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
228#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
229#define CONFIG_FSL_SATA_ERRATUM_A001
York Sun9855b3b2014-05-23 13:15:00 -0700230#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700231#define CONFIG_SYS_FSL_ERRATUM_A005125
Nikhil Badola0dc78ff2014-11-21 17:25:21 +0530232#define CONFIG_SYS_FSL_ERRATUM_A004477
Kumar Gala243be8e2011-01-19 03:05:26 -0600233
York Sun9bb1d6b2016-11-16 15:45:31 -0800234#elif defined(CONFIG_ARCH_P1023)
Roy Zang67a719d2011-02-03 22:14:19 -0600235#define CONFIG_MAX_CPUS 2
236#define CONFIG_SYS_FSL_NUM_LAWS 12
237#define CONFIG_SYS_FSL_SEC_COMPAT 4
238#define CONFIG_SYS_NUM_FMAN 1
239#define CONFIG_SYS_NUM_FM1_DTSEC 2
240#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530241#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Roy Zang67a719d2011-02-03 22:14:19 -0600242#define CONFIG_SYS_QMAN_NUM_PORTALS 3
243#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galac657d892011-02-04 00:43:34 -0600244#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala8f290842011-05-20 00:39:21 -0500245#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500246#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
York Sun9855b3b2014-05-23 13:15:00 -0700247#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700248#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800249#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
250#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Roy Zang67a719d2011-02-03 22:14:19 -0600251
Kumar Gala093cffb2011-02-05 13:45:07 -0600252/* P1024 is lower end variant of P1020 */
York Sun52b6f132016-11-18 11:00:57 -0800253#elif defined(CONFIG_ARCH_P1024)
Kumar Gala093cffb2011-02-05 13:45:07 -0600254#define CONFIG_MAX_CPUS 2
255#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000256#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala093cffb2011-02-05 13:45:07 -0600257#define CONFIG_TSECV2
258#define CONFIG_FSL_PCIE_DISABLE_ASPM
259#define CONFIG_SYS_FSL_SEC_COMPAT 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530260#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500261#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600262#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
263#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun9855b3b2014-05-23 13:15:00 -0700264#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700265#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala093cffb2011-02-05 13:45:07 -0600266
267/* P1025 is lower end variant of P1021 */
268#elif defined(CONFIG_P1025)
269#define CONFIG_MAX_CPUS 2
270#define CONFIG_SYS_FSL_NUM_LAWS 12
Nikhil Badola1ff10a82015-05-21 09:07:53 +0530271#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000272#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala093cffb2011-02-05 13:45:07 -0600273#define CONFIG_TSECV2
274#define CONFIG_FSL_PCIE_DISABLE_ASPM
275#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500276#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600277#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
278#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600279#define QE_MURAM_SIZE 0x6000UL
280#define MAX_QE_RISC 1
281#define QE_NUM_OF_SNUM 28
York Sun9855b3b2014-05-23 13:15:00 -0700282#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700283#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala093cffb2011-02-05 13:45:07 -0600284
285/* P2010 is single core version of P2020 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600286#elif defined(CONFIG_P2010)
287#define CONFIG_MAX_CPUS 1
288#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000289#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600290#define CONFIG_SYS_FSL_SEC_COMPAT 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530291#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Timur Tabie46fedf2011-08-04 18:03:41 -0500292#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala6e7f0bc02011-01-26 01:43:15 -0600293#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala5103a032011-01-29 15:36:10 -0600294#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
York Sun9855b3b2014-05-23 13:15:00 -0700295#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700296#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600297
298#elif defined(CONFIG_P2020)
299#define CONFIG_MAX_CPUS 2
300#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000301#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600302#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500303#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala6e7f0bc02011-01-26 01:43:15 -0600304#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala5103a032011-01-29 15:36:10 -0600305#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Liu Gang7d67ed52012-03-08 00:33:14 +0000306#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
307#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
308#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
309#define CONFIG_SYS_FSL_RMU
310#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun9855b3b2014-05-23 13:15:00 -0700311#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700312#define CONFIG_SYS_FSL_ERRATUM_A005125
Nikhil Badola0dc78ff2014-11-21 17:25:21 +0530313#define CONFIG_SYS_FSL_ERRATUM_A004477
ramneek mehreshf1810d82013-10-18 17:40:17 +0530314#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
York Sun9855b3b2014-05-23 13:15:00 -0700315
Scott Wood3e978f52012-08-14 10:14:51 +0000316#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
York Sund1001e32012-10-08 07:44:15 +0000317#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700318#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala1f979872011-05-13 01:16:07 -0500319#define CONFIG_MAX_CPUS 4
320#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
321#define CONFIG_SYS_FSL_NUM_LAWS 32
322#define CONFIG_SYS_FSL_SEC_COMPAT 4
323#define CONFIG_SYS_NUM_FMAN 1
324#define CONFIG_SYS_NUM_FM1_DTSEC 5
325#define CONFIG_SYS_NUM_FM1_10GEC 1
326#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530327#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Kumar Gala1f979872011-05-13 01:16:07 -0500328#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
329#define CONFIG_SYS_FSL_TBCLK_DIV 32
330#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500331#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala1f979872011-05-13 01:16:07 -0500332#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
333#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500334#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala1f979872011-05-13 01:16:07 -0500335#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun5e23ab02012-05-07 07:26:47 +0000336#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei99d7b0a2013-03-11 17:56:34 +0000337#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala43f082b2011-11-22 06:51:15 -0600338#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sune22be772013-03-25 07:30:11 +0000339#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun41085082011-11-20 10:01:35 -0800340#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000341#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
342#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
343#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000344#define CONFIG_SYS_FSL_ERRATUM_A004510
345#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
346#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
347#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000348#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi01180332012-10-25 12:40:00 +0000349#define CONFIG_SYS_FSL_ERRATUM_A004849
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800350#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Suresh Gupta9c641a82014-02-26 14:29:12 +0530351#define CONFIG_SYS_FSL_ERRATUM_A006261
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800352#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Kumar Gala1f979872011-05-13 01:16:07 -0500353
Kumar Gala243be8e2011-01-19 03:05:26 -0600354#elif defined(CONFIG_PPC_P3041)
York Sund1001e32012-10-08 07:44:15 +0000355#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700356#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala243be8e2011-01-19 03:05:26 -0600357#define CONFIG_MAX_CPUS 4
Kumar Galab5c87532011-02-16 02:03:29 -0600358#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600359#define CONFIG_SYS_FSL_NUM_LAWS 32
360#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galafbee0f72011-01-25 12:42:32 -0600361#define CONFIG_SYS_NUM_FMAN 1
362#define CONFIG_SYS_NUM_FM1_DTSEC 5
363#define CONFIG_SYS_NUM_FM1_10GEC 1
364#define CONFIG_NUM_DDR_CONTROLLERS 1
York Sun34e026f2014-03-27 17:54:47 -0700365#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
Kumar Galac657d892011-02-04 00:43:34 -0600366#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600367#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala8f290842011-05-20 00:39:21 -0500368#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500369#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang86221f02011-04-13 00:08:51 -0500370#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
371#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500372#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
ramneek mehreshf1810d82013-10-18 17:40:17 +0530373#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Lei Xu30009762011-04-19 15:28:41 +0800374#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun57125f22012-08-08 18:04:53 +0000375#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei99d7b0a2013-03-11 17:56:34 +0000376#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala43f082b2011-11-22 06:51:15 -0600377#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sune22be772013-03-25 07:30:11 +0000378#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun41085082011-11-20 10:01:35 -0800379#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000380#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
381#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
382#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000383#define CONFIG_SYS_FSL_ERRATUM_A004510
384#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
385#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
386#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000387#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi01180332012-10-25 12:40:00 +0000388#define CONFIG_SYS_FSL_ERRATUM_A004849
York Sund217a9a2013-06-25 11:37:49 -0700389#define CONFIG_SYS_FSL_ERRATUM_A005812
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800390#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Suresh Gupta9c641a82014-02-26 14:29:12 +0530391#define CONFIG_SYS_FSL_ERRATUM_A006261
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800392#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala243be8e2011-01-19 03:05:26 -0600393
Scott Wood3e978f52012-08-14 10:14:51 +0000394#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
York Sund1001e32012-10-08 07:44:15 +0000395#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700396#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala243be8e2011-01-19 03:05:26 -0600397#define CONFIG_MAX_CPUS 8
Kumar Galab5c87532011-02-16 02:03:29 -0600398#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Gala243be8e2011-01-19 03:05:26 -0600399#define CONFIG_SYS_FSL_NUM_LAWS 32
400#define CONFIG_SYS_FSL_SEC_COMPAT 4
401#define CONFIG_SYS_NUM_FMAN 2
402#define CONFIG_SYS_NUM_FM1_DTSEC 4
403#define CONFIG_SYS_NUM_FM2_DTSEC 4
404#define CONFIG_SYS_NUM_FM1_10GEC 1
405#define CONFIG_SYS_NUM_FM2_10GEC 1
406#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700407#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530408#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Kumar Galac657d892011-02-04 00:43:34 -0600409#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600410#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala8f290842011-05-20 00:39:21 -0500411#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabie46fedf2011-08-04 18:03:41 -0500412#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala243be8e2011-01-19 03:05:26 -0600413#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
414#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sunfa8d23c2011-01-10 12:03:01 +0000415#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Gala243be8e2011-01-19 03:05:26 -0600416#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
417#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
418#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
Zang Roy-R619114e0be342012-09-18 09:50:08 +0000419#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
Kumar Gala243be8e2011-01-19 03:05:26 -0600420#define CONFIG_SYS_P4080_ERRATUM_CPU22
York Sun5e23ab02012-05-07 07:26:47 +0000421#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala243be8e2011-01-19 03:05:26 -0600422#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medvedf8af0b2010-08-31 22:57:38 -0500423#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabid90fdba2011-04-18 17:16:00 -0500424#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabida30b9f2011-04-01 13:19:36 -0500425#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Gala43f082b2011-11-22 06:51:15 -0600426#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun41085082011-11-20 10:01:35 -0800427#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000428#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
429#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
430#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
431#define CONFIG_SYS_FSL_RMU
432#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Scott Wood33eee332012-08-14 10:14:53 +0000433#define CONFIG_SYS_FSL_ERRATUM_A004510
434#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
435#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
Liu Gangd59c5572012-09-28 21:26:19 +0000436#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi01180332012-10-25 12:40:00 +0000437#define CONFIG_SYS_FSL_ERRATUM_A004849
Timur Tabid607b962012-11-01 08:20:23 +0000438#define CONFIG_SYS_FSL_ERRATUM_A004580
Yuanquan Chenc0a4e6b2012-11-26 23:49:45 +0000439#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
York Sund217a9a2013-06-25 11:37:49 -0700440#define CONFIG_SYS_FSL_ERRATUM_A005812
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800441#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Nikhil Badola11856912014-02-26 17:43:15 +0530442#define CONFIG_SYS_FSL_ERRATUM_A007075
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800443#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala243be8e2011-01-19 03:05:26 -0600444
Scott Wood3e978f52012-08-14 10:14:51 +0000445#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
York Sunffd06e02012-10-08 07:44:30 +0000446#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sund1001e32012-10-08 07:44:15 +0000447#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700448#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala243be8e2011-01-19 03:05:26 -0600449#define CONFIG_MAX_CPUS 2
Kumar Galab5c87532011-02-16 02:03:29 -0600450#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600451#define CONFIG_SYS_FSL_NUM_LAWS 32
452#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galafbee0f72011-01-25 12:42:32 -0600453#define CONFIG_SYS_NUM_FMAN 1
454#define CONFIG_SYS_NUM_FM1_DTSEC 5
455#define CONFIG_SYS_NUM_FM1_10GEC 1
456#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700457#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530458#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Kumar Galac657d892011-02-04 00:43:34 -0600459#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600460#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala8f290842011-05-20 00:39:21 -0500461#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500462#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang86221f02011-04-13 00:08:51 -0500463#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
464#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500465#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu30009762011-04-19 15:28:41 +0800466#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei99d7b0a2013-03-11 17:56:34 +0000467#define CONFIG_SYS_FSL_ERRATUM_USB14
York Sune22be772013-03-25 07:30:11 +0000468#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun41085082011-11-20 10:01:35 -0800469#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000470#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
471#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
472#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000473#define CONFIG_SYS_FSL_ERRATUM_A004510
474#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
475#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000476#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800477#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Suresh Gupta9c641a82014-02-26 14:29:12 +0530478#define CONFIG_SYS_FSL_ERRATUM_A006261
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800479#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala243be8e2011-01-19 03:05:26 -0600480
Timur Tabi49054432012-10-05 11:09:19 +0000481#elif defined(CONFIG_PPC_P5040)
Timur Tabi1956e432012-10-23 10:48:09 +0000482#define CONFIG_SYS_PPC64
Timur Tabi49054432012-10-05 11:09:19 +0000483#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700484#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Timur Tabi49054432012-10-05 11:09:19 +0000485#define CONFIG_MAX_CPUS 4
486#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
487#define CONFIG_SYS_FSL_NUM_LAWS 32
488#define CONFIG_SYS_FSL_SEC_COMPAT 4
489#define CONFIG_SYS_NUM_FMAN 2
490#define CONFIG_SYS_NUM_FM1_DTSEC 5
491#define CONFIG_SYS_NUM_FM1_10GEC 1
492#define CONFIG_SYS_NUM_FM2_DTSEC 5
493#define CONFIG_SYS_NUM_FM2_10GEC 1
494#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700495#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530496#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Timur Tabi49054432012-10-05 11:09:19 +0000497#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
498#define CONFIG_SYS_FSL_TBCLK_DIV 16
499#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
500#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
501#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
502#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
503#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
504#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei99d7b0a2013-03-11 17:56:34 +0000505#define CONFIG_SYS_FSL_ERRATUM_USB14
Timur Tabi49054432012-10-05 11:09:19 +0000506#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
507#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
508#define CONFIG_SYS_FSL_ERRATUM_A004699
Timur Tabi49054432012-10-05 11:09:19 +0000509#define CONFIG_SYS_FSL_ERRATUM_A004510
510#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
Suresh Gupta9c641a82014-02-26 14:29:12 +0530511#define CONFIG_SYS_FSL_ERRATUM_A006261
Timur Tabi49054432012-10-05 11:09:19 +0000512#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
York Sund217a9a2013-06-25 11:37:49 -0700513#define CONFIG_SYS_FSL_ERRATUM_A005812
Timur Tabi49054432012-10-05 11:09:19 +0000514
York Sun115d60c2016-11-15 14:09:50 -0800515#elif defined(CONFIG_ARCH_BSC9131)
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000516#define CONFIG_MAX_CPUS 1
517#define CONFIG_FSL_SDHC_V2_3
518#define CONFIG_SYS_FSL_NUM_LAWS 12
519#define CONFIG_TSECV2
520#define CONFIG_SYS_FSL_SEC_COMPAT 4
521#define CONFIG_NUM_DDR_CONTROLLERS 1
York Sun34e026f2014-03-27 17:54:47 -0700522#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530523#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Priyanka Jain765b0bd2013-04-04 09:31:54 +0530524#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
525#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
Mingkai Hu362ee042013-05-16 10:18:13 +0800526#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000527#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
528#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000529#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun954a1a42013-08-20 15:09:43 -0700530#define CONFIG_SYS_FSL_ERRATUM_A005125
Nikhil Badola0dc78ff2014-11-21 17:25:21 +0530531#define CONFIG_SYS_FSL_ERRATUM_A004477
Haijun.Zhangf28bea02014-01-10 13:52:19 +0800532#define CONFIG_ESDHC_HC_BLK_ADDR
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000533
York Sun115d60c2016-11-15 14:09:50 -0800534#elif defined(CONFIG_ARCH_BSC9132)
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000535#define CONFIG_MAX_CPUS 2
536#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
537#define CONFIG_FSL_SDHC_V2_3
538#define CONFIG_SYS_FSL_NUM_LAWS 12
539#define CONFIG_TSECV2
540#define CONFIG_SYS_FSL_SEC_COMPAT 4
541#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700542#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
ramneek mehreshf1810d82013-10-18 17:40:17 +0530543#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Priyanka Jain64501c62013-07-02 09:21:04 +0530544#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
545#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
546#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
547#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
York Sun061ffed2013-04-18 19:31:01 -0700548#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000549#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
550#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000551#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
552#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
553#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
York Sun954a1a42013-08-20 15:09:43 -0700554#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lanf1a96ec2014-05-07 10:50:20 +0800555#define CONFIG_SYS_FSL_ERRATUM_A005434
Nikhil Badola0dc78ff2014-11-21 17:25:21 +0530556#define CONFIG_SYS_FSL_ERRATUM_A004477
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800557#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
558#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Haijun.Zhangf28bea02014-01-10 13:52:19 +0800559#define CONFIG_ESDHC_HC_BLK_ADDR
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000560
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800561#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
562 defined(CONFIG_PPC_T4080)
York Sun3d2972f2013-03-25 07:40:05 +0000563#define CONFIG_E6500
York Sunffd06e02012-10-08 07:44:30 +0000564#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun9e758752012-10-08 07:44:19 +0000565#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
566#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
York Sunf6981432013-03-25 07:40:07 +0000567#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
York Sun9e758752012-10-08 07:44:19 +0000568#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
York Sun3d2972f2013-03-25 07:40:05 +0000569#ifdef CONFIG_PPC_T4240
York Sun9e758752012-10-08 07:44:19 +0000570#define CONFIG_MAX_CPUS 12
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530571#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
York Sun9e758752012-10-08 07:44:19 +0000572#define CONFIG_SYS_NUM_FM1_DTSEC 8
573#define CONFIG_SYS_NUM_FM1_10GEC 2
574#define CONFIG_SYS_NUM_FM2_DTSEC 8
575#define CONFIG_SYS_NUM_FM2_10GEC 2
576#define CONFIG_NUM_DDR_CONTROLLERS 3
Sriram Dashf413d1c2016-08-17 11:47:54 +0530577#define CONFIG_SYS_FSL_ERRATUM_A006261
York Sun3d2972f2013-03-25 07:40:05 +0000578#else
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800579#define CONFIG_SYS_NUM_FM1_DTSEC 6
York Sun3d2972f2013-03-25 07:40:05 +0000580#define CONFIG_SYS_NUM_FM1_10GEC 1
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800581#define CONFIG_SYS_NUM_FM2_DTSEC 8
York Sun3d2972f2013-03-25 07:40:05 +0000582#define CONFIG_SYS_NUM_FM2_10GEC 1
583#define CONFIG_NUM_DDR_CONTROLLERS 2
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800584#if defined(CONFIG_PPC_T4160)
585#define CONFIG_MAX_CPUS 8
586#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
587#elif defined(CONFIG_PPC_T4080)
588#define CONFIG_MAX_CPUS 4
589#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 }
590#endif
York Sun3d2972f2013-03-25 07:40:05 +0000591#endif
York Sunb6240842013-03-25 07:33:29 +0000592#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
593#define CONFIG_SYS_FSL_NUM_LAWS 32
Prabhakar Kushwahaa4c955b2013-07-31 16:56:41 +0530594#define CONFIG_SYS_FSL_SRDS_1
595#define CONFIG_SYS_FSL_SRDS_2
York Sunb6240842013-03-25 07:33:29 +0000596#define CONFIG_SYS_FSL_SRDS_3
597#define CONFIG_SYS_FSL_SRDS_4
598#define CONFIG_SYS_FSL_SEC_COMPAT 4
599#define CONFIG_SYS_NUM_FMAN 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530600#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530601#define CONFIG_SYS_PME_CLK 0
York Sunb6240842013-03-25 07:33:29 +0000602#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Mingkai Hu362ee042013-05-16 10:18:13 +0800603#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
York Sunb6240842013-03-25 07:33:29 +0000604#define CONFIG_SYS_FMAN_V3
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530605#define CONFIG_SYS_FM1_CLK 3
606#define CONFIG_SYS_FM2_CLK 3
York Sunb6240842013-03-25 07:33:29 +0000607#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
608#define CONFIG_SYS_FSL_TBCLK_DIV 16
609#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
610#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
611#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
612#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Liu Gang08047932013-06-25 18:12:14 +0800613#define CONFIG_SYS_FSL_SRIO_LIODN
York Sunb6240842013-03-25 07:33:29 +0000614#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
615#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
616#define CONFIG_SYS_FSL_ERRATUM_A004468
617#define CONFIG_SYS_FSL_ERRATUM_A_004934
618#define CONFIG_SYS_FSL_ERRATUM_A005871
York Sun133fbfa2013-09-16 12:49:31 -0700619#define CONFIG_SYS_FSL_ERRATUM_A006379
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530620#define CONFIG_SYS_FSL_ERRATUM_A007186
Scott Wood82125192013-05-15 17:50:13 -0500621#define CONFIG_SYS_FSL_ERRATUM_A006593
Nikhil Badolaf3dff692014-10-17 09:12:07 +0530622#define CONFIG_SYS_FSL_ERRATUM_A007798
York Sunb6240842013-03-25 07:33:29 +0000623#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530624#define CONFIG_SYS_FSL_SFP_VER_3_0
York Sunb6240842013-03-25 07:33:29 +0000625#define CONFIG_SYS_FSL_PCI_VER_3_X
626
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000627#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
628#define CONFIG_E6500
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000629#define CONFIG_SYS_PPC64 /* 64-bit core */
630#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
631#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
632#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530633#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
634#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
635#define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000636#define CONFIG_SYS_FSL_NUM_LAWS 32
Prabhakar Kushwahaa4c955b2013-07-31 16:56:41 +0530637#define CONFIG_SYS_FSL_SRDS_1
638#define CONFIG_SYS_FSL_SRDS_2
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530639#define CONFIG_SYS_MAPLE
640#define CONFIG_SYS_CPRI
641#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000642#define CONFIG_SYS_FSL_SEC_COMPAT 4
643#define CONFIG_SYS_NUM_FMAN 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530644#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530645#define CONFIG_SYS_FM1_CLK 0
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530646#define CONFIG_SYS_CPRI_CLK 3
647#define CONFIG_SYS_ULB_CLK 4
648#define CONFIG_SYS_ETVPE_CLK 1
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000649#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Mingkai Hu362ee042013-05-16 10:18:13 +0800650#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000651#define CONFIG_SYS_FMAN_V3
652#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
653#define CONFIG_SYS_FSL_TBCLK_DIV 16
654#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
655#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
656#define CONFIG_SYS_FSL_ERRATUM_A_004934
Shengzhou Liu04feb572013-02-27 21:56:54 +0000657#define CONFIG_SYS_FSL_ERRATUM_A005871
York Sun133fbfa2013-09-16 12:49:31 -0700658#define CONFIG_SYS_FSL_ERRATUM_A006379
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530659#define CONFIG_SYS_FSL_ERRATUM_A007186
Scott Wood82125192013-05-15 17:50:13 -0500660#define CONFIG_SYS_FSL_ERRATUM_A006593
Nikhil Badola11856912014-02-26 17:43:15 +0530661#define CONFIG_SYS_FSL_ERRATUM_A007075
Shaveta Leekha7af9a072014-02-26 16:08:22 +0530662#define CONFIG_SYS_FSL_ERRATUM_A006475
663#define CONFIG_SYS_FSL_ERRATUM_A006384
York Sunc3678b02014-03-28 15:07:27 -0700664#define CONFIG_SYS_FSL_ERRATUM_A007212
Nikhil Badola0dc78ff2014-11-21 17:25:21 +0530665#define CONFIG_SYS_FSL_ERRATUM_A004477
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000666#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530667#define CONFIG_SYS_FSL_SFP_VER_3_0
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000668
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000669#ifdef CONFIG_PPC_B4860
York Sunf6981432013-03-25 07:40:07 +0000670#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
York Sund2404142012-10-08 07:44:20 +0000671#define CONFIG_MAX_CPUS 4
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530672#define CONFIG_MAX_DSP_CPUS 12
673#define CONFIG_NUM_DSP_CPUS 6
Shaveta Leekha6df82e32014-02-26 16:07:37 +0530674#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530675#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
York Sund2404142012-10-08 07:44:20 +0000676#define CONFIG_SYS_NUM_FM1_DTSEC 6
677#define CONFIG_SYS_NUM_FM1_10GEC 2
Poonam Aggrwale394ceb2012-12-23 19:22:33 +0000678#define CONFIG_NUM_DDR_CONTROLLERS 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530679#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
York Sund2404142012-10-08 07:44:20 +0000680#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
681#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
682#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Liu Gang32f38ee2013-06-25 18:12:13 +0800683#define CONFIG_SYS_FSL_SRIO_LIODN
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000684#else
685#define CONFIG_MAX_CPUS 2
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530686#define CONFIG_MAX_DSP_CPUS 2
Shaveta Leekha6df82e32014-02-26 16:07:37 +0530687#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000688#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530689#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000690#define CONFIG_SYS_NUM_FM1_DTSEC 4
691#define CONFIG_SYS_NUM_FM1_10GEC 0
692#define CONFIG_NUM_DDR_CONTROLLERS 1
693#endif
York Sund2404142012-10-08 07:44:20 +0000694
Priyanka Jain2967af62013-10-18 12:30:21 +0530695#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
696defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
York Sun5f208d12013-03-25 07:40:06 +0000697#define CONFIG_E5500
698#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
699#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
York Sunf6981432013-03-25 07:40:07 +0000700#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
York Sun5f208d12013-03-25 07:40:06 +0000701#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
York Sun34e026f2014-03-27 17:54:47 -0700702#ifdef CONFIG_SYS_FSL_DDR4
703#define CONFIG_SYS_FSL_DDRC_GEN4
704#endif
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530705#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
York Sun5f208d12013-03-25 07:40:06 +0000706#define CONFIG_MAX_CPUS 4
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530707#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
708#define CONFIG_MAX_CPUS 2
709#endif
710#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530711#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
York Sun5f208d12013-03-25 07:40:06 +0000712#define CONFIG_SYS_FSL_NUM_LAWS 16
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530713#define CONFIG_SYS_FSL_SRDS_1
714#define CONFIG_SYS_FSL_SEC_COMPAT 5
York Sun5f208d12013-03-25 07:40:06 +0000715#define CONFIG_SYS_NUM_FMAN 1
716#define CONFIG_SYS_NUM_FM1_DTSEC 5
717#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530718#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530719#define CONFIG_PME_PLAT_CLK_DIV 2
720#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530721#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
722#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
Prabhakar Kushwaha9f074e62014-10-29 22:33:09 +0530723#define CONFIG_SYS_FSL_ERRATUM_A008044
York Sun5f208d12013-03-25 07:40:06 +0000724#define CONFIG_SYS_FMAN_V3
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530725#define CONFIG_FM_PLAT_CLK_DIV 1
726#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +0800727#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
728 per rcw field value */
729#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530730#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
Priyanka Jainb1359912013-12-17 14:25:52 +0530731#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
Prabhakar Kushwahae03c76c2013-12-11 12:49:13 +0530732#define CONFIG_SYS_FSL_TBCLK_DIV 16
York Sun5f208d12013-03-25 07:40:06 +0000733#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
Nikhil Badolaa4f7cba2014-01-27 15:21:58 +0530734#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
York Sun5f208d12013-03-25 07:40:06 +0000735#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
736#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Haijun.Zhang1336e2d2014-03-18 17:04:23 +0800737#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
738#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
Zhao Qiang2a44efe2014-03-21 16:21:45 +0800739#define QE_MURAM_SIZE 0x6000UL
740#define MAX_QE_RISC 1
741#define QE_NUM_OF_SNUM 28
gaurav ranae622d9e2015-03-26 15:52:47 +0530742#define CONFIG_SYS_FSL_SFP_VER_3_0
Shengzhou Liua46b1852015-11-20 15:52:04 +0800743#define CONFIG_SYS_FSL_ERRATUM_A008378
Shengzhou Liua994b3d2015-12-16 16:45:41 +0800744#define CONFIG_SYS_FSL_ERRATUM_A009663
York Sun5f208d12013-03-25 07:40:06 +0000745
Shengzhou Liuf6050792014-11-24 17:11:54 +0800746#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
747defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
748#define CONFIG_E5500
749#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
750#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
751#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
752#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
753#define CONFIG_SYS_FMAN_V3
754#ifdef CONFIG_SYS_FSL_DDR4
755#define CONFIG_SYS_FSL_DDRC_GEN4
756#endif
757#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
758#define CONFIG_MAX_CPUS 2
759#elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
760#define CONFIG_MAX_CPUS 1
761#endif
762#define CONFIG_SYS_FSL_NUM_CC_PLL 2
763#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
Shengzhou Liuf6050792014-11-24 17:11:54 +0800764#define CONFIG_SYS_FSL_NUM_LAWS 16
765#define CONFIG_SYS_FSL_SRDS_1
766#define CONFIG_SYS_FSL_SEC_COMPAT 5
767#define CONFIG_SYS_NUM_FMAN 1
768#define CONFIG_SYS_NUM_FM1_DTSEC 4
769#define CONFIG_SYS_NUM_FM1_10GEC 1
Shengzhou Liucc19c252014-11-24 17:11:57 +0800770#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
Shengzhou Liuf6050792014-11-24 17:11:54 +0800771#define CONFIG_NUM_DDR_CONTROLLERS 1
772#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
773#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
774#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
775#define CONFIG_SYS_FM1_CLK 0
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +0800776#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
777 per rcw field value */
Shengzhou Liuf6050792014-11-24 17:11:54 +0800778#define CONFIG_QBMAN_CLK_DIV 1
779#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
780#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
781#define CONFIG_SYS_FSL_TBCLK_DIV 16
782#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
783#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
784#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
785#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
786#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
787#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
788#define QE_MURAM_SIZE 0x6000UL
789#define MAX_QE_RISC 1
790#define QE_NUM_OF_SNUM 28
791#define CONFIG_SYS_FSL_SFP_VER_3_0
Shengzhou Liua46b1852015-11-20 15:52:04 +0800792#define CONFIG_SYS_FSL_ERRATUM_A008378
Shengzhou Liua994b3d2015-12-16 16:45:41 +0800793#define CONFIG_SYS_FSL_ERRATUM_A009663
Shengzhou Liuf6050792014-11-24 17:11:54 +0800794
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800795#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
796#define CONFIG_E6500
797#define CONFIG_SYS_PPC64 /* 64-bit core */
798#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
799#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
800#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
801#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
802#define CONFIG_SYS_FSL_QMAN_V3
803#define CONFIG_MAX_CPUS 4
804#define CONFIG_SYS_FSL_NUM_LAWS 32
805#define CONFIG_SYS_FSL_SEC_COMPAT 4
806#define CONFIG_SYS_NUM_FMAN 1
807#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
808#define CONFIG_SYS_FSL_SRDS_1
809#define CONFIG_SYS_FSL_PCI_VER_3_X
810#if defined(CONFIG_PPC_T2080)
811#define CONFIG_SYS_NUM_FM1_DTSEC 8
812#define CONFIG_SYS_NUM_FM1_10GEC 4
813#define CONFIG_SYS_FSL_SRDS_2
814#define CONFIG_SYS_FSL_SRIO_LIODN
815#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
816#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
817#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
818#elif defined(CONFIG_PPC_T2081)
819#define CONFIG_SYS_NUM_FM1_DTSEC 6
820#define CONFIG_SYS_NUM_FM1_10GEC 2
821#endif
Shengzhou Liu2ffa96d2013-12-18 10:27:55 +0800822#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800823#define CONFIG_NUM_DDR_CONTROLLERS 1
824#define CONFIG_PME_PLAT_CLK_DIV 1
825#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
826#define CONFIG_SYS_FM1_CLK 0
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +0800827#define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
828 per rcw field value */
829#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800830#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
831#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
832#define CONFIG_SYS_FMAN_V3
833#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
834#define CONFIG_SYS_FSL_TBCLK_DIV 16
835#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
836#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
837#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
York Sunc3678b02014-03-28 15:07:27 -0700838#define CONFIG_SYS_FSL_ERRATUM_A007212
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800839#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
840#define CONFIG_SYS_FSL_SFP_VER_3_0
841#define CONFIG_SYS_FSL_ISBC_VER 2
Haijun.Zhang1336e2d2014-03-18 17:04:23 +0800842#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Shengzhou Liuc665c472014-04-24 11:10:09 +0800843#define CONFIG_SYS_FSL_ERRATUM_A006593
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530844#define CONFIG_SYS_FSL_ERRATUM_A007186
Shengzhou Liuc665c472014-04-24 11:10:09 +0800845#define CONFIG_SYS_FSL_ERRATUM_A006379
Haijun.Zhang1336e2d2014-03-18 17:04:23 +0800846#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530847#define CONFIG_SYS_FSL_SFP_VER_3_0
Haijun.Zhang1336e2d2014-03-18 17:04:23 +0800848
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800849
York Sun4fd64742016-11-15 18:44:22 -0800850#elif defined(CONFIG_ARCH_C29X)
Mingkai Hu3b75e982013-07-04 17:30:36 +0800851#define CONFIG_MAX_CPUS 1
852#define CONFIG_FSL_SDHC_V2_3
853#define CONFIG_SYS_FSL_NUM_LAWS 12
854#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
855#define CONFIG_TSECV2_1
856#define CONFIG_SYS_FSL_SEC_COMPAT 6
857#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
858#define CONFIG_NUM_DDR_CONTROLLERS 1
York Sun34e026f2014-03-27 17:54:47 -0700859#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
Mingkai Hu3b75e982013-07-04 17:30:36 +0800860#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
861#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun954a1a42013-08-20 15:09:43 -0700862#define CONFIG_SYS_FSL_ERRATUM_A005125
Alex Porosanu404bf452016-04-29 15:17:59 +0300863#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
864#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
Mingkai Hu3b75e982013-07-04 17:30:36 +0800865
Alexander Graffa08d392014-04-11 17:09:45 +0200866#elif defined(CONFIG_QEMU_E500)
867#define CONFIG_MAX_CPUS 1
868#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
869
Kumar Gala243be8e2011-01-19 03:05:26 -0600870#else
871#error Processor type not defined for this platform
872#endif
873
Timur Tabie46fedf2011-08-04 18:03:41 -0500874#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
875#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
876#endif
877
York Sunf6981432013-03-25 07:40:07 +0000878#ifdef CONFIG_E6500
879#define CONFIG_SYS_FSL_THREADS_PER_CORE 2
880#else
881#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
882#endif
883
York Sun5614e712013-09-30 09:22:09 -0700884#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
885 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
York Sun34e026f2014-03-27 17:54:47 -0700886 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
887 !defined(CONFIG_SYS_FSL_DDRC_GEN4)
York Sun5614e712013-09-30 09:22:09 -0700888#define CONFIG_SYS_FSL_DDRC_GEN3
889#endif
890
York Sun4fd64742016-11-15 18:44:22 -0800891#if !defined(CONFIG_ARCH_C29X)
Alex Porosanu404bf452016-04-29 15:17:59 +0300892#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
893#endif
894
Kumar Gala243be8e2011-01-19 03:05:26 -0600895#endif /* _ASM_MPC85xx_CONFIG_H_ */