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wdenk42d1f032003-10-15 23:53:47 +00001/*
Kumar Galaa09b9b62010-12-30 12:09:53 -06002 * Copyright 2007-2011 Freescale Semiconductor, Inc.
Ed Swarthout29372ff2007-07-27 01:50:47 -05003 *
wdenk42d1f032003-10-15 23:53:47 +00004 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +000011 */
12
13#include <common.h>
14#include <watchdog.h>
15#include <asm/processor.h>
16#include <ioports.h>
Kumar Galaf54fe872010-04-20 10:21:25 -050017#include <sata.h>
Kumar Galac916d7c2011-04-13 08:37:44 -050018#include <fm_eth.h>
wdenk42d1f032003-10-15 23:53:47 +000019#include <asm/io.h>
Kumar Galafd3c9be2010-05-05 22:35:27 -050020#include <asm/cache.h>
Kumar Gala87163182008-01-16 22:38:34 -060021#include <asm/mmu.h>
York Sun133fbfa2013-09-16 12:49:31 -070022#include <asm/fsl_errata.h>
Kumar Gala83d40df2008-01-16 01:13:58 -060023#include <asm/fsl_law.h>
Kumar Galaf54fe872010-04-20 10:21:25 -050024#include <asm/fsl_serdes.h>
Liu Gang5ffa88e2012-03-08 00:33:17 +000025#include <asm/fsl_srio.h>
ramneek mehresh9dee2052013-08-05 16:00:16 +053026#include <fsl_usb.h>
York Sun57125f22012-08-08 18:04:53 +000027#include <hwconfig.h>
Timur Tabifbc20aa2011-11-21 17:10:23 -060028#include <linux/compiler.h>
Kumar Galaec2b74f2008-01-17 16:48:33 -060029#include "mp.h"
Timur Tabif2717b42011-11-22 09:21:25 -060030#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
Haiying Wanga7b1e1b2011-02-07 16:14:15 -050031#include <nand.h>
32#include <errno.h>
33#endif
wdenk42d1f032003-10-15 23:53:47 +000034
Timur Tabifbc20aa2011-11-21 17:10:23 -060035#include "../../../../drivers/block/fsl_sata.h"
Zhao Qiang2a44efe2014-03-21 16:21:45 +080036#ifdef CONFIG_U_QE
37#include "../../../../drivers/qe/qe.h"
38#endif
Timur Tabifbc20aa2011-11-21 17:10:23 -060039
Wolfgang Denkd87080b2006-03-31 18:32:53 +020040DECLARE_GLOBAL_DATA_PTR;
41
Nikhil Badolad1c561c2014-04-15 14:44:52 +053042#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
43/*
44 * For deriving usb clock from 100MHz sysclk, reference divisor is set
45 * to a value of 5, which gives an intermediate value 20(100/5). The
46 * multiplication factor integer is set to 24, which when multiplied to
47 * above intermediate value provides clock for usb ip.
48 */
49void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
50{
51 sys_info_t sysinfo;
52
53 get_sys_info(&sysinfo);
54 if (sysinfo.diff_sysclk == 1) {
55 clrbits_be32(&usb_phy->pllprg[1],
56 CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
57 setbits_be32(&usb_phy->pllprg[1],
58 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
59 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
60 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
61 }
62}
63#endif
64
Suresh Gupta9c641a82014-02-26 14:29:12 +053065#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
66void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
67{
68#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
69 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
70
71 /* Increase Disconnect Threshold by 50mV */
72 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
73 INC_DCNT_THRESHOLD_50MV;
74 /* Enable programming of USB High speed Disconnect threshold */
75 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
76 out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
77
78 xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
79 /* Increase Disconnect Threshold by 50mV */
80 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
81 INC_DCNT_THRESHOLD_50MV;
82 /* Enable programming of USB High speed Disconnect threshold */
83 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
84 out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
85#else
86
87 u32 temp = 0;
88 u32 status = in_be32(&usb_phy->status1);
89
90 u32 squelch_prog_rd_0_2 =
91 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
92 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
93
94 u32 squelch_prog_rd_3_5 =
95 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
96 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
97
98 setbits_be32(&usb_phy->config1,
99 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
100 setbits_be32(&usb_phy->config2,
101 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
102
103 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
104 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
105
106 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
107 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
108#endif
109}
110#endif
111
112
Zhao Qiang2a44efe2014-03-21 16:21:45 +0800113#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
Andy Flemingda9d4612007-08-14 00:14:25 -0500114extern qe_iop_conf_t qe_iop_conf_tab[];
115extern void qe_config_iopin(u8 port, u8 pin, int dir,
116 int open_drain, int assign);
117extern void qe_init(uint qe_base);
118extern void qe_reset(void);
119
120static void config_qe_ioports(void)
121{
122 u8 port, pin;
123 int dir, open_drain, assign;
124 int i;
125
126 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
127 port = qe_iop_conf_tab[i].port;
128 pin = qe_iop_conf_tab[i].pin;
129 dir = qe_iop_conf_tab[i].dir;
130 open_drain = qe_iop_conf_tab[i].open_drain;
131 assign = qe_iop_conf_tab[i].assign;
132 qe_config_iopin(port, pin, dir, open_drain, assign);
133 }
134}
135#endif
Matthew McClintock40d5fa32006-06-28 10:43:36 -0500136
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500137#ifdef CONFIG_CPM2
Kumar Galaaafeefb2007-11-28 00:36:33 -0600138void config_8560_ioports (volatile ccsr_cpm_t * cpm)
wdenk42d1f032003-10-15 23:53:47 +0000139{
140 int portnum;
141
142 for (portnum = 0; portnum < 4; portnum++) {
143 uint pmsk = 0,
144 ppar = 0,
145 psor = 0,
146 pdir = 0,
147 podr = 0,
148 pdat = 0;
149 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
150 iop_conf_t *eiopc = iopc + 32;
151 uint msk = 1;
152
153 /*
154 * NOTE:
155 * index 0 refers to pin 31,
156 * index 31 refers to pin 0
157 */
158 while (iopc < eiopc) {
159 if (iopc->conf) {
160 pmsk |= msk;
161 if (iopc->ppar)
162 ppar |= msk;
163 if (iopc->psor)
164 psor |= msk;
165 if (iopc->pdir)
166 pdir |= msk;
167 if (iopc->podr)
168 podr |= msk;
169 if (iopc->pdat)
170 pdat |= msk;
171 }
172
173 msk <<= 1;
174 iopc++;
175 }
176
177 if (pmsk != 0) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600178 volatile ioport_t *iop = ioport_addr (cpm, portnum);
wdenk42d1f032003-10-15 23:53:47 +0000179 uint tpmsk = ~pmsk;
180
181 /*
182 * the (somewhat confused) paragraph at the
183 * bottom of page 35-5 warns that there might
184 * be "unknown behaviour" when programming
185 * PSORx and PDIRx, if PPARx = 1, so I
186 * decided this meant I had to disable the
187 * dedicated function first, and enable it
188 * last.
189 */
190 iop->ppar &= tpmsk;
191 iop->psor = (iop->psor & tpmsk) | psor;
192 iop->podr = (iop->podr & tpmsk) | podr;
193 iop->pdat = (iop->pdat & tpmsk) | pdat;
194 iop->pdir = (iop->pdir & tpmsk) | pdir;
195 iop->ppar |= ppar;
196 }
197 }
198}
199#endif
200
Kumar Gala6aba33e2009-03-19 03:40:08 -0500201#ifdef CONFIG_SYS_FSL_CPC
Aneesh Bansalfb4a2402014-03-18 23:40:26 +0530202#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
203static void disable_cpc_sram(void)
Kumar Gala6aba33e2009-03-19 03:40:08 -0500204{
205 int i;
Kumar Gala6aba33e2009-03-19 03:40:08 -0500206
207 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
208
209 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
Shaohui Xie2a9fab82011-03-16 10:10:32 +0800210 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
211 /* find and disable LAW of SRAM */
212 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
213
214 if (law.index == -1) {
215 printf("\nFatal error happened\n");
216 return;
217 }
218 disable_law(law.index);
219
220 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
221 out_be32(&cpc->cpccsr0, 0);
222 out_be32(&cpc->cpcsrcr0, 0);
223 }
Aneesh Bansalfb4a2402014-03-18 23:40:26 +0530224 }
225}
Shaohui Xie2a9fab82011-03-16 10:10:32 +0800226#endif
Kumar Gala6aba33e2009-03-19 03:40:08 -0500227
Sandeep Singh377ffcf2014-06-05 18:49:57 +0530228#if defined(T1040_TDM_QUIRK_CCSR_BASE)
229#ifdef CONFIG_POST
230#error POST memory test cannot be enabled with TDM
231#endif
232static void enable_tdm_law(void)
233{
234 int ret;
235 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
236 int tdm_hwconfig_enabled = 0;
237
238 /*
239 * Extract hwconfig from environment since environment
240 * is not setup properly yet. Search for tdm entry in
241 * hwconfig.
242 */
243 ret = getenv_f("hwconfig", buffer, sizeof(buffer));
244 if (ret > 0) {
245 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
246 /* If tdm is defined in hwconfig, set law for tdm workaround */
247 if (tdm_hwconfig_enabled)
248 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
249 LAW_TRGT_IF_CCSR);
250 }
251}
252#endif
253
Aneesh Bansalfb4a2402014-03-18 23:40:26 +0530254static void enable_cpc(void)
255{
256 int i;
257 u32 size = 0;
258
259 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
260
261 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
262 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
263 size += CPC_CFG0_SZ_K(cpccfg0);
264
Kumar Gala1d2c2a62011-01-13 01:54:01 -0600265#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
266 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
267#endif
Kumar Gala868da592011-01-13 01:56:18 -0600268#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
269 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
270#endif
Scott Wood82125192013-05-15 17:50:13 -0500271#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
272 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
273#endif
York Sun133fbfa2013-09-16 12:49:31 -0700274#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
275 if (has_erratum_a006379()) {
276 setbits_be32(&cpc->cpchdbcr0,
277 CPC_HDBCR0_SPLRU_LEVEL_EN);
278 }
279#endif
Kumar Gala1d2c2a62011-01-13 01:54:01 -0600280
Kumar Gala6aba33e2009-03-19 03:40:08 -0500281 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
282 /* Read back to sync write */
283 in_be32(&cpc->cpccsr0);
284
285 }
286
Shruti Kanetkar2f848f92013-08-15 11:25:37 -0500287 puts("Corenet Platform Cache: ");
288 print_size(size * 1024, " enabled\n");
Kumar Gala6aba33e2009-03-19 03:40:08 -0500289}
290
Kim Phillipse56143e2012-10-29 13:34:38 +0000291static void invalidate_cpc(void)
Kumar Gala6aba33e2009-03-19 03:40:08 -0500292{
293 int i;
294 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
295
296 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
Shaohui Xie2a9fab82011-03-16 10:10:32 +0800297 /* skip CPC when it used as all SRAM */
298 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
299 continue;
Kumar Gala6aba33e2009-03-19 03:40:08 -0500300 /* Flash invalidate the CPC and clear all the locks */
301 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
302 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
303 ;
304 }
305}
306#else
307#define enable_cpc()
308#define invalidate_cpc()
309#endif /* CONFIG_SYS_FSL_CPC */
310
wdenk42d1f032003-10-15 23:53:47 +0000311/*
312 * Breathe some life into the CPU...
313 *
314 * Set up the memory map
315 * initialize a bunch of registers
316 */
317
Kumar Gala3c2a67e2009-09-17 01:52:37 -0500318#ifdef CONFIG_FSL_CORENET
319static void corenet_tb_init(void)
320{
321 volatile ccsr_rcpm_t *rcpm =
322 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
323 volatile ccsr_pic_t *pic =
Kim Phillips680c6132010-08-09 18:39:57 -0500324 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
Kumar Gala3c2a67e2009-09-17 01:52:37 -0500325 u32 whoami = in_be32(&pic->whoami);
326
327 /* Enable the timebase register for this core */
328 out_be32(&rcpm->ctbenrl, (1 << whoami));
329}
330#endif
331
York Sunc3678b02014-03-28 15:07:27 -0700332#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
333void fsl_erratum_a007212_workaround(void)
334{
335 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
336 u32 ddr_pll_ratio;
337 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
338 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
339 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
340#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
341 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
342 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
343#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
344 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
345 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
346#endif
347#endif
348 /*
349 * Even this workaround applies to selected version of SoCs, it is
350 * safe to apply to all versions, with the limitation of odd ratios.
351 * If RCW has disabled DDR PLL, we have to apply this workaround,
352 * otherwise DDR will not work.
353 */
354 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
355 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
356 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
357 /* check if RCW sets ratio to 0, required by this workaround */
358 if (ddr_pll_ratio != 0)
359 return;
360 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
361 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
362 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
363 /* check if reserved bits have the desired ratio */
364 if (ddr_pll_ratio == 0) {
365 printf("Error: Unknown DDR PLL ratio!\n");
366 return;
367 }
368 ddr_pll_ratio >>= 1;
369
370 setbits_be32(plldadcr1, 0x02000001);
371#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
372 setbits_be32(plldadcr2, 0x02000001);
373#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
374 setbits_be32(plldadcr3, 0x02000001);
375#endif
376#endif
377 setbits_be32(dpdovrcr4, 0xe0000000);
378 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
379#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
380 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
381#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
382 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
383#endif
384#endif
385 udelay(100);
386 clrbits_be32(plldadcr1, 0x02000001);
387#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
388 clrbits_be32(plldadcr2, 0x02000001);
389#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
390 clrbits_be32(plldadcr3, 0x02000001);
391#endif
392#endif
393 clrbits_be32(dpdovrcr4, 0xe0000000);
394}
395#endif
396
York Sun701e6402014-04-30 14:43:47 -0700397ulong cpu_init_f(void)
wdenk42d1f032003-10-15 23:53:47 +0000398{
York Sun701e6402014-04-30 14:43:47 -0700399 ulong flag = 0;
wdenk42d1f032003-10-15 23:53:47 +0000400 extern void m8560_cpm_reset (void);
Stephen Georgef110fe92011-07-20 09:47:26 -0500401#ifdef CONFIG_SYS_DCSRBAR_PHYS
402 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
403#endif
Ruchika Gupta7065b7d2010-12-15 17:02:08 +0000404#if defined(CONFIG_SECURE_BOOT)
405 struct law_entry law;
406#endif
Peter Tysera2cd50e2008-11-11 10:17:10 -0600407#ifdef CONFIG_MPC8548
408 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
409 uint svr = get_svr();
410
411 /*
412 * CPU2 errata workaround: A core hang possible while executing
413 * a msync instruction and a snoopable transaction from an I/O
414 * master tagged to make quick forward progress is present.
415 * Fixed in silicon rev 2.1.
416 */
417 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
418 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
419#endif
wdenk42d1f032003-10-15 23:53:47 +0000420
Kumar Gala87163182008-01-16 22:38:34 -0600421 disable_tlb(14);
422 disable_tlb(15);
423
Ruchika Gupta7065b7d2010-12-15 17:02:08 +0000424#if defined(CONFIG_SECURE_BOOT)
425 /* Disable the LAW created for NOR flash by the PBI commands */
426 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
427 if (law.index != -1)
428 disable_law(law.index);
Aneesh Bansalfb4a2402014-03-18 23:40:26 +0530429
430#if defined(CONFIG_SYS_CPC_REINIT_F)
431 disable_cpc_sram();
432#endif
Ruchika Gupta7065b7d2010-12-15 17:02:08 +0000433#endif
434
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500435#ifdef CONFIG_CPM2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
wdenk42d1f032003-10-15 23:53:47 +0000437#endif
438
Becky Brucef51cdaf2010-06-17 11:37:20 -0500439 init_early_memctl_regs();
wdenk42d1f032003-10-15 23:53:47 +0000440
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500441#if defined(CONFIG_CPM2)
wdenk42d1f032003-10-15 23:53:47 +0000442 m8560_cpm_reset();
443#endif
Zhao Qiang2a44efe2014-03-21 16:21:45 +0800444
445#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
Andy Flemingda9d4612007-08-14 00:14:25 -0500446 /* Config QE ioports */
447 config_qe_ioports();
448#endif
Zhao Qiang2a44efe2014-03-21 16:21:45 +0800449
Peter Tyser79f43332009-06-30 17:15:47 -0500450#if defined(CONFIG_FSL_DMA)
451 dma_init();
452#endif
Kumar Gala3c2a67e2009-09-17 01:52:37 -0500453#ifdef CONFIG_FSL_CORENET
454 corenet_tb_init();
455#endif
Kumar Gala94e94112009-11-12 10:26:16 -0600456 init_used_tlb_cams();
Kumar Gala6aba33e2009-03-19 03:40:08 -0500457
458 /* Invalidate the CPC before DDR gets enabled */
459 invalidate_cpc();
Stephen Georgef110fe92011-07-20 09:47:26 -0500460
461 #ifdef CONFIG_SYS_DCSRBAR_PHYS
462 /* set DCSRCR so that DCSR space is 1G */
463 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
464 in_be32(&gur->dcsrcr);
465#endif
466
Tang Yuantianaade2002014-04-17 15:33:46 +0800467#ifdef CONFIG_SYS_DCSRBAR_PHYS
468#ifdef CONFIG_DEEP_SLEEP
469 /* disable the console if boot from deep sleep */
470 if (in_be32(&gur->scrtsr[0]) & (1 << 3))
York Sun701e6402014-04-30 14:43:47 -0700471 flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
Tang Yuantianaade2002014-04-17 15:33:46 +0800472#endif
473#endif
York Sunc3678b02014-03-28 15:07:27 -0700474#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
475 fsl_erratum_a007212_workaround();
476#endif
477
York Sun701e6402014-04-30 14:43:47 -0700478 return flag;
wdenk42d1f032003-10-15 23:53:47 +0000479}
480
Kumar Gala35079aa2010-12-15 03:50:47 -0600481/* Implement a dummy function for those platforms w/o SERDES */
482static void __fsl_serdes__init(void)
483{
484 return ;
485}
486__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500487
Prabhakar Kushwahae9827462013-08-29 13:10:38 +0530488#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
York Sun6d2b9da2012-10-08 07:44:08 +0000489int enable_cluster_l2(void)
490{
491 int i = 0;
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800492 u32 cluster, svr = get_svr();
York Sun6d2b9da2012-10-08 07:44:08 +0000493 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
494 struct ccsr_cluster_l2 __iomem *l2cache;
495
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800496 /* only the L2 of first cluster should be enabled as expected on T4080,
497 * but there is no EOC in the first cluster as HW sake, so return here
498 * to skip enabling L2 cache of the 2nd cluster.
499 */
500 if (SVR_SOC_VER(svr) == SVR_T4080)
501 return 0;
502
York Sun6d2b9da2012-10-08 07:44:08 +0000503 cluster = in_be32(&gur->tp_cluster[i].lower);
504 if (cluster & TP_CLUSTER_EOC)
505 return 0;
506
507 /* The first cache has already been set up, so skip it */
508 i++;
509
510 /* Look through the remaining clusters, and set up their caches */
511 do {
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000512 int j, cluster_valid = 0;
513
York Sun6d2b9da2012-10-08 07:44:08 +0000514 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000515
York Sun6d2b9da2012-10-08 07:44:08 +0000516 cluster = in_be32(&gur->tp_cluster[i].lower);
517
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000518 /* check that at least one core/accel is enabled in cluster */
519 for (j = 0; j < 4; j++) {
520 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
521 u32 type = in_be32(&gur->tp_ityp[idx]);
York Sun6d2b9da2012-10-08 07:44:08 +0000522
Shaveta Leekhaa1399a92014-07-02 11:44:54 +0530523 if ((type & TP_ITYP_AV) &&
524 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000525 cluster_valid = 1;
526 }
York Sun6d2b9da2012-10-08 07:44:08 +0000527
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000528 if (cluster_valid) {
529 /* set stash ID to (cluster) * 2 + 32 + 1 */
530 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
531
532 printf("enable l2 for cluster %d %p\n", i, l2cache);
533
534 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
535 while ((in_be32(&l2cache->l2csr0)
536 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
537 ;
James Yang9cd95ac2013-03-25 07:40:03 +0000538 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000539 }
York Sun6d2b9da2012-10-08 07:44:08 +0000540 i++;
541 } while (!(cluster & TP_CLUSTER_EOC));
542
543 return 0;
544}
545#endif
546
wdenk42d1f032003-10-15 23:53:47 +0000547/*
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500548 * Initialize L2 as cache.
549 *
550 * The newer 8548, etc, parts have twice as much cache, but
551 * use the same bit-encoding as the older 8555, etc, parts.
552 *
wdenk42d1f032003-10-15 23:53:47 +0000553 */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500554int cpu_init_r(void)
wdenk42d1f032003-10-15 23:53:47 +0000555{
Timur Tabifbc20aa2011-11-21 17:10:23 -0600556 __maybe_unused u32 svr = get_svr();
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500557#ifdef CONFIG_SYS_LBC_LCRR
York Sun6d2b9da2012-10-08 07:44:08 +0000558 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
559#endif
560#ifdef CONFIG_L2_CACHE
561 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
Prabhakar Kushwahae9827462013-08-29 13:10:38 +0530562#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
York Sun6d2b9da2012-10-08 07:44:08 +0000563 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500564#endif
York Sunafbfdf52012-11-08 12:33:39 +0000565#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
York Sun2a5fcb82012-10-28 08:12:54 +0000566 extern int spin_table_compat;
567 const char *spin;
568#endif
Shengzhou Liu424bf942013-08-15 09:31:47 +0800569#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
570 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
571#endif
York Sun5e23ab02012-05-07 07:26:47 +0000572#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
573 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
574 /*
York Sun57125f22012-08-08 18:04:53 +0000575 * CPU22 and NMG_CPU_A011 share the same workaround.
York Sun5e23ab02012-05-07 07:26:47 +0000576 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
577 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
York Sun57125f22012-08-08 18:04:53 +0000578 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
579 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
580 * be disabled by hwconfig with syntax:
581 *
582 * fsl_cpu_a011:disable
York Sun5e23ab02012-05-07 07:26:47 +0000583 */
York Sun57125f22012-08-08 18:04:53 +0000584 extern int enable_cpu_a011_workaround;
585#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
586 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
587#else
588 char buffer[HWCONFIG_BUFFER_SIZE];
589 char *buf = NULL;
590 int n, res;
591
592 n = getenv_f("hwconfig", buffer, sizeof(buffer));
593 if (n > 0)
594 buf = buffer;
595
596 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
597 if (res > 0)
598 enable_cpu_a011_workaround = 0;
599 else {
600 if (n >= HWCONFIG_BUFFER_SIZE) {
601 printf("fsl_cpu_a011 was not found. hwconfig variable "
602 "may be too long\n");
603 }
604 enable_cpu_a011_workaround =
605 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
606 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
607 }
608#endif
609 if (enable_cpu_a011_workaround) {
York Sun1e9ea852012-05-07 07:26:45 +0000610 flush_dcache();
611 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
612 sync();
613 }
Kumar Galafd3c9be2010-05-05 22:35:27 -0500614#endif
York Sund217a9a2013-06-25 11:37:49 -0700615#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
616 /*
617 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
618 * in write shadow mode. Checking DCWS before setting SPR 976.
619 */
620 if (mfspr(L1CSR2) & L1CSR2_DCWS)
621 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
622#endif
Kumar Galafd3c9be2010-05-05 22:35:27 -0500623
York Sunafbfdf52012-11-08 12:33:39 +0000624#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
York Sun2a5fcb82012-10-28 08:12:54 +0000625 spin = getenv("spin_table_compat");
626 if (spin && (*spin == 'n'))
627 spin_table_compat = 0;
628 else
629 spin_table_compat = 1;
630#endif
631
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200632 puts ("L2: ");
633
wdenk42d1f032003-10-15 23:53:47 +0000634#if defined(CONFIG_L2_CACHE)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500635 volatile uint cache_ctl;
Timur Tabifbc20aa2011-11-21 17:10:23 -0600636 uint ver;
Kumar Gala73f15a02008-07-14 14:07:00 -0500637 u32 l2siz_field;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500638
Kumar Galaf3e04bd2008-04-08 10:45:50 -0500639 ver = SVR_SOC_VER(svr);
wdenk42d1f032003-10-15 23:53:47 +0000640
641 asm("msync;isync");
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500642 cache_ctl = l2cache->l2ctl;
Mingkai Hu7da53352009-09-11 14:19:10 +0800643
644#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
645 if (cache_ctl & MPC85xx_L2CTL_L2E) {
646 /* Clear L2 SRAM memory-mapped base address */
647 out_be32(&l2cache->l2srbar0, 0x0);
648 out_be32(&l2cache->l2srbar1, 0x0);
649
650 /* set MBECCDIS=0, SBECCDIS=0 */
651 clrbits_be32(&l2cache->l2errdis,
652 (MPC85xx_L2ERRDIS_MBECC |
653 MPC85xx_L2ERRDIS_SBECC));
654
655 /* set L2E=0, L2SRAM=0 */
656 clrbits_be32(&l2cache->l2ctl,
657 (MPC85xx_L2CTL_L2E |
658 MPC85xx_L2CTL_L2SRAM_ENTIRE));
659 }
660#endif
661
Kumar Gala73f15a02008-07-14 14:07:00 -0500662 l2siz_field = (cache_ctl >> 28) & 0x3;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500663
Kumar Gala73f15a02008-07-14 14:07:00 -0500664 switch (l2siz_field) {
665 case 0x0:
666 printf(" unknown size (0x%08x)\n", cache_ctl);
667 return -1;
668 break;
669 case 0x1:
670 if (ver == SVR_8540 || ver == SVR_8560 ||
York Sun48f6a5c2012-07-06 17:10:33 -0500671 ver == SVR_8541 || ver == SVR_8555) {
Shruti Kanetkar6b44d9e2013-08-15 11:25:38 -0500672 puts("128 KiB ");
673 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
Kumar Gala73f15a02008-07-14 14:07:00 -0500674 cache_ctl = 0xc4000000;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500675 } else {
Shruti Kanetkar6b44d9e2013-08-15 11:25:38 -0500676 puts("256 KiB ");
Ed Swarthout29372ff2007-07-27 01:50:47 -0500677 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
678 }
679 break;
Kumar Gala73f15a02008-07-14 14:07:00 -0500680 case 0x2:
681 if (ver == SVR_8540 || ver == SVR_8560 ||
York Sun48f6a5c2012-07-06 17:10:33 -0500682 ver == SVR_8541 || ver == SVR_8555) {
Shruti Kanetkar6b44d9e2013-08-15 11:25:38 -0500683 puts("256 KiB ");
684 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
Kumar Gala73f15a02008-07-14 14:07:00 -0500685 cache_ctl = 0xc8000000;
686 } else {
Shruti Kanetkar6b44d9e2013-08-15 11:25:38 -0500687 puts("512 KiB ");
Kumar Gala73f15a02008-07-14 14:07:00 -0500688 /* set L2E=1, L2I=1, & L2SRAM=0 */
689 cache_ctl = 0xc0000000;
690 }
691 break;
692 case 0x3:
Shruti Kanetkar6b44d9e2013-08-15 11:25:38 -0500693 puts("1024 KiB ");
Kumar Gala73f15a02008-07-14 14:07:00 -0500694 /* set L2E=1, L2I=1, & L2SRAM=0 */
695 cache_ctl = 0xc0000000;
696 break;
Jon Loeligerd65cfe82005-07-25 10:58:39 -0500697 }
698
Mingkai Hu76b474e2009-08-18 15:37:15 +0800699 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200700 puts("already enabled");
Haiying Wang888279b2010-12-01 10:35:30 -0500701#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
Kumar Galae4c9a352011-11-09 09:56:41 -0600702 u32 l2srbar = l2cache->l2srbar0;
Mingkai Hu76b474e2009-08-18 15:37:15 +0800703 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
704 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200705 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
Ed Swarthout29372ff2007-07-27 01:50:47 -0500706 l2cache->l2srbar0 = l2srbar;
Scott Wood9a511bd2012-10-29 19:00:41 -0500707 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
Ed Swarthout29372ff2007-07-27 01:50:47 -0500708 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200709#endif /* CONFIG_SYS_INIT_L2_ADDR */
Ed Swarthout29372ff2007-07-27 01:50:47 -0500710 puts("\n");
711 } else {
712 asm("msync;isync");
713 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
714 asm("msync;isync");
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200715 puts("enabled\n");
Ed Swarthout29372ff2007-07-27 01:50:47 -0500716 }
Kumar Gala1b3e4042009-03-19 09:16:10 -0500717#elif defined(CONFIG_BACKSIDE_L2_CACHE)
York Sun48f6a5c2012-07-06 17:10:33 -0500718 if (SVR_SOC_VER(svr) == SVR_P2040) {
Kumar Galaacf3f8d2011-07-21 00:20:21 -0500719 puts("N/A\n");
720 goto skip_l2;
721 }
722
Kumar Gala1b3e4042009-03-19 09:16:10 -0500723 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
724
725 /* invalidate the L2 cache */
Kumar Gala25bacf72009-09-22 15:45:44 -0500726 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
727 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
Kumar Gala1b3e4042009-03-19 09:16:10 -0500728 ;
729
Kumar Gala82fd1f82009-03-19 02:53:01 -0500730#ifdef CONFIG_SYS_CACHE_STASHING
731 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
732 mtspr(SPRN_L2CSR1, (32 + 1));
733#endif
734
Kumar Gala1b3e4042009-03-19 09:16:10 -0500735 /* enable the cache */
736 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
737
Dave Liu654ea1f2009-10-22 00:10:23 -0500738 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
739 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
740 ;
Shruti Kanetkar2f848f92013-08-15 11:25:37 -0500741 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
Dave Liu654ea1f2009-10-22 00:10:23 -0500742 }
Kumar Galaacf3f8d2011-07-21 00:20:21 -0500743
744skip_l2:
Prabhakar Kushwahae9827462013-08-29 13:10:38 +0530745#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
York Sun6d2b9da2012-10-08 07:44:08 +0000746 if (l2cache->l2csr0 & L2CSR0_L2E)
Shruti Kanetkar2f848f92013-08-15 11:25:37 -0500747 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
748 " enabled\n");
York Sun6d2b9da2012-10-08 07:44:08 +0000749
750 enable_cluster_l2();
wdenk42d1f032003-10-15 23:53:47 +0000751#else
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200752 puts("disabled\n");
wdenk42d1f032003-10-15 23:53:47 +0000753#endif
Kumar Gala6aba33e2009-03-19 03:40:08 -0500754
Aneesh Bansalfb4a2402014-03-18 23:40:26 +0530755#if defined(CONFIG_RAMBOOT_PBL)
756 disable_cpc_sram();
757#endif
Kumar Gala6aba33e2009-03-19 03:40:08 -0500758 enable_cpc();
Sandeep Singh377ffcf2014-06-05 18:49:57 +0530759#if defined(T1040_TDM_QUIRK_CCSR_BASE)
760 enable_tdm_law();
761#endif
Kumar Gala6aba33e2009-03-19 03:40:08 -0500762
York Suncb930712013-06-25 11:37:41 -0700763#ifndef CONFIG_SYS_FSL_NO_SERDES
Kumar Galaaf025062010-05-22 13:21:39 -0500764 /* needs to be in ram since code uses global static vars */
765 fsl_serdes_init();
York Suncb930712013-06-25 11:37:41 -0700766#endif
Kumar Galaaf025062010-05-22 13:21:39 -0500767
Shengzhou Liu424bf942013-08-15 09:31:47 +0800768#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
769#define MCFGR_AXIPIPE 0x000000f0
770 if (IS_SVR_REV(svr, 1, 0))
771 clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE);
772#endif
773
Shengzhou Liu72bd83c2013-01-23 19:56:23 +0000774#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
775 if (IS_SVR_REV(svr, 1, 0)) {
776 int i;
777 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
778
779 for (i = 0; i < 12; i++) {
780 p += i + (i > 5 ? 11 : 0);
781 out_be32(p, 0x2);
782 }
783 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
784 out_be32(p, 0x34);
785 }
786#endif
787
Kumar Galaa09b9b62010-12-30 12:09:53 -0600788#ifdef CONFIG_SYS_SRIO
789 srio_init();
Liu Gangc8b28152013-05-07 16:30:46 +0800790#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
Liu Gangff65f122012-08-09 05:09:59 +0000791 char *s = getenv("bootmaster");
792 if (s) {
793 if (!strcmp(s, "SRIO1")) {
794 srio_boot_master(1);
795 srio_boot_master_release_slave(1);
796 }
797 if (!strcmp(s, "SRIO2")) {
798 srio_boot_master(2);
799 srio_boot_master_release_slave(2);
800 }
801 }
Liu Gang5ffa88e2012-03-08 00:33:17 +0000802#endif
Kumar Galaa09b9b62010-12-30 12:09:53 -0600803#endif
804
Kumar Galaec2b74f2008-01-17 16:48:33 -0600805#if defined(CONFIG_MP)
806 setup_mp();
807#endif
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500808
Zang Roy-R619114e0be342012-09-18 09:50:08 +0000809#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
Roy Zangae026ff2011-01-07 00:24:27 -0600810 {
Zang Roy-R619114e0be342012-09-18 09:50:08 +0000811 if (SVR_MAJ(svr) < 3) {
812 void *p;
813 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
814 setbits_be32(p, 1 << (31 - 14));
815 }
Roy Zangae026ff2011-01-07 00:24:27 -0600816 }
817#endif
818
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500819#ifdef CONFIG_SYS_LBC_LCRR
820 /*
821 * Modify the CLKDIV field of LCRR register to improve the writing
822 * speed for NOR flash.
823 */
824 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
825 __raw_readl(&lbc->lcrr);
826 isync();
Kumar Gala2b3a1cd2011-10-03 08:37:57 -0500827#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
828 udelay(100);
829#endif
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500830#endif
831
Roy Zang86221f02011-04-13 00:08:51 -0500832#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
833 {
ramneek mehresh9dee2052013-08-05 16:00:16 +0530834 struct ccsr_usb_phy __iomem *usb_phy1 =
Roy Zang86221f02011-04-13 00:08:51 -0500835 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
Suresh Gupta9c641a82014-02-26 14:29:12 +0530836#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
837 if (has_erratum_a006261())
838 fsl_erratum_a006261_workaround(usb_phy1);
839#endif
Roy Zang86221f02011-04-13 00:08:51 -0500840 out_be32(&usb_phy1->usb_enable_override,
841 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
842 }
843#endif
844#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
845 {
ramneek mehresh9dee2052013-08-05 16:00:16 +0530846 struct ccsr_usb_phy __iomem *usb_phy2 =
Roy Zang86221f02011-04-13 00:08:51 -0500847 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
Suresh Gupta9c641a82014-02-26 14:29:12 +0530848#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
849 if (has_erratum_a006261())
850 fsl_erratum_a006261_workaround(usb_phy2);
851#endif
Roy Zang86221f02011-04-13 00:08:51 -0500852 out_be32(&usb_phy2->usb_enable_override,
853 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
854 }
855#endif
856
Xulei99d7b0a2013-03-11 17:56:34 +0000857#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
858 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
859 * multi-bit ECC errors which has impact on performance, so software
860 * should disable all ECC reporting from USB1 and USB2.
861 */
862 if (IS_SVR_REV(get_svr(), 1, 0)) {
863 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
864 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
865 setbits_be32(&dcfg->ecccr1,
866 (DCSR_DCFG_ECC_DISABLE_USB1 |
867 DCSR_DCFG_ECC_DISABLE_USB2));
868 }
869#endif
870
Roy Zang3fa75c82013-03-25 07:39:33 +0000871#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
ramneek mehresh9dee2052013-08-05 16:00:16 +0530872 struct ccsr_usb_phy __iomem *usb_phy =
Roy Zang3fa75c82013-03-25 07:39:33 +0000873 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
874 setbits_be32(&usb_phy->pllprg[1],
875 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
876 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
877 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
878 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
Nikhil Badolad1c561c2014-04-15 14:44:52 +0530879#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
880 usb_single_source_clk_configure(usb_phy);
881#endif
Roy Zang3fa75c82013-03-25 07:39:33 +0000882 setbits_be32(&usb_phy->port1.ctrl,
883 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
884 setbits_be32(&usb_phy->port1.drvvbuscfg,
885 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
886 setbits_be32(&usb_phy->port1.pwrfltcfg,
887 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
888 setbits_be32(&usb_phy->port2.ctrl,
889 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
890 setbits_be32(&usb_phy->port2.drvvbuscfg,
891 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
892 setbits_be32(&usb_phy->port2.pwrfltcfg,
893 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
Suresh Gupta9c641a82014-02-26 14:29:12 +0530894
895#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
896 if (has_erratum_a006261())
897 fsl_erratum_a006261_workaround(usb_phy);
Roy Zang3fa75c82013-03-25 07:39:33 +0000898#endif
899
Suresh Gupta9c641a82014-02-26 14:29:12 +0530900#endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
901
Kumar Galac916d7c2011-04-13 08:37:44 -0500902#ifdef CONFIG_FMAN_ENET
903 fman_enet_init();
904#endif
905
Timur Tabifbc20aa2011-11-21 17:10:23 -0600906#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
907 /*
908 * For P1022/1013 Rev1.0 silicon, after power on SATA host
909 * controller is configured in legacy mode instead of the
910 * expected enterprise mode. Software needs to clear bit[28]
911 * of HControl register to change to enterprise mode from
912 * legacy mode. We assume that the controller is offline.
913 */
914 if (IS_SVR_REV(svr, 1, 0) &&
915 ((SVR_SOC_VER(svr) == SVR_P1022) ||
York Sun48f6a5c2012-07-06 17:10:33 -0500916 (SVR_SOC_VER(svr) == SVR_P1013))) {
Timur Tabifbc20aa2011-11-21 17:10:23 -0600917 fsl_sata_reg_t *reg;
918
919 /* first SATA controller */
920 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
921 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
922
923 /* second SATA controller */
924 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
925 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
926 }
927#endif
928
Alexander Graff13c9152014-04-30 19:21:12 +0200929 init_used_tlb_cams();
Timur Tabifbc20aa2011-11-21 17:10:23 -0600930
wdenk42d1f032003-10-15 23:53:47 +0000931 return 0;
932}
Kumar Gala26f4cdba2009-08-14 13:37:54 -0500933
Kumar Gala26f4cdba2009-08-14 13:37:54 -0500934void arch_preboot_os(void)
935{
Kumar Gala15fba322009-09-11 15:28:41 -0500936 u32 msr;
937
938 /*
939 * We are changing interrupt offsets and are about to boot the OS so
940 * we need to make sure we disable all async interrupts. EE is already
941 * disabled by the time we get called.
942 */
943 msr = mfmsr();
Prabhakar Kushwaha5344f7a2012-04-29 23:56:30 +0000944 msr &= ~(MSR_ME|MSR_CE);
Kumar Gala15fba322009-09-11 15:28:41 -0500945 mtmsr(msr);
Kumar Gala26f4cdba2009-08-14 13:37:54 -0500946}
Kumar Galaf54fe872010-04-20 10:21:25 -0500947
948#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
949int sata_initialize(void)
950{
951 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
952 return __sata_initialize();
953
954 return 1;
955}
956#endif
Kumar Galaf9a33f12011-02-02 11:23:50 -0600957
958void cpu_secondary_init_r(void)
959{
Zhao Qiang2a44efe2014-03-21 16:21:45 +0800960#ifdef CONFIG_U_QE
961 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
962#elif defined CONFIG_QE
Kumar Galaf9a33f12011-02-02 11:23:50 -0600963 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
Zhao Qiang2a44efe2014-03-21 16:21:45 +0800964#endif
965
966#ifdef CONFIG_QE
Kumar Galaf9a33f12011-02-02 11:23:50 -0600967 qe_init(qe_base);
968 qe_reset();
969#endif
970}