wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1 | /* |
Kumar Gala | a09b9b6 | 2010-12-30 12:09:53 -0600 | [diff] [blame] | 2 | * Copyright 2007-2011 Freescale Semiconductor, Inc. |
Ed Swarthout | 29372ff | 2007-07-27 01:50:47 -0500 | [diff] [blame] | 3 | * |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 4 | * (C) Copyright 2003 Motorola Inc. |
| 5 | * Modified by Xianghua Xiao, X.Xiao@motorola.com |
| 6 | * |
| 7 | * (C) Copyright 2000 |
| 8 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 9 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 10 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #include <common.h> |
| 14 | #include <watchdog.h> |
| 15 | #include <asm/processor.h> |
| 16 | #include <ioports.h> |
Kumar Gala | f54fe87 | 2010-04-20 10:21:25 -0500 | [diff] [blame] | 17 | #include <sata.h> |
Kumar Gala | c916d7c | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 18 | #include <fm_eth.h> |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 19 | #include <asm/io.h> |
Kumar Gala | fd3c9be | 2010-05-05 22:35:27 -0500 | [diff] [blame] | 20 | #include <asm/cache.h> |
Kumar Gala | 8716318 | 2008-01-16 22:38:34 -0600 | [diff] [blame] | 21 | #include <asm/mmu.h> |
Kumar Gala | 83d40df | 2008-01-16 01:13:58 -0600 | [diff] [blame] | 22 | #include <asm/fsl_law.h> |
Kumar Gala | f54fe87 | 2010-04-20 10:21:25 -0500 | [diff] [blame] | 23 | #include <asm/fsl_serdes.h> |
Liu Gang | 5ffa88e | 2012-03-08 00:33:17 +0000 | [diff] [blame] | 24 | #include <asm/fsl_srio.h> |
York Sun | 57125f2 | 2012-08-08 18:04:53 +0000 | [diff] [blame] | 25 | #include <hwconfig.h> |
Timur Tabi | fbc20aa | 2011-11-21 17:10:23 -0600 | [diff] [blame] | 26 | #include <linux/compiler.h> |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 27 | #include "mp.h" |
Timur Tabi | f2717b4 | 2011-11-22 09:21:25 -0600 | [diff] [blame] | 28 | #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND |
Haiying Wang | a7b1e1b | 2011-02-07 16:14:15 -0500 | [diff] [blame] | 29 | #include <nand.h> |
| 30 | #include <errno.h> |
| 31 | #endif |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 32 | |
Timur Tabi | fbc20aa | 2011-11-21 17:10:23 -0600 | [diff] [blame] | 33 | #include "../../../../drivers/block/fsl_sata.h" |
| 34 | |
Wolfgang Denk | d87080b | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 35 | DECLARE_GLOBAL_DATA_PTR; |
| 36 | |
Andy Fleming | da9d461 | 2007-08-14 00:14:25 -0500 | [diff] [blame] | 37 | #ifdef CONFIG_QE |
| 38 | extern qe_iop_conf_t qe_iop_conf_tab[]; |
| 39 | extern void qe_config_iopin(u8 port, u8 pin, int dir, |
| 40 | int open_drain, int assign); |
| 41 | extern void qe_init(uint qe_base); |
| 42 | extern void qe_reset(void); |
| 43 | |
| 44 | static void config_qe_ioports(void) |
| 45 | { |
| 46 | u8 port, pin; |
| 47 | int dir, open_drain, assign; |
| 48 | int i; |
| 49 | |
| 50 | for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { |
| 51 | port = qe_iop_conf_tab[i].port; |
| 52 | pin = qe_iop_conf_tab[i].pin; |
| 53 | dir = qe_iop_conf_tab[i].dir; |
| 54 | open_drain = qe_iop_conf_tab[i].open_drain; |
| 55 | assign = qe_iop_conf_tab[i].assign; |
| 56 | qe_config_iopin(port, pin, dir, open_drain, assign); |
| 57 | } |
| 58 | } |
| 59 | #endif |
Matthew McClintock | 40d5fa3 | 2006-06-28 10:43:36 -0500 | [diff] [blame] | 60 | |
Jon Loeliger | 9c4c5ae | 2005-07-23 10:37:35 -0500 | [diff] [blame] | 61 | #ifdef CONFIG_CPM2 |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 62 | void config_8560_ioports (volatile ccsr_cpm_t * cpm) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 63 | { |
| 64 | int portnum; |
| 65 | |
| 66 | for (portnum = 0; portnum < 4; portnum++) { |
| 67 | uint pmsk = 0, |
| 68 | ppar = 0, |
| 69 | psor = 0, |
| 70 | pdir = 0, |
| 71 | podr = 0, |
| 72 | pdat = 0; |
| 73 | iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; |
| 74 | iop_conf_t *eiopc = iopc + 32; |
| 75 | uint msk = 1; |
| 76 | |
| 77 | /* |
| 78 | * NOTE: |
| 79 | * index 0 refers to pin 31, |
| 80 | * index 31 refers to pin 0 |
| 81 | */ |
| 82 | while (iopc < eiopc) { |
| 83 | if (iopc->conf) { |
| 84 | pmsk |= msk; |
| 85 | if (iopc->ppar) |
| 86 | ppar |= msk; |
| 87 | if (iopc->psor) |
| 88 | psor |= msk; |
| 89 | if (iopc->pdir) |
| 90 | pdir |= msk; |
| 91 | if (iopc->podr) |
| 92 | podr |= msk; |
| 93 | if (iopc->pdat) |
| 94 | pdat |= msk; |
| 95 | } |
| 96 | |
| 97 | msk <<= 1; |
| 98 | iopc++; |
| 99 | } |
| 100 | |
| 101 | if (pmsk != 0) { |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 102 | volatile ioport_t *iop = ioport_addr (cpm, portnum); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 103 | uint tpmsk = ~pmsk; |
| 104 | |
| 105 | /* |
| 106 | * the (somewhat confused) paragraph at the |
| 107 | * bottom of page 35-5 warns that there might |
| 108 | * be "unknown behaviour" when programming |
| 109 | * PSORx and PDIRx, if PPARx = 1, so I |
| 110 | * decided this meant I had to disable the |
| 111 | * dedicated function first, and enable it |
| 112 | * last. |
| 113 | */ |
| 114 | iop->ppar &= tpmsk; |
| 115 | iop->psor = (iop->psor & tpmsk) | psor; |
| 116 | iop->podr = (iop->podr & tpmsk) | podr; |
| 117 | iop->pdat = (iop->pdat & tpmsk) | pdat; |
| 118 | iop->pdir = (iop->pdir & tpmsk) | pdir; |
| 119 | iop->ppar |= ppar; |
| 120 | } |
| 121 | } |
| 122 | } |
| 123 | #endif |
| 124 | |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 125 | #ifdef CONFIG_SYS_FSL_CPC |
| 126 | static void enable_cpc(void) |
| 127 | { |
| 128 | int i; |
| 129 | u32 size = 0; |
| 130 | |
| 131 | cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; |
| 132 | |
| 133 | for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { |
| 134 | u32 cpccfg0 = in_be32(&cpc->cpccfg0); |
| 135 | size += CPC_CFG0_SZ_K(cpccfg0); |
Shaohui Xie | 2a9fab8 | 2011-03-16 10:10:32 +0800 | [diff] [blame] | 136 | #ifdef CONFIG_RAMBOOT_PBL |
| 137 | if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { |
| 138 | /* find and disable LAW of SRAM */ |
| 139 | struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); |
| 140 | |
| 141 | if (law.index == -1) { |
| 142 | printf("\nFatal error happened\n"); |
| 143 | return; |
| 144 | } |
| 145 | disable_law(law.index); |
| 146 | |
| 147 | clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); |
| 148 | out_be32(&cpc->cpccsr0, 0); |
| 149 | out_be32(&cpc->cpcsrcr0, 0); |
| 150 | } |
| 151 | #endif |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 152 | |
Kumar Gala | 1d2c2a6 | 2011-01-13 01:54:01 -0600 | [diff] [blame] | 153 | #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 |
| 154 | setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); |
| 155 | #endif |
Kumar Gala | 868da59 | 2011-01-13 01:56:18 -0600 | [diff] [blame] | 156 | #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 |
| 157 | setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); |
| 158 | #endif |
Scott Wood | 8212519 | 2013-05-15 17:50:13 -0500 | [diff] [blame] | 159 | #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 |
| 160 | setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); |
| 161 | #endif |
Kumar Gala | 1d2c2a6 | 2011-01-13 01:54:01 -0600 | [diff] [blame] | 162 | |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 163 | out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); |
| 164 | /* Read back to sync write */ |
| 165 | in_be32(&cpc->cpccsr0); |
| 166 | |
| 167 | } |
| 168 | |
| 169 | printf("Corenet Platform Cache: %d KB enabled\n", size); |
| 170 | } |
| 171 | |
Kim Phillips | e56143e | 2012-10-29 13:34:38 +0000 | [diff] [blame] | 172 | static void invalidate_cpc(void) |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 173 | { |
| 174 | int i; |
| 175 | cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; |
| 176 | |
| 177 | for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { |
Shaohui Xie | 2a9fab8 | 2011-03-16 10:10:32 +0800 | [diff] [blame] | 178 | /* skip CPC when it used as all SRAM */ |
| 179 | if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) |
| 180 | continue; |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 181 | /* Flash invalidate the CPC and clear all the locks */ |
| 182 | out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); |
| 183 | while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) |
| 184 | ; |
| 185 | } |
| 186 | } |
| 187 | #else |
| 188 | #define enable_cpc() |
| 189 | #define invalidate_cpc() |
| 190 | #endif /* CONFIG_SYS_FSL_CPC */ |
| 191 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 192 | /* |
| 193 | * Breathe some life into the CPU... |
| 194 | * |
| 195 | * Set up the memory map |
| 196 | * initialize a bunch of registers |
| 197 | */ |
| 198 | |
Kumar Gala | 3c2a67e | 2009-09-17 01:52:37 -0500 | [diff] [blame] | 199 | #ifdef CONFIG_FSL_CORENET |
| 200 | static void corenet_tb_init(void) |
| 201 | { |
| 202 | volatile ccsr_rcpm_t *rcpm = |
| 203 | (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); |
| 204 | volatile ccsr_pic_t *pic = |
Kim Phillips | 680c613 | 2010-08-09 18:39:57 -0500 | [diff] [blame] | 205 | (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); |
Kumar Gala | 3c2a67e | 2009-09-17 01:52:37 -0500 | [diff] [blame] | 206 | u32 whoami = in_be32(&pic->whoami); |
| 207 | |
| 208 | /* Enable the timebase register for this core */ |
| 209 | out_be32(&rcpm->ctbenrl, (1 << whoami)); |
| 210 | } |
| 211 | #endif |
| 212 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 213 | void cpu_init_f (void) |
| 214 | { |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 215 | extern void m8560_cpm_reset (void); |
Stephen George | f110fe9 | 2011-07-20 09:47:26 -0500 | [diff] [blame] | 216 | #ifdef CONFIG_SYS_DCSRBAR_PHYS |
| 217 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 218 | #endif |
Ruchika Gupta | 7065b7d | 2010-12-15 17:02:08 +0000 | [diff] [blame] | 219 | #if defined(CONFIG_SECURE_BOOT) |
| 220 | struct law_entry law; |
| 221 | #endif |
Peter Tyser | a2cd50e | 2008-11-11 10:17:10 -0600 | [diff] [blame] | 222 | #ifdef CONFIG_MPC8548 |
| 223 | ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); |
| 224 | uint svr = get_svr(); |
| 225 | |
| 226 | /* |
| 227 | * CPU2 errata workaround: A core hang possible while executing |
| 228 | * a msync instruction and a snoopable transaction from an I/O |
| 229 | * master tagged to make quick forward progress is present. |
| 230 | * Fixed in silicon rev 2.1. |
| 231 | */ |
| 232 | if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) |
| 233 | out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); |
| 234 | #endif |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 235 | |
Kumar Gala | 8716318 | 2008-01-16 22:38:34 -0600 | [diff] [blame] | 236 | disable_tlb(14); |
| 237 | disable_tlb(15); |
| 238 | |
Ruchika Gupta | 7065b7d | 2010-12-15 17:02:08 +0000 | [diff] [blame] | 239 | #if defined(CONFIG_SECURE_BOOT) |
| 240 | /* Disable the LAW created for NOR flash by the PBI commands */ |
| 241 | law = find_law(CONFIG_SYS_PBI_FLASH_BASE); |
| 242 | if (law.index != -1) |
| 243 | disable_law(law.index); |
| 244 | #endif |
| 245 | |
Jon Loeliger | 9c4c5ae | 2005-07-23 10:37:35 -0500 | [diff] [blame] | 246 | #ifdef CONFIG_CPM2 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 247 | config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 248 | #endif |
| 249 | |
Becky Bruce | f51cdaf | 2010-06-17 11:37:20 -0500 | [diff] [blame] | 250 | init_early_memctl_regs(); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 251 | |
Jon Loeliger | 9c4c5ae | 2005-07-23 10:37:35 -0500 | [diff] [blame] | 252 | #if defined(CONFIG_CPM2) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 253 | m8560_cpm_reset(); |
| 254 | #endif |
Andy Fleming | da9d461 | 2007-08-14 00:14:25 -0500 | [diff] [blame] | 255 | #ifdef CONFIG_QE |
| 256 | /* Config QE ioports */ |
| 257 | config_qe_ioports(); |
| 258 | #endif |
Peter Tyser | 79f4333 | 2009-06-30 17:15:47 -0500 | [diff] [blame] | 259 | #if defined(CONFIG_FSL_DMA) |
| 260 | dma_init(); |
| 261 | #endif |
Kumar Gala | 3c2a67e | 2009-09-17 01:52:37 -0500 | [diff] [blame] | 262 | #ifdef CONFIG_FSL_CORENET |
| 263 | corenet_tb_init(); |
| 264 | #endif |
Kumar Gala | 94e9411 | 2009-11-12 10:26:16 -0600 | [diff] [blame] | 265 | init_used_tlb_cams(); |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 266 | |
| 267 | /* Invalidate the CPC before DDR gets enabled */ |
| 268 | invalidate_cpc(); |
Stephen George | f110fe9 | 2011-07-20 09:47:26 -0500 | [diff] [blame] | 269 | |
| 270 | #ifdef CONFIG_SYS_DCSRBAR_PHYS |
| 271 | /* set DCSRCR so that DCSR space is 1G */ |
| 272 | setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); |
| 273 | in_be32(&gur->dcsrcr); |
| 274 | #endif |
| 275 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 276 | } |
| 277 | |
Kumar Gala | 35079aa | 2010-12-15 03:50:47 -0600 | [diff] [blame] | 278 | /* Implement a dummy function for those platforms w/o SERDES */ |
| 279 | static void __fsl_serdes__init(void) |
| 280 | { |
| 281 | return ; |
| 282 | } |
| 283 | __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 284 | |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 285 | #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 |
| 286 | int enable_cluster_l2(void) |
| 287 | { |
| 288 | int i = 0; |
| 289 | u32 cluster; |
| 290 | ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 291 | struct ccsr_cluster_l2 __iomem *l2cache; |
| 292 | |
| 293 | cluster = in_be32(&gur->tp_cluster[i].lower); |
| 294 | if (cluster & TP_CLUSTER_EOC) |
| 295 | return 0; |
| 296 | |
| 297 | /* The first cache has already been set up, so skip it */ |
| 298 | i++; |
| 299 | |
| 300 | /* Look through the remaining clusters, and set up their caches */ |
| 301 | do { |
Prabhakar Kushwaha | db9a807 | 2012-12-23 19:25:18 +0000 | [diff] [blame] | 302 | int j, cluster_valid = 0; |
| 303 | |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 304 | l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); |
Prabhakar Kushwaha | db9a807 | 2012-12-23 19:25:18 +0000 | [diff] [blame] | 305 | |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 306 | cluster = in_be32(&gur->tp_cluster[i].lower); |
| 307 | |
Prabhakar Kushwaha | db9a807 | 2012-12-23 19:25:18 +0000 | [diff] [blame] | 308 | /* check that at least one core/accel is enabled in cluster */ |
| 309 | for (j = 0; j < 4; j++) { |
| 310 | u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; |
| 311 | u32 type = in_be32(&gur->tp_ityp[idx]); |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 312 | |
Prabhakar Kushwaha | db9a807 | 2012-12-23 19:25:18 +0000 | [diff] [blame] | 313 | if (type & TP_ITYP_AV) |
| 314 | cluster_valid = 1; |
| 315 | } |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 316 | |
Prabhakar Kushwaha | db9a807 | 2012-12-23 19:25:18 +0000 | [diff] [blame] | 317 | if (cluster_valid) { |
| 318 | /* set stash ID to (cluster) * 2 + 32 + 1 */ |
| 319 | clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); |
| 320 | |
| 321 | printf("enable l2 for cluster %d %p\n", i, l2cache); |
| 322 | |
| 323 | out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); |
| 324 | while ((in_be32(&l2cache->l2csr0) |
| 325 | & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) |
| 326 | ; |
James Yang | 9cd95ac | 2013-03-25 07:40:03 +0000 | [diff] [blame] | 327 | out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); |
Prabhakar Kushwaha | db9a807 | 2012-12-23 19:25:18 +0000 | [diff] [blame] | 328 | } |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 329 | i++; |
| 330 | } while (!(cluster & TP_CLUSTER_EOC)); |
| 331 | |
| 332 | return 0; |
| 333 | } |
| 334 | #endif |
| 335 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 336 | /* |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 337 | * Initialize L2 as cache. |
| 338 | * |
| 339 | * The newer 8548, etc, parts have twice as much cache, but |
| 340 | * use the same bit-encoding as the older 8555, etc, parts. |
| 341 | * |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 342 | */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 343 | int cpu_init_r(void) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 344 | { |
Timur Tabi | fbc20aa | 2011-11-21 17:10:23 -0600 | [diff] [blame] | 345 | __maybe_unused u32 svr = get_svr(); |
Lan Chunhe | 3f0202e | 2010-04-21 07:40:50 -0500 | [diff] [blame] | 346 | #ifdef CONFIG_SYS_LBC_LCRR |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 347 | fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; |
| 348 | #endif |
| 349 | #ifdef CONFIG_L2_CACHE |
| 350 | ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; |
| 351 | #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) |
| 352 | struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; |
Lan Chunhe | 3f0202e | 2010-04-21 07:40:50 -0500 | [diff] [blame] | 353 | #endif |
York Sun | afbfdf5 | 2012-11-08 12:33:39 +0000 | [diff] [blame] | 354 | #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) |
York Sun | 2a5fcb8 | 2012-10-28 08:12:54 +0000 | [diff] [blame] | 355 | extern int spin_table_compat; |
| 356 | const char *spin; |
| 357 | #endif |
Lan Chunhe | 3f0202e | 2010-04-21 07:40:50 -0500 | [diff] [blame] | 358 | |
York Sun | 5e23ab0 | 2012-05-07 07:26:47 +0000 | [diff] [blame] | 359 | #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ |
| 360 | defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) |
| 361 | /* |
York Sun | 57125f2 | 2012-08-08 18:04:53 +0000 | [diff] [blame] | 362 | * CPU22 and NMG_CPU_A011 share the same workaround. |
York Sun | 5e23ab0 | 2012-05-07 07:26:47 +0000 | [diff] [blame] | 363 | * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 |
| 364 | * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 |
York Sun | 57125f2 | 2012-08-08 18:04:53 +0000 | [diff] [blame] | 365 | * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both |
| 366 | * fixed in 2.0. NMG_CPU_A011 is activated by default and can |
| 367 | * be disabled by hwconfig with syntax: |
| 368 | * |
| 369 | * fsl_cpu_a011:disable |
York Sun | 5e23ab0 | 2012-05-07 07:26:47 +0000 | [diff] [blame] | 370 | */ |
York Sun | 57125f2 | 2012-08-08 18:04:53 +0000 | [diff] [blame] | 371 | extern int enable_cpu_a011_workaround; |
| 372 | #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 |
| 373 | enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); |
| 374 | #else |
| 375 | char buffer[HWCONFIG_BUFFER_SIZE]; |
| 376 | char *buf = NULL; |
| 377 | int n, res; |
| 378 | |
| 379 | n = getenv_f("hwconfig", buffer, sizeof(buffer)); |
| 380 | if (n > 0) |
| 381 | buf = buffer; |
| 382 | |
| 383 | res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); |
| 384 | if (res > 0) |
| 385 | enable_cpu_a011_workaround = 0; |
| 386 | else { |
| 387 | if (n >= HWCONFIG_BUFFER_SIZE) { |
| 388 | printf("fsl_cpu_a011 was not found. hwconfig variable " |
| 389 | "may be too long\n"); |
| 390 | } |
| 391 | enable_cpu_a011_workaround = |
| 392 | (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || |
| 393 | (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); |
| 394 | } |
| 395 | #endif |
| 396 | if (enable_cpu_a011_workaround) { |
York Sun | 1e9ea85 | 2012-05-07 07:26:45 +0000 | [diff] [blame] | 397 | flush_dcache(); |
| 398 | mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); |
| 399 | sync(); |
| 400 | } |
Kumar Gala | fd3c9be | 2010-05-05 22:35:27 -0500 | [diff] [blame] | 401 | #endif |
York Sun | d217a9a | 2013-06-25 11:37:49 -0700 | [diff] [blame^] | 402 | #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 |
| 403 | /* |
| 404 | * A-005812 workaround sets bit 32 of SPR 976 for SoCs running |
| 405 | * in write shadow mode. Checking DCWS before setting SPR 976. |
| 406 | */ |
| 407 | if (mfspr(L1CSR2) & L1CSR2_DCWS) |
| 408 | mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); |
| 409 | #endif |
Kumar Gala | fd3c9be | 2010-05-05 22:35:27 -0500 | [diff] [blame] | 410 | |
York Sun | afbfdf5 | 2012-11-08 12:33:39 +0000 | [diff] [blame] | 411 | #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) |
York Sun | 2a5fcb8 | 2012-10-28 08:12:54 +0000 | [diff] [blame] | 412 | spin = getenv("spin_table_compat"); |
| 413 | if (spin && (*spin == 'n')) |
| 414 | spin_table_compat = 0; |
| 415 | else |
| 416 | spin_table_compat = 1; |
| 417 | #endif |
| 418 | |
Wolfgang Grandegger | 6beecfb | 2008-06-05 13:11:59 +0200 | [diff] [blame] | 419 | puts ("L2: "); |
| 420 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 421 | #if defined(CONFIG_L2_CACHE) |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 422 | volatile uint cache_ctl; |
Timur Tabi | fbc20aa | 2011-11-21 17:10:23 -0600 | [diff] [blame] | 423 | uint ver; |
Kumar Gala | 73f15a0 | 2008-07-14 14:07:00 -0500 | [diff] [blame] | 424 | u32 l2siz_field; |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 425 | |
Kumar Gala | f3e04bd | 2008-04-08 10:45:50 -0500 | [diff] [blame] | 426 | ver = SVR_SOC_VER(svr); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 427 | |
| 428 | asm("msync;isync"); |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 429 | cache_ctl = l2cache->l2ctl; |
Mingkai Hu | 7da5335 | 2009-09-11 14:19:10 +0800 | [diff] [blame] | 430 | |
| 431 | #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) |
| 432 | if (cache_ctl & MPC85xx_L2CTL_L2E) { |
| 433 | /* Clear L2 SRAM memory-mapped base address */ |
| 434 | out_be32(&l2cache->l2srbar0, 0x0); |
| 435 | out_be32(&l2cache->l2srbar1, 0x0); |
| 436 | |
| 437 | /* set MBECCDIS=0, SBECCDIS=0 */ |
| 438 | clrbits_be32(&l2cache->l2errdis, |
| 439 | (MPC85xx_L2ERRDIS_MBECC | |
| 440 | MPC85xx_L2ERRDIS_SBECC)); |
| 441 | |
| 442 | /* set L2E=0, L2SRAM=0 */ |
| 443 | clrbits_be32(&l2cache->l2ctl, |
| 444 | (MPC85xx_L2CTL_L2E | |
| 445 | MPC85xx_L2CTL_L2SRAM_ENTIRE)); |
| 446 | } |
| 447 | #endif |
| 448 | |
Kumar Gala | 73f15a0 | 2008-07-14 14:07:00 -0500 | [diff] [blame] | 449 | l2siz_field = (cache_ctl >> 28) & 0x3; |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 450 | |
Kumar Gala | 73f15a0 | 2008-07-14 14:07:00 -0500 | [diff] [blame] | 451 | switch (l2siz_field) { |
| 452 | case 0x0: |
| 453 | printf(" unknown size (0x%08x)\n", cache_ctl); |
| 454 | return -1; |
| 455 | break; |
| 456 | case 0x1: |
| 457 | if (ver == SVR_8540 || ver == SVR_8560 || |
York Sun | 48f6a5c | 2012-07-06 17:10:33 -0500 | [diff] [blame] | 458 | ver == SVR_8541 || ver == SVR_8555) { |
Kumar Gala | 73f15a0 | 2008-07-14 14:07:00 -0500 | [diff] [blame] | 459 | puts("128 KB "); |
| 460 | /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ |
| 461 | cache_ctl = 0xc4000000; |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 462 | } else { |
Wolfgang Grandegger | 6beecfb | 2008-06-05 13:11:59 +0200 | [diff] [blame] | 463 | puts("256 KB "); |
Ed Swarthout | 29372ff | 2007-07-27 01:50:47 -0500 | [diff] [blame] | 464 | cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ |
| 465 | } |
| 466 | break; |
Kumar Gala | 73f15a0 | 2008-07-14 14:07:00 -0500 | [diff] [blame] | 467 | case 0x2: |
| 468 | if (ver == SVR_8540 || ver == SVR_8560 || |
York Sun | 48f6a5c | 2012-07-06 17:10:33 -0500 | [diff] [blame] | 469 | ver == SVR_8541 || ver == SVR_8555) { |
Kumar Gala | 73f15a0 | 2008-07-14 14:07:00 -0500 | [diff] [blame] | 470 | puts("256 KB "); |
| 471 | /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ |
| 472 | cache_ctl = 0xc8000000; |
| 473 | } else { |
| 474 | puts ("512 KB "); |
| 475 | /* set L2E=1, L2I=1, & L2SRAM=0 */ |
| 476 | cache_ctl = 0xc0000000; |
| 477 | } |
| 478 | break; |
| 479 | case 0x3: |
| 480 | puts("1024 KB "); |
| 481 | /* set L2E=1, L2I=1, & L2SRAM=0 */ |
| 482 | cache_ctl = 0xc0000000; |
| 483 | break; |
Jon Loeliger | d65cfe8 | 2005-07-25 10:58:39 -0500 | [diff] [blame] | 484 | } |
| 485 | |
Mingkai Hu | 76b474e | 2009-08-18 15:37:15 +0800 | [diff] [blame] | 486 | if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { |
Wolfgang Grandegger | 6beecfb | 2008-06-05 13:11:59 +0200 | [diff] [blame] | 487 | puts("already enabled"); |
Haiying Wang | 888279b | 2010-12-01 10:35:30 -0500 | [diff] [blame] | 488 | #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) |
Kumar Gala | e4c9a35 | 2011-11-09 09:56:41 -0600 | [diff] [blame] | 489 | u32 l2srbar = l2cache->l2srbar0; |
Mingkai Hu | 76b474e | 2009-08-18 15:37:15 +0800 | [diff] [blame] | 490 | if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE |
| 491 | && l2srbar >= CONFIG_SYS_FLASH_BASE) { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 492 | l2srbar = CONFIG_SYS_INIT_L2_ADDR; |
Ed Swarthout | 29372ff | 2007-07-27 01:50:47 -0500 | [diff] [blame] | 493 | l2cache->l2srbar0 = l2srbar; |
Scott Wood | 9a511bd | 2012-10-29 19:00:41 -0500 | [diff] [blame] | 494 | printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); |
Ed Swarthout | 29372ff | 2007-07-27 01:50:47 -0500 | [diff] [blame] | 495 | } |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 496 | #endif /* CONFIG_SYS_INIT_L2_ADDR */ |
Ed Swarthout | 29372ff | 2007-07-27 01:50:47 -0500 | [diff] [blame] | 497 | puts("\n"); |
| 498 | } else { |
| 499 | asm("msync;isync"); |
| 500 | l2cache->l2ctl = cache_ctl; /* invalidate & enable */ |
| 501 | asm("msync;isync"); |
Wolfgang Grandegger | 6beecfb | 2008-06-05 13:11:59 +0200 | [diff] [blame] | 502 | puts("enabled\n"); |
Ed Swarthout | 29372ff | 2007-07-27 01:50:47 -0500 | [diff] [blame] | 503 | } |
Kumar Gala | 1b3e404 | 2009-03-19 09:16:10 -0500 | [diff] [blame] | 504 | #elif defined(CONFIG_BACKSIDE_L2_CACHE) |
York Sun | 48f6a5c | 2012-07-06 17:10:33 -0500 | [diff] [blame] | 505 | if (SVR_SOC_VER(svr) == SVR_P2040) { |
Kumar Gala | acf3f8d | 2011-07-21 00:20:21 -0500 | [diff] [blame] | 506 | puts("N/A\n"); |
| 507 | goto skip_l2; |
| 508 | } |
| 509 | |
Kumar Gala | 1b3e404 | 2009-03-19 09:16:10 -0500 | [diff] [blame] | 510 | u32 l2cfg0 = mfspr(SPRN_L2CFG0); |
| 511 | |
| 512 | /* invalidate the L2 cache */ |
Kumar Gala | 25bacf7 | 2009-09-22 15:45:44 -0500 | [diff] [blame] | 513 | mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); |
| 514 | while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) |
Kumar Gala | 1b3e404 | 2009-03-19 09:16:10 -0500 | [diff] [blame] | 515 | ; |
| 516 | |
Kumar Gala | 82fd1f8 | 2009-03-19 02:53:01 -0500 | [diff] [blame] | 517 | #ifdef CONFIG_SYS_CACHE_STASHING |
| 518 | /* set stash id to (coreID) * 2 + 32 + L2 (1) */ |
| 519 | mtspr(SPRN_L2CSR1, (32 + 1)); |
| 520 | #endif |
| 521 | |
Kumar Gala | 1b3e404 | 2009-03-19 09:16:10 -0500 | [diff] [blame] | 522 | /* enable the cache */ |
| 523 | mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); |
| 524 | |
Dave Liu | 654ea1f | 2009-10-22 00:10:23 -0500 | [diff] [blame] | 525 | if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { |
| 526 | while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) |
| 527 | ; |
Kumar Gala | 1b3e404 | 2009-03-19 09:16:10 -0500 | [diff] [blame] | 528 | printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); |
Dave Liu | 654ea1f | 2009-10-22 00:10:23 -0500 | [diff] [blame] | 529 | } |
Kumar Gala | acf3f8d | 2011-07-21 00:20:21 -0500 | [diff] [blame] | 530 | |
| 531 | skip_l2: |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 532 | #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) |
| 533 | if (l2cache->l2csr0 & L2CSR0_L2E) |
| 534 | printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64); |
| 535 | |
| 536 | enable_cluster_l2(); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 537 | #else |
Wolfgang Grandegger | 6beecfb | 2008-06-05 13:11:59 +0200 | [diff] [blame] | 538 | puts("disabled\n"); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 539 | #endif |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 540 | |
| 541 | enable_cpc(); |
| 542 | |
York Sun | cb93071 | 2013-06-25 11:37:41 -0700 | [diff] [blame] | 543 | #ifndef CONFIG_SYS_FSL_NO_SERDES |
Kumar Gala | af02506 | 2010-05-22 13:21:39 -0500 | [diff] [blame] | 544 | /* needs to be in ram since code uses global static vars */ |
| 545 | fsl_serdes_init(); |
York Sun | cb93071 | 2013-06-25 11:37:41 -0700 | [diff] [blame] | 546 | #endif |
Kumar Gala | af02506 | 2010-05-22 13:21:39 -0500 | [diff] [blame] | 547 | |
Shengzhou Liu | 72bd83c | 2013-01-23 19:56:23 +0000 | [diff] [blame] | 548 | #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 |
| 549 | if (IS_SVR_REV(svr, 1, 0)) { |
| 550 | int i; |
| 551 | __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; |
| 552 | |
| 553 | for (i = 0; i < 12; i++) { |
| 554 | p += i + (i > 5 ? 11 : 0); |
| 555 | out_be32(p, 0x2); |
| 556 | } |
| 557 | p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; |
| 558 | out_be32(p, 0x34); |
| 559 | } |
| 560 | #endif |
| 561 | |
Kumar Gala | a09b9b6 | 2010-12-30 12:09:53 -0600 | [diff] [blame] | 562 | #ifdef CONFIG_SYS_SRIO |
| 563 | srio_init(); |
Liu Gang | c8b2815 | 2013-05-07 16:30:46 +0800 | [diff] [blame] | 564 | #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER |
Liu Gang | ff65f12 | 2012-08-09 05:09:59 +0000 | [diff] [blame] | 565 | char *s = getenv("bootmaster"); |
| 566 | if (s) { |
| 567 | if (!strcmp(s, "SRIO1")) { |
| 568 | srio_boot_master(1); |
| 569 | srio_boot_master_release_slave(1); |
| 570 | } |
| 571 | if (!strcmp(s, "SRIO2")) { |
| 572 | srio_boot_master(2); |
| 573 | srio_boot_master_release_slave(2); |
| 574 | } |
| 575 | } |
Liu Gang | 5ffa88e | 2012-03-08 00:33:17 +0000 | [diff] [blame] | 576 | #endif |
Kumar Gala | a09b9b6 | 2010-12-30 12:09:53 -0600 | [diff] [blame] | 577 | #endif |
| 578 | |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 579 | #if defined(CONFIG_MP) |
| 580 | setup_mp(); |
| 581 | #endif |
Lan Chunhe | 3f0202e | 2010-04-21 07:40:50 -0500 | [diff] [blame] | 582 | |
Zang Roy-R61911 | 4e0be34 | 2012-09-18 09:50:08 +0000 | [diff] [blame] | 583 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 |
Roy Zang | ae026ff | 2011-01-07 00:24:27 -0600 | [diff] [blame] | 584 | { |
Zang Roy-R61911 | 4e0be34 | 2012-09-18 09:50:08 +0000 | [diff] [blame] | 585 | if (SVR_MAJ(svr) < 3) { |
| 586 | void *p; |
| 587 | p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; |
| 588 | setbits_be32(p, 1 << (31 - 14)); |
| 589 | } |
Roy Zang | ae026ff | 2011-01-07 00:24:27 -0600 | [diff] [blame] | 590 | } |
| 591 | #endif |
| 592 | |
Lan Chunhe | 3f0202e | 2010-04-21 07:40:50 -0500 | [diff] [blame] | 593 | #ifdef CONFIG_SYS_LBC_LCRR |
| 594 | /* |
| 595 | * Modify the CLKDIV field of LCRR register to improve the writing |
| 596 | * speed for NOR flash. |
| 597 | */ |
| 598 | clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); |
| 599 | __raw_readl(&lbc->lcrr); |
| 600 | isync(); |
Kumar Gala | 2b3a1cd | 2011-10-03 08:37:57 -0500 | [diff] [blame] | 601 | #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 |
| 602 | udelay(100); |
| 603 | #endif |
Lan Chunhe | 3f0202e | 2010-04-21 07:40:50 -0500 | [diff] [blame] | 604 | #endif |
| 605 | |
Roy Zang | 86221f0 | 2011-04-13 00:08:51 -0500 | [diff] [blame] | 606 | #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE |
| 607 | { |
| 608 | ccsr_usb_phy_t *usb_phy1 = |
| 609 | (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; |
| 610 | out_be32(&usb_phy1->usb_enable_override, |
| 611 | CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); |
| 612 | } |
| 613 | #endif |
| 614 | #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE |
| 615 | { |
| 616 | ccsr_usb_phy_t *usb_phy2 = |
| 617 | (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; |
| 618 | out_be32(&usb_phy2->usb_enable_override, |
| 619 | CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); |
| 620 | } |
| 621 | #endif |
| 622 | |
Xulei | 99d7b0a | 2013-03-11 17:56:34 +0000 | [diff] [blame] | 623 | #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 |
| 624 | /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal |
| 625 | * multi-bit ECC errors which has impact on performance, so software |
| 626 | * should disable all ECC reporting from USB1 and USB2. |
| 627 | */ |
| 628 | if (IS_SVR_REV(get_svr(), 1, 0)) { |
| 629 | struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) |
| 630 | (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); |
| 631 | setbits_be32(&dcfg->ecccr1, |
| 632 | (DCSR_DCFG_ECC_DISABLE_USB1 | |
| 633 | DCSR_DCFG_ECC_DISABLE_USB2)); |
| 634 | } |
| 635 | #endif |
| 636 | |
Roy Zang | 3fa75c8 | 2013-03-25 07:39:33 +0000 | [diff] [blame] | 637 | #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) |
| 638 | ccsr_usb_phy_t *usb_phy = |
| 639 | (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; |
| 640 | setbits_be32(&usb_phy->pllprg[1], |
| 641 | CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | |
| 642 | CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | |
| 643 | CONFIG_SYS_FSL_USB_PLLPRG2_MFI | |
| 644 | CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); |
| 645 | setbits_be32(&usb_phy->port1.ctrl, |
| 646 | CONFIG_SYS_FSL_USB_CTRL_PHY_EN); |
| 647 | setbits_be32(&usb_phy->port1.drvvbuscfg, |
| 648 | CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); |
| 649 | setbits_be32(&usb_phy->port1.pwrfltcfg, |
| 650 | CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); |
| 651 | setbits_be32(&usb_phy->port2.ctrl, |
| 652 | CONFIG_SYS_FSL_USB_CTRL_PHY_EN); |
| 653 | setbits_be32(&usb_phy->port2.drvvbuscfg, |
| 654 | CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); |
| 655 | setbits_be32(&usb_phy->port2.pwrfltcfg, |
| 656 | CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); |
| 657 | #endif |
| 658 | |
Kumar Gala | c916d7c | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 659 | #ifdef CONFIG_FMAN_ENET |
| 660 | fman_enet_init(); |
| 661 | #endif |
| 662 | |
Timur Tabi | fbc20aa | 2011-11-21 17:10:23 -0600 | [diff] [blame] | 663 | #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) |
| 664 | /* |
| 665 | * For P1022/1013 Rev1.0 silicon, after power on SATA host |
| 666 | * controller is configured in legacy mode instead of the |
| 667 | * expected enterprise mode. Software needs to clear bit[28] |
| 668 | * of HControl register to change to enterprise mode from |
| 669 | * legacy mode. We assume that the controller is offline. |
| 670 | */ |
| 671 | if (IS_SVR_REV(svr, 1, 0) && |
| 672 | ((SVR_SOC_VER(svr) == SVR_P1022) || |
York Sun | 48f6a5c | 2012-07-06 17:10:33 -0500 | [diff] [blame] | 673 | (SVR_SOC_VER(svr) == SVR_P1013))) { |
Timur Tabi | fbc20aa | 2011-11-21 17:10:23 -0600 | [diff] [blame] | 674 | fsl_sata_reg_t *reg; |
| 675 | |
| 676 | /* first SATA controller */ |
| 677 | reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; |
| 678 | clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); |
| 679 | |
| 680 | /* second SATA controller */ |
| 681 | reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; |
| 682 | clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); |
| 683 | } |
| 684 | #endif |
| 685 | |
| 686 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 687 | return 0; |
| 688 | } |
Kumar Gala | 26f4cdba | 2009-08-14 13:37:54 -0500 | [diff] [blame] | 689 | |
| 690 | extern void setup_ivors(void); |
| 691 | |
| 692 | void arch_preboot_os(void) |
| 693 | { |
Kumar Gala | 15fba32 | 2009-09-11 15:28:41 -0500 | [diff] [blame] | 694 | u32 msr; |
| 695 | |
| 696 | /* |
| 697 | * We are changing interrupt offsets and are about to boot the OS so |
| 698 | * we need to make sure we disable all async interrupts. EE is already |
| 699 | * disabled by the time we get called. |
| 700 | */ |
| 701 | msr = mfmsr(); |
Prabhakar Kushwaha | 5344f7a | 2012-04-29 23:56:30 +0000 | [diff] [blame] | 702 | msr &= ~(MSR_ME|MSR_CE); |
Kumar Gala | 15fba32 | 2009-09-11 15:28:41 -0500 | [diff] [blame] | 703 | mtmsr(msr); |
| 704 | |
Kumar Gala | 26f4cdba | 2009-08-14 13:37:54 -0500 | [diff] [blame] | 705 | setup_ivors(); |
| 706 | } |
Kumar Gala | f54fe87 | 2010-04-20 10:21:25 -0500 | [diff] [blame] | 707 | |
| 708 | #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) |
| 709 | int sata_initialize(void) |
| 710 | { |
| 711 | if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) |
| 712 | return __sata_initialize(); |
| 713 | |
| 714 | return 1; |
| 715 | } |
| 716 | #endif |
Kumar Gala | f9a33f1 | 2011-02-02 11:23:50 -0600 | [diff] [blame] | 717 | |
| 718 | void cpu_secondary_init_r(void) |
| 719 | { |
| 720 | #ifdef CONFIG_QE |
| 721 | uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ |
Timur Tabi | f2717b4 | 2011-11-22 09:21:25 -0600 | [diff] [blame] | 722 | #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND |
Haiying Wang | a7b1e1b | 2011-02-07 16:14:15 -0500 | [diff] [blame] | 723 | int ret; |
Timur Tabi | f2717b4 | 2011-11-22 09:21:25 -0600 | [diff] [blame] | 724 | size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; |
Haiying Wang | a7b1e1b | 2011-02-07 16:14:15 -0500 | [diff] [blame] | 725 | |
| 726 | /* load QE firmware from NAND flash to DDR first */ |
Timur Tabi | f2717b4 | 2011-11-22 09:21:25 -0600 | [diff] [blame] | 727 | ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, |
| 728 | &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR); |
Haiying Wang | a7b1e1b | 2011-02-07 16:14:15 -0500 | [diff] [blame] | 729 | |
| 730 | if (ret && ret == -EUCLEAN) { |
| 731 | printf ("NAND read for QE firmware at offset %x failed %d\n", |
Timur Tabi | f2717b4 | 2011-11-22 09:21:25 -0600 | [diff] [blame] | 732 | CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret); |
Haiying Wang | a7b1e1b | 2011-02-07 16:14:15 -0500 | [diff] [blame] | 733 | } |
| 734 | #endif |
Kumar Gala | f9a33f1 | 2011-02-02 11:23:50 -0600 | [diff] [blame] | 735 | qe_init(qe_base); |
| 736 | qe_reset(); |
| 737 | #endif |
| 738 | } |