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wdenk42d1f032003-10-15 23:53:47 +00001/*
Kumar Galaa09b9b62010-12-30 12:09:53 -06002 * Copyright 2007-2011 Freescale Semiconductor, Inc.
Ed Swarthout29372ff2007-07-27 01:50:47 -05003 *
wdenk42d1f032003-10-15 23:53:47 +00004 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <watchdog.h>
31#include <asm/processor.h>
32#include <ioports.h>
Kumar Galaf54fe872010-04-20 10:21:25 -050033#include <sata.h>
Kumar Galac916d7c2011-04-13 08:37:44 -050034#include <fm_eth.h>
wdenk42d1f032003-10-15 23:53:47 +000035#include <asm/io.h>
Kumar Galafd3c9be2010-05-05 22:35:27 -050036#include <asm/cache.h>
Kumar Gala87163182008-01-16 22:38:34 -060037#include <asm/mmu.h>
Kumar Gala83d40df2008-01-16 01:13:58 -060038#include <asm/fsl_law.h>
Kumar Galaf54fe872010-04-20 10:21:25 -050039#include <asm/fsl_serdes.h>
Liu Gang5ffa88e2012-03-08 00:33:17 +000040#include <asm/fsl_srio.h>
York Sun57125f22012-08-08 18:04:53 +000041#include <hwconfig.h>
Timur Tabifbc20aa2011-11-21 17:10:23 -060042#include <linux/compiler.h>
Kumar Galaec2b74f2008-01-17 16:48:33 -060043#include "mp.h"
Timur Tabif2717b42011-11-22 09:21:25 -060044#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
Haiying Wanga7b1e1b2011-02-07 16:14:15 -050045#include <nand.h>
46#include <errno.h>
47#endif
wdenk42d1f032003-10-15 23:53:47 +000048
Timur Tabifbc20aa2011-11-21 17:10:23 -060049#include "../../../../drivers/block/fsl_sata.h"
50
Wolfgang Denkd87080b2006-03-31 18:32:53 +020051DECLARE_GLOBAL_DATA_PTR;
52
Andy Flemingda9d4612007-08-14 00:14:25 -050053#ifdef CONFIG_QE
54extern qe_iop_conf_t qe_iop_conf_tab[];
55extern void qe_config_iopin(u8 port, u8 pin, int dir,
56 int open_drain, int assign);
57extern void qe_init(uint qe_base);
58extern void qe_reset(void);
59
60static void config_qe_ioports(void)
61{
62 u8 port, pin;
63 int dir, open_drain, assign;
64 int i;
65
66 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
67 port = qe_iop_conf_tab[i].port;
68 pin = qe_iop_conf_tab[i].pin;
69 dir = qe_iop_conf_tab[i].dir;
70 open_drain = qe_iop_conf_tab[i].open_drain;
71 assign = qe_iop_conf_tab[i].assign;
72 qe_config_iopin(port, pin, dir, open_drain, assign);
73 }
74}
75#endif
Matthew McClintock40d5fa32006-06-28 10:43:36 -050076
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050077#ifdef CONFIG_CPM2
Kumar Galaaafeefb2007-11-28 00:36:33 -060078void config_8560_ioports (volatile ccsr_cpm_t * cpm)
wdenk42d1f032003-10-15 23:53:47 +000079{
80 int portnum;
81
82 for (portnum = 0; portnum < 4; portnum++) {
83 uint pmsk = 0,
84 ppar = 0,
85 psor = 0,
86 pdir = 0,
87 podr = 0,
88 pdat = 0;
89 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
90 iop_conf_t *eiopc = iopc + 32;
91 uint msk = 1;
92
93 /*
94 * NOTE:
95 * index 0 refers to pin 31,
96 * index 31 refers to pin 0
97 */
98 while (iopc < eiopc) {
99 if (iopc->conf) {
100 pmsk |= msk;
101 if (iopc->ppar)
102 ppar |= msk;
103 if (iopc->psor)
104 psor |= msk;
105 if (iopc->pdir)
106 pdir |= msk;
107 if (iopc->podr)
108 podr |= msk;
109 if (iopc->pdat)
110 pdat |= msk;
111 }
112
113 msk <<= 1;
114 iopc++;
115 }
116
117 if (pmsk != 0) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600118 volatile ioport_t *iop = ioport_addr (cpm, portnum);
wdenk42d1f032003-10-15 23:53:47 +0000119 uint tpmsk = ~pmsk;
120
121 /*
122 * the (somewhat confused) paragraph at the
123 * bottom of page 35-5 warns that there might
124 * be "unknown behaviour" when programming
125 * PSORx and PDIRx, if PPARx = 1, so I
126 * decided this meant I had to disable the
127 * dedicated function first, and enable it
128 * last.
129 */
130 iop->ppar &= tpmsk;
131 iop->psor = (iop->psor & tpmsk) | psor;
132 iop->podr = (iop->podr & tpmsk) | podr;
133 iop->pdat = (iop->pdat & tpmsk) | pdat;
134 iop->pdir = (iop->pdir & tpmsk) | pdir;
135 iop->ppar |= ppar;
136 }
137 }
138}
139#endif
140
Kumar Gala6aba33e2009-03-19 03:40:08 -0500141#ifdef CONFIG_SYS_FSL_CPC
142static void enable_cpc(void)
143{
144 int i;
145 u32 size = 0;
146
147 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
148
149 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
150 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
151 size += CPC_CFG0_SZ_K(cpccfg0);
Shaohui Xie2a9fab82011-03-16 10:10:32 +0800152#ifdef CONFIG_RAMBOOT_PBL
153 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
154 /* find and disable LAW of SRAM */
155 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
156
157 if (law.index == -1) {
158 printf("\nFatal error happened\n");
159 return;
160 }
161 disable_law(law.index);
162
163 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
164 out_be32(&cpc->cpccsr0, 0);
165 out_be32(&cpc->cpcsrcr0, 0);
166 }
167#endif
Kumar Gala6aba33e2009-03-19 03:40:08 -0500168
Kumar Gala1d2c2a62011-01-13 01:54:01 -0600169#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
170 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
171#endif
Kumar Gala868da592011-01-13 01:56:18 -0600172#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
173 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
174#endif
Scott Wood82125192013-05-15 17:50:13 -0500175#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
176 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
177#endif
Kumar Gala1d2c2a62011-01-13 01:54:01 -0600178
Kumar Gala6aba33e2009-03-19 03:40:08 -0500179 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
180 /* Read back to sync write */
181 in_be32(&cpc->cpccsr0);
182
183 }
184
185 printf("Corenet Platform Cache: %d KB enabled\n", size);
186}
187
Kim Phillipse56143e2012-10-29 13:34:38 +0000188static void invalidate_cpc(void)
Kumar Gala6aba33e2009-03-19 03:40:08 -0500189{
190 int i;
191 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
192
193 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
Shaohui Xie2a9fab82011-03-16 10:10:32 +0800194 /* skip CPC when it used as all SRAM */
195 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
196 continue;
Kumar Gala6aba33e2009-03-19 03:40:08 -0500197 /* Flash invalidate the CPC and clear all the locks */
198 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
199 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
200 ;
201 }
202}
203#else
204#define enable_cpc()
205#define invalidate_cpc()
206#endif /* CONFIG_SYS_FSL_CPC */
207
wdenk42d1f032003-10-15 23:53:47 +0000208/*
209 * Breathe some life into the CPU...
210 *
211 * Set up the memory map
212 * initialize a bunch of registers
213 */
214
Kumar Gala3c2a67e2009-09-17 01:52:37 -0500215#ifdef CONFIG_FSL_CORENET
216static void corenet_tb_init(void)
217{
218 volatile ccsr_rcpm_t *rcpm =
219 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
220 volatile ccsr_pic_t *pic =
Kim Phillips680c6132010-08-09 18:39:57 -0500221 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
Kumar Gala3c2a67e2009-09-17 01:52:37 -0500222 u32 whoami = in_be32(&pic->whoami);
223
224 /* Enable the timebase register for this core */
225 out_be32(&rcpm->ctbenrl, (1 << whoami));
226}
227#endif
228
wdenk42d1f032003-10-15 23:53:47 +0000229void cpu_init_f (void)
230{
wdenk42d1f032003-10-15 23:53:47 +0000231 extern void m8560_cpm_reset (void);
Stephen Georgef110fe92011-07-20 09:47:26 -0500232#ifdef CONFIG_SYS_DCSRBAR_PHYS
233 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
234#endif
Ruchika Gupta7065b7d2010-12-15 17:02:08 +0000235#if defined(CONFIG_SECURE_BOOT)
236 struct law_entry law;
237#endif
Peter Tysera2cd50e2008-11-11 10:17:10 -0600238#ifdef CONFIG_MPC8548
239 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
240 uint svr = get_svr();
241
242 /*
243 * CPU2 errata workaround: A core hang possible while executing
244 * a msync instruction and a snoopable transaction from an I/O
245 * master tagged to make quick forward progress is present.
246 * Fixed in silicon rev 2.1.
247 */
248 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
249 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
250#endif
wdenk42d1f032003-10-15 23:53:47 +0000251
Kumar Gala87163182008-01-16 22:38:34 -0600252 disable_tlb(14);
253 disable_tlb(15);
254
Ruchika Gupta7065b7d2010-12-15 17:02:08 +0000255#if defined(CONFIG_SECURE_BOOT)
256 /* Disable the LAW created for NOR flash by the PBI commands */
257 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
258 if (law.index != -1)
259 disable_law(law.index);
260#endif
261
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500262#ifdef CONFIG_CPM2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
wdenk42d1f032003-10-15 23:53:47 +0000264#endif
265
Becky Brucef51cdaf2010-06-17 11:37:20 -0500266 init_early_memctl_regs();
wdenk42d1f032003-10-15 23:53:47 +0000267
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500268#if defined(CONFIG_CPM2)
wdenk42d1f032003-10-15 23:53:47 +0000269 m8560_cpm_reset();
270#endif
Andy Flemingda9d4612007-08-14 00:14:25 -0500271#ifdef CONFIG_QE
272 /* Config QE ioports */
273 config_qe_ioports();
274#endif
Peter Tyser79f43332009-06-30 17:15:47 -0500275#if defined(CONFIG_FSL_DMA)
276 dma_init();
277#endif
Kumar Gala3c2a67e2009-09-17 01:52:37 -0500278#ifdef CONFIG_FSL_CORENET
279 corenet_tb_init();
280#endif
Kumar Gala94e94112009-11-12 10:26:16 -0600281 init_used_tlb_cams();
Kumar Gala6aba33e2009-03-19 03:40:08 -0500282
283 /* Invalidate the CPC before DDR gets enabled */
284 invalidate_cpc();
Stephen Georgef110fe92011-07-20 09:47:26 -0500285
286 #ifdef CONFIG_SYS_DCSRBAR_PHYS
287 /* set DCSRCR so that DCSR space is 1G */
288 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
289 in_be32(&gur->dcsrcr);
290#endif
291
wdenk42d1f032003-10-15 23:53:47 +0000292}
293
Kumar Gala35079aa2010-12-15 03:50:47 -0600294/* Implement a dummy function for those platforms w/o SERDES */
295static void __fsl_serdes__init(void)
296{
297 return ;
298}
299__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500300
York Sun6d2b9da2012-10-08 07:44:08 +0000301#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
302int enable_cluster_l2(void)
303{
304 int i = 0;
305 u32 cluster;
306 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
307 struct ccsr_cluster_l2 __iomem *l2cache;
308
309 cluster = in_be32(&gur->tp_cluster[i].lower);
310 if (cluster & TP_CLUSTER_EOC)
311 return 0;
312
313 /* The first cache has already been set up, so skip it */
314 i++;
315
316 /* Look through the remaining clusters, and set up their caches */
317 do {
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000318 int j, cluster_valid = 0;
319
York Sun6d2b9da2012-10-08 07:44:08 +0000320 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000321
York Sun6d2b9da2012-10-08 07:44:08 +0000322 cluster = in_be32(&gur->tp_cluster[i].lower);
323
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000324 /* check that at least one core/accel is enabled in cluster */
325 for (j = 0; j < 4; j++) {
326 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
327 u32 type = in_be32(&gur->tp_ityp[idx]);
York Sun6d2b9da2012-10-08 07:44:08 +0000328
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000329 if (type & TP_ITYP_AV)
330 cluster_valid = 1;
331 }
York Sun6d2b9da2012-10-08 07:44:08 +0000332
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000333 if (cluster_valid) {
334 /* set stash ID to (cluster) * 2 + 32 + 1 */
335 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
336
337 printf("enable l2 for cluster %d %p\n", i, l2cache);
338
339 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
340 while ((in_be32(&l2cache->l2csr0)
341 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
342 ;
James Yang9cd95ac2013-03-25 07:40:03 +0000343 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000344 }
York Sun6d2b9da2012-10-08 07:44:08 +0000345 i++;
346 } while (!(cluster & TP_CLUSTER_EOC));
347
348 return 0;
349}
350#endif
351
wdenk42d1f032003-10-15 23:53:47 +0000352/*
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500353 * Initialize L2 as cache.
354 *
355 * The newer 8548, etc, parts have twice as much cache, but
356 * use the same bit-encoding as the older 8555, etc, parts.
357 *
wdenk42d1f032003-10-15 23:53:47 +0000358 */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500359int cpu_init_r(void)
wdenk42d1f032003-10-15 23:53:47 +0000360{
Timur Tabifbc20aa2011-11-21 17:10:23 -0600361 __maybe_unused u32 svr = get_svr();
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500362#ifdef CONFIG_SYS_LBC_LCRR
York Sun6d2b9da2012-10-08 07:44:08 +0000363 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
364#endif
365#ifdef CONFIG_L2_CACHE
366 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
367#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
368 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500369#endif
York Sunafbfdf52012-11-08 12:33:39 +0000370#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
York Sun2a5fcb82012-10-28 08:12:54 +0000371 extern int spin_table_compat;
372 const char *spin;
373#endif
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500374
York Sun5e23ab02012-05-07 07:26:47 +0000375#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
376 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
377 /*
York Sun57125f22012-08-08 18:04:53 +0000378 * CPU22 and NMG_CPU_A011 share the same workaround.
York Sun5e23ab02012-05-07 07:26:47 +0000379 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
380 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
York Sun57125f22012-08-08 18:04:53 +0000381 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
382 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
383 * be disabled by hwconfig with syntax:
384 *
385 * fsl_cpu_a011:disable
York Sun5e23ab02012-05-07 07:26:47 +0000386 */
York Sun57125f22012-08-08 18:04:53 +0000387 extern int enable_cpu_a011_workaround;
388#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
389 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
390#else
391 char buffer[HWCONFIG_BUFFER_SIZE];
392 char *buf = NULL;
393 int n, res;
394
395 n = getenv_f("hwconfig", buffer, sizeof(buffer));
396 if (n > 0)
397 buf = buffer;
398
399 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
400 if (res > 0)
401 enable_cpu_a011_workaround = 0;
402 else {
403 if (n >= HWCONFIG_BUFFER_SIZE) {
404 printf("fsl_cpu_a011 was not found. hwconfig variable "
405 "may be too long\n");
406 }
407 enable_cpu_a011_workaround =
408 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
409 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
410 }
411#endif
412 if (enable_cpu_a011_workaround) {
York Sun1e9ea852012-05-07 07:26:45 +0000413 flush_dcache();
414 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
415 sync();
416 }
Kumar Galafd3c9be2010-05-05 22:35:27 -0500417#endif
418
York Sunafbfdf52012-11-08 12:33:39 +0000419#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
York Sun2a5fcb82012-10-28 08:12:54 +0000420 spin = getenv("spin_table_compat");
421 if (spin && (*spin == 'n'))
422 spin_table_compat = 0;
423 else
424 spin_table_compat = 1;
425#endif
426
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200427 puts ("L2: ");
428
wdenk42d1f032003-10-15 23:53:47 +0000429#if defined(CONFIG_L2_CACHE)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500430 volatile uint cache_ctl;
Timur Tabifbc20aa2011-11-21 17:10:23 -0600431 uint ver;
Kumar Gala73f15a02008-07-14 14:07:00 -0500432 u32 l2siz_field;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500433
Kumar Galaf3e04bd2008-04-08 10:45:50 -0500434 ver = SVR_SOC_VER(svr);
wdenk42d1f032003-10-15 23:53:47 +0000435
436 asm("msync;isync");
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500437 cache_ctl = l2cache->l2ctl;
Mingkai Hu7da53352009-09-11 14:19:10 +0800438
439#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
440 if (cache_ctl & MPC85xx_L2CTL_L2E) {
441 /* Clear L2 SRAM memory-mapped base address */
442 out_be32(&l2cache->l2srbar0, 0x0);
443 out_be32(&l2cache->l2srbar1, 0x0);
444
445 /* set MBECCDIS=0, SBECCDIS=0 */
446 clrbits_be32(&l2cache->l2errdis,
447 (MPC85xx_L2ERRDIS_MBECC |
448 MPC85xx_L2ERRDIS_SBECC));
449
450 /* set L2E=0, L2SRAM=0 */
451 clrbits_be32(&l2cache->l2ctl,
452 (MPC85xx_L2CTL_L2E |
453 MPC85xx_L2CTL_L2SRAM_ENTIRE));
454 }
455#endif
456
Kumar Gala73f15a02008-07-14 14:07:00 -0500457 l2siz_field = (cache_ctl >> 28) & 0x3;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500458
Kumar Gala73f15a02008-07-14 14:07:00 -0500459 switch (l2siz_field) {
460 case 0x0:
461 printf(" unknown size (0x%08x)\n", cache_ctl);
462 return -1;
463 break;
464 case 0x1:
465 if (ver == SVR_8540 || ver == SVR_8560 ||
York Sun48f6a5c2012-07-06 17:10:33 -0500466 ver == SVR_8541 || ver == SVR_8555) {
Kumar Gala73f15a02008-07-14 14:07:00 -0500467 puts("128 KB ");
468 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
469 cache_ctl = 0xc4000000;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500470 } else {
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200471 puts("256 KB ");
Ed Swarthout29372ff2007-07-27 01:50:47 -0500472 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
473 }
474 break;
Kumar Gala73f15a02008-07-14 14:07:00 -0500475 case 0x2:
476 if (ver == SVR_8540 || ver == SVR_8560 ||
York Sun48f6a5c2012-07-06 17:10:33 -0500477 ver == SVR_8541 || ver == SVR_8555) {
Kumar Gala73f15a02008-07-14 14:07:00 -0500478 puts("256 KB ");
479 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
480 cache_ctl = 0xc8000000;
481 } else {
482 puts ("512 KB ");
483 /* set L2E=1, L2I=1, & L2SRAM=0 */
484 cache_ctl = 0xc0000000;
485 }
486 break;
487 case 0x3:
488 puts("1024 KB ");
489 /* set L2E=1, L2I=1, & L2SRAM=0 */
490 cache_ctl = 0xc0000000;
491 break;
Jon Loeligerd65cfe82005-07-25 10:58:39 -0500492 }
493
Mingkai Hu76b474e2009-08-18 15:37:15 +0800494 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200495 puts("already enabled");
Haiying Wang888279b2010-12-01 10:35:30 -0500496#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
Kumar Galae4c9a352011-11-09 09:56:41 -0600497 u32 l2srbar = l2cache->l2srbar0;
Mingkai Hu76b474e2009-08-18 15:37:15 +0800498 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
499 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200500 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
Ed Swarthout29372ff2007-07-27 01:50:47 -0500501 l2cache->l2srbar0 = l2srbar;
Scott Wood9a511bd2012-10-29 19:00:41 -0500502 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
Ed Swarthout29372ff2007-07-27 01:50:47 -0500503 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504#endif /* CONFIG_SYS_INIT_L2_ADDR */
Ed Swarthout29372ff2007-07-27 01:50:47 -0500505 puts("\n");
506 } else {
507 asm("msync;isync");
508 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
509 asm("msync;isync");
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200510 puts("enabled\n");
Ed Swarthout29372ff2007-07-27 01:50:47 -0500511 }
Kumar Gala1b3e4042009-03-19 09:16:10 -0500512#elif defined(CONFIG_BACKSIDE_L2_CACHE)
York Sun48f6a5c2012-07-06 17:10:33 -0500513 if (SVR_SOC_VER(svr) == SVR_P2040) {
Kumar Galaacf3f8d2011-07-21 00:20:21 -0500514 puts("N/A\n");
515 goto skip_l2;
516 }
517
Kumar Gala1b3e4042009-03-19 09:16:10 -0500518 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
519
520 /* invalidate the L2 cache */
Kumar Gala25bacf72009-09-22 15:45:44 -0500521 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
522 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
Kumar Gala1b3e4042009-03-19 09:16:10 -0500523 ;
524
Kumar Gala82fd1f82009-03-19 02:53:01 -0500525#ifdef CONFIG_SYS_CACHE_STASHING
526 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
527 mtspr(SPRN_L2CSR1, (32 + 1));
528#endif
529
Kumar Gala1b3e4042009-03-19 09:16:10 -0500530 /* enable the cache */
531 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
532
Dave Liu654ea1f2009-10-22 00:10:23 -0500533 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
534 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
535 ;
Kumar Gala1b3e4042009-03-19 09:16:10 -0500536 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
Dave Liu654ea1f2009-10-22 00:10:23 -0500537 }
Kumar Galaacf3f8d2011-07-21 00:20:21 -0500538
539skip_l2:
York Sun6d2b9da2012-10-08 07:44:08 +0000540#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
541 if (l2cache->l2csr0 & L2CSR0_L2E)
542 printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64);
543
544 enable_cluster_l2();
wdenk42d1f032003-10-15 23:53:47 +0000545#else
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200546 puts("disabled\n");
wdenk42d1f032003-10-15 23:53:47 +0000547#endif
Kumar Gala6aba33e2009-03-19 03:40:08 -0500548
549 enable_cpc();
550
Kumar Galaaf025062010-05-22 13:21:39 -0500551 /* needs to be in ram since code uses global static vars */
552 fsl_serdes_init();
Kumar Galaaf025062010-05-22 13:21:39 -0500553
Shengzhou Liu72bd83c2013-01-23 19:56:23 +0000554#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
555 if (IS_SVR_REV(svr, 1, 0)) {
556 int i;
557 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
558
559 for (i = 0; i < 12; i++) {
560 p += i + (i > 5 ? 11 : 0);
561 out_be32(p, 0x2);
562 }
563 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
564 out_be32(p, 0x34);
565 }
566#endif
567
Kumar Galaa09b9b62010-12-30 12:09:53 -0600568#ifdef CONFIG_SYS_SRIO
569 srio_init();
Liu Gangc8b28152013-05-07 16:30:46 +0800570#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
Liu Gangff65f122012-08-09 05:09:59 +0000571 char *s = getenv("bootmaster");
572 if (s) {
573 if (!strcmp(s, "SRIO1")) {
574 srio_boot_master(1);
575 srio_boot_master_release_slave(1);
576 }
577 if (!strcmp(s, "SRIO2")) {
578 srio_boot_master(2);
579 srio_boot_master_release_slave(2);
580 }
581 }
Liu Gang5ffa88e2012-03-08 00:33:17 +0000582#endif
Kumar Galaa09b9b62010-12-30 12:09:53 -0600583#endif
584
Kumar Galaec2b74f2008-01-17 16:48:33 -0600585#if defined(CONFIG_MP)
586 setup_mp();
587#endif
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500588
Zang Roy-R619114e0be342012-09-18 09:50:08 +0000589#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
Roy Zangae026ff2011-01-07 00:24:27 -0600590 {
Zang Roy-R619114e0be342012-09-18 09:50:08 +0000591 if (SVR_MAJ(svr) < 3) {
592 void *p;
593 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
594 setbits_be32(p, 1 << (31 - 14));
595 }
Roy Zangae026ff2011-01-07 00:24:27 -0600596 }
597#endif
598
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500599#ifdef CONFIG_SYS_LBC_LCRR
600 /*
601 * Modify the CLKDIV field of LCRR register to improve the writing
602 * speed for NOR flash.
603 */
604 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
605 __raw_readl(&lbc->lcrr);
606 isync();
Kumar Gala2b3a1cd2011-10-03 08:37:57 -0500607#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
608 udelay(100);
609#endif
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500610#endif
611
Roy Zang86221f02011-04-13 00:08:51 -0500612#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
613 {
614 ccsr_usb_phy_t *usb_phy1 =
615 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
616 out_be32(&usb_phy1->usb_enable_override,
617 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
618 }
619#endif
620#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
621 {
622 ccsr_usb_phy_t *usb_phy2 =
623 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
624 out_be32(&usb_phy2->usb_enable_override,
625 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
626 }
627#endif
628
Xulei99d7b0a2013-03-11 17:56:34 +0000629#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
630 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
631 * multi-bit ECC errors which has impact on performance, so software
632 * should disable all ECC reporting from USB1 and USB2.
633 */
634 if (IS_SVR_REV(get_svr(), 1, 0)) {
635 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
636 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
637 setbits_be32(&dcfg->ecccr1,
638 (DCSR_DCFG_ECC_DISABLE_USB1 |
639 DCSR_DCFG_ECC_DISABLE_USB2));
640 }
641#endif
642
Roy Zang3fa75c82013-03-25 07:39:33 +0000643#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
644 ccsr_usb_phy_t *usb_phy =
645 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
646 setbits_be32(&usb_phy->pllprg[1],
647 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
648 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
649 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
650 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
651 setbits_be32(&usb_phy->port1.ctrl,
652 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
653 setbits_be32(&usb_phy->port1.drvvbuscfg,
654 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
655 setbits_be32(&usb_phy->port1.pwrfltcfg,
656 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
657 setbits_be32(&usb_phy->port2.ctrl,
658 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
659 setbits_be32(&usb_phy->port2.drvvbuscfg,
660 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
661 setbits_be32(&usb_phy->port2.pwrfltcfg,
662 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
663#endif
664
Kumar Galac916d7c2011-04-13 08:37:44 -0500665#ifdef CONFIG_FMAN_ENET
666 fman_enet_init();
667#endif
668
Timur Tabifbc20aa2011-11-21 17:10:23 -0600669#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
670 /*
671 * For P1022/1013 Rev1.0 silicon, after power on SATA host
672 * controller is configured in legacy mode instead of the
673 * expected enterprise mode. Software needs to clear bit[28]
674 * of HControl register to change to enterprise mode from
675 * legacy mode. We assume that the controller is offline.
676 */
677 if (IS_SVR_REV(svr, 1, 0) &&
678 ((SVR_SOC_VER(svr) == SVR_P1022) ||
York Sun48f6a5c2012-07-06 17:10:33 -0500679 (SVR_SOC_VER(svr) == SVR_P1013))) {
Timur Tabifbc20aa2011-11-21 17:10:23 -0600680 fsl_sata_reg_t *reg;
681
682 /* first SATA controller */
683 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
684 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
685
686 /* second SATA controller */
687 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
688 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
689 }
690#endif
691
692
wdenk42d1f032003-10-15 23:53:47 +0000693 return 0;
694}
Kumar Gala26f4cdba2009-08-14 13:37:54 -0500695
696extern void setup_ivors(void);
697
698void arch_preboot_os(void)
699{
Kumar Gala15fba322009-09-11 15:28:41 -0500700 u32 msr;
701
702 /*
703 * We are changing interrupt offsets and are about to boot the OS so
704 * we need to make sure we disable all async interrupts. EE is already
705 * disabled by the time we get called.
706 */
707 msr = mfmsr();
Prabhakar Kushwaha5344f7a2012-04-29 23:56:30 +0000708 msr &= ~(MSR_ME|MSR_CE);
Kumar Gala15fba322009-09-11 15:28:41 -0500709 mtmsr(msr);
710
Kumar Gala26f4cdba2009-08-14 13:37:54 -0500711 setup_ivors();
712}
Kumar Galaf54fe872010-04-20 10:21:25 -0500713
714#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
715int sata_initialize(void)
716{
717 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
718 return __sata_initialize();
719
720 return 1;
721}
722#endif
Kumar Galaf9a33f12011-02-02 11:23:50 -0600723
724void cpu_secondary_init_r(void)
725{
726#ifdef CONFIG_QE
727 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
Timur Tabif2717b42011-11-22 09:21:25 -0600728#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
Haiying Wanga7b1e1b2011-02-07 16:14:15 -0500729 int ret;
Timur Tabif2717b42011-11-22 09:21:25 -0600730 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
Haiying Wanga7b1e1b2011-02-07 16:14:15 -0500731
732 /* load QE firmware from NAND flash to DDR first */
Timur Tabif2717b42011-11-22 09:21:25 -0600733 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
734 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
Haiying Wanga7b1e1b2011-02-07 16:14:15 -0500735
736 if (ret && ret == -EUCLEAN) {
737 printf ("NAND read for QE firmware at offset %x failed %d\n",
Timur Tabif2717b42011-11-22 09:21:25 -0600738 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
Haiying Wanga7b1e1b2011-02-07 16:14:15 -0500739 }
740#endif
Kumar Galaf9a33f12011-02-02 11:23:50 -0600741 qe_init(qe_base);
742 qe_reset();
743#endif
744}