blob: 941c20e00a58f2994d5859ca5cb4321ba249836d [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
Kumar Galaa09b9b62010-12-30 12:09:53 -06002 * Copyright 2007-2011 Freescale Semiconductor, Inc.
Ed Swarthout29372ff2007-07-27 01:50:47 -05003 *
wdenk42d1f032003-10-15 23:53:47 +00004 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +000011 */
12
13#include <common.h>
14#include <watchdog.h>
15#include <asm/processor.h>
16#include <ioports.h>
Kumar Galaf54fe872010-04-20 10:21:25 -050017#include <sata.h>
Kumar Galac916d7c2011-04-13 08:37:44 -050018#include <fm_eth.h>
wdenk42d1f032003-10-15 23:53:47 +000019#include <asm/io.h>
Kumar Galafd3c9be2010-05-05 22:35:27 -050020#include <asm/cache.h>
Kumar Gala87163182008-01-16 22:38:34 -060021#include <asm/mmu.h>
York Sun133fbfa2013-09-16 12:49:31 -070022#include <asm/fsl_errata.h>
Kumar Gala83d40df2008-01-16 01:13:58 -060023#include <asm/fsl_law.h>
Kumar Galaf54fe872010-04-20 10:21:25 -050024#include <asm/fsl_serdes.h>
Liu Gang5ffa88e2012-03-08 00:33:17 +000025#include <asm/fsl_srio.h>
ramneek mehresh9dee2052013-08-05 16:00:16 +053026#include <fsl_usb.h>
York Sun57125f22012-08-08 18:04:53 +000027#include <hwconfig.h>
Timur Tabifbc20aa2011-11-21 17:10:23 -060028#include <linux/compiler.h>
Kumar Galaec2b74f2008-01-17 16:48:33 -060029#include "mp.h"
Timur Tabif2717b42011-11-22 09:21:25 -060030#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
Haiying Wanga7b1e1b2011-02-07 16:14:15 -050031#include <nand.h>
32#include <errno.h>
33#endif
wdenk42d1f032003-10-15 23:53:47 +000034
Timur Tabifbc20aa2011-11-21 17:10:23 -060035#include "../../../../drivers/block/fsl_sata.h"
Zhao Qiang2a44efe2014-03-21 16:21:45 +080036#ifdef CONFIG_U_QE
37#include "../../../../drivers/qe/qe.h"
38#endif
Timur Tabifbc20aa2011-11-21 17:10:23 -060039
Wolfgang Denkd87080b2006-03-31 18:32:53 +020040DECLARE_GLOBAL_DATA_PTR;
41
Suresh Gupta9c641a82014-02-26 14:29:12 +053042#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
43void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
44{
45#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
46 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
47
48 /* Increase Disconnect Threshold by 50mV */
49 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
50 INC_DCNT_THRESHOLD_50MV;
51 /* Enable programming of USB High speed Disconnect threshold */
52 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
53 out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
54
55 xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
56 /* Increase Disconnect Threshold by 50mV */
57 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
58 INC_DCNT_THRESHOLD_50MV;
59 /* Enable programming of USB High speed Disconnect threshold */
60 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
61 out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
62#else
63
64 u32 temp = 0;
65 u32 status = in_be32(&usb_phy->status1);
66
67 u32 squelch_prog_rd_0_2 =
68 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
69 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
70
71 u32 squelch_prog_rd_3_5 =
72 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
73 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
74
75 setbits_be32(&usb_phy->config1,
76 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
77 setbits_be32(&usb_phy->config2,
78 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
79
80 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
81 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
82
83 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
84 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
85#endif
86}
87#endif
88
89
Zhao Qiang2a44efe2014-03-21 16:21:45 +080090#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
Andy Flemingda9d4612007-08-14 00:14:25 -050091extern qe_iop_conf_t qe_iop_conf_tab[];
92extern void qe_config_iopin(u8 port, u8 pin, int dir,
93 int open_drain, int assign);
94extern void qe_init(uint qe_base);
95extern void qe_reset(void);
96
97static void config_qe_ioports(void)
98{
99 u8 port, pin;
100 int dir, open_drain, assign;
101 int i;
102
103 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
104 port = qe_iop_conf_tab[i].port;
105 pin = qe_iop_conf_tab[i].pin;
106 dir = qe_iop_conf_tab[i].dir;
107 open_drain = qe_iop_conf_tab[i].open_drain;
108 assign = qe_iop_conf_tab[i].assign;
109 qe_config_iopin(port, pin, dir, open_drain, assign);
110 }
111}
112#endif
Matthew McClintock40d5fa32006-06-28 10:43:36 -0500113
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500114#ifdef CONFIG_CPM2
Kumar Galaaafeefb2007-11-28 00:36:33 -0600115void config_8560_ioports (volatile ccsr_cpm_t * cpm)
wdenk42d1f032003-10-15 23:53:47 +0000116{
117 int portnum;
118
119 for (portnum = 0; portnum < 4; portnum++) {
120 uint pmsk = 0,
121 ppar = 0,
122 psor = 0,
123 pdir = 0,
124 podr = 0,
125 pdat = 0;
126 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
127 iop_conf_t *eiopc = iopc + 32;
128 uint msk = 1;
129
130 /*
131 * NOTE:
132 * index 0 refers to pin 31,
133 * index 31 refers to pin 0
134 */
135 while (iopc < eiopc) {
136 if (iopc->conf) {
137 pmsk |= msk;
138 if (iopc->ppar)
139 ppar |= msk;
140 if (iopc->psor)
141 psor |= msk;
142 if (iopc->pdir)
143 pdir |= msk;
144 if (iopc->podr)
145 podr |= msk;
146 if (iopc->pdat)
147 pdat |= msk;
148 }
149
150 msk <<= 1;
151 iopc++;
152 }
153
154 if (pmsk != 0) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600155 volatile ioport_t *iop = ioport_addr (cpm, portnum);
wdenk42d1f032003-10-15 23:53:47 +0000156 uint tpmsk = ~pmsk;
157
158 /*
159 * the (somewhat confused) paragraph at the
160 * bottom of page 35-5 warns that there might
161 * be "unknown behaviour" when programming
162 * PSORx and PDIRx, if PPARx = 1, so I
163 * decided this meant I had to disable the
164 * dedicated function first, and enable it
165 * last.
166 */
167 iop->ppar &= tpmsk;
168 iop->psor = (iop->psor & tpmsk) | psor;
169 iop->podr = (iop->podr & tpmsk) | podr;
170 iop->pdat = (iop->pdat & tpmsk) | pdat;
171 iop->pdir = (iop->pdir & tpmsk) | pdir;
172 iop->ppar |= ppar;
173 }
174 }
175}
176#endif
177
Kumar Gala6aba33e2009-03-19 03:40:08 -0500178#ifdef CONFIG_SYS_FSL_CPC
Aneesh Bansalfb4a2402014-03-18 23:40:26 +0530179#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
180static void disable_cpc_sram(void)
Kumar Gala6aba33e2009-03-19 03:40:08 -0500181{
182 int i;
Kumar Gala6aba33e2009-03-19 03:40:08 -0500183
184 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
185
186 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
Shaohui Xie2a9fab82011-03-16 10:10:32 +0800187 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
188 /* find and disable LAW of SRAM */
189 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
190
191 if (law.index == -1) {
192 printf("\nFatal error happened\n");
193 return;
194 }
195 disable_law(law.index);
196
197 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
198 out_be32(&cpc->cpccsr0, 0);
199 out_be32(&cpc->cpcsrcr0, 0);
200 }
Aneesh Bansalfb4a2402014-03-18 23:40:26 +0530201 }
202}
Shaohui Xie2a9fab82011-03-16 10:10:32 +0800203#endif
Kumar Gala6aba33e2009-03-19 03:40:08 -0500204
Aneesh Bansalfb4a2402014-03-18 23:40:26 +0530205static void enable_cpc(void)
206{
207 int i;
208 u32 size = 0;
209
210 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
211
212 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
213 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
214 size += CPC_CFG0_SZ_K(cpccfg0);
215
Kumar Gala1d2c2a62011-01-13 01:54:01 -0600216#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
217 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
218#endif
Kumar Gala868da592011-01-13 01:56:18 -0600219#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
220 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
221#endif
Scott Wood82125192013-05-15 17:50:13 -0500222#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
223 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
224#endif
York Sun133fbfa2013-09-16 12:49:31 -0700225#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
226 if (has_erratum_a006379()) {
227 setbits_be32(&cpc->cpchdbcr0,
228 CPC_HDBCR0_SPLRU_LEVEL_EN);
229 }
230#endif
Kumar Gala1d2c2a62011-01-13 01:54:01 -0600231
Kumar Gala6aba33e2009-03-19 03:40:08 -0500232 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
233 /* Read back to sync write */
234 in_be32(&cpc->cpccsr0);
235
236 }
237
Shruti Kanetkar2f848f92013-08-15 11:25:37 -0500238 puts("Corenet Platform Cache: ");
239 print_size(size * 1024, " enabled\n");
Kumar Gala6aba33e2009-03-19 03:40:08 -0500240}
241
Kim Phillipse56143e2012-10-29 13:34:38 +0000242static void invalidate_cpc(void)
Kumar Gala6aba33e2009-03-19 03:40:08 -0500243{
244 int i;
245 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
246
247 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
Shaohui Xie2a9fab82011-03-16 10:10:32 +0800248 /* skip CPC when it used as all SRAM */
249 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
250 continue;
Kumar Gala6aba33e2009-03-19 03:40:08 -0500251 /* Flash invalidate the CPC and clear all the locks */
252 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
253 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
254 ;
255 }
256}
257#else
258#define enable_cpc()
259#define invalidate_cpc()
260#endif /* CONFIG_SYS_FSL_CPC */
261
wdenk42d1f032003-10-15 23:53:47 +0000262/*
263 * Breathe some life into the CPU...
264 *
265 * Set up the memory map
266 * initialize a bunch of registers
267 */
268
Kumar Gala3c2a67e2009-09-17 01:52:37 -0500269#ifdef CONFIG_FSL_CORENET
270static void corenet_tb_init(void)
271{
272 volatile ccsr_rcpm_t *rcpm =
273 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
274 volatile ccsr_pic_t *pic =
Kim Phillips680c6132010-08-09 18:39:57 -0500275 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
Kumar Gala3c2a67e2009-09-17 01:52:37 -0500276 u32 whoami = in_be32(&pic->whoami);
277
278 /* Enable the timebase register for this core */
279 out_be32(&rcpm->ctbenrl, (1 << whoami));
280}
281#endif
282
York Sunc3678b02014-03-28 15:07:27 -0700283#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
284void fsl_erratum_a007212_workaround(void)
285{
286 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
287 u32 ddr_pll_ratio;
288 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
289 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
290 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
291#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
292 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
293 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
294#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
295 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
296 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
297#endif
298#endif
299 /*
300 * Even this workaround applies to selected version of SoCs, it is
301 * safe to apply to all versions, with the limitation of odd ratios.
302 * If RCW has disabled DDR PLL, we have to apply this workaround,
303 * otherwise DDR will not work.
304 */
305 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
306 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
307 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
308 /* check if RCW sets ratio to 0, required by this workaround */
309 if (ddr_pll_ratio != 0)
310 return;
311 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
312 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
313 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
314 /* check if reserved bits have the desired ratio */
315 if (ddr_pll_ratio == 0) {
316 printf("Error: Unknown DDR PLL ratio!\n");
317 return;
318 }
319 ddr_pll_ratio >>= 1;
320
321 setbits_be32(plldadcr1, 0x02000001);
322#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
323 setbits_be32(plldadcr2, 0x02000001);
324#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
325 setbits_be32(plldadcr3, 0x02000001);
326#endif
327#endif
328 setbits_be32(dpdovrcr4, 0xe0000000);
329 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
330#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
331 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
332#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
333 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
334#endif
335#endif
336 udelay(100);
337 clrbits_be32(plldadcr1, 0x02000001);
338#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
339 clrbits_be32(plldadcr2, 0x02000001);
340#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
341 clrbits_be32(plldadcr3, 0x02000001);
342#endif
343#endif
344 clrbits_be32(dpdovrcr4, 0xe0000000);
345}
346#endif
347
wdenk42d1f032003-10-15 23:53:47 +0000348void cpu_init_f (void)
349{
wdenk42d1f032003-10-15 23:53:47 +0000350 extern void m8560_cpm_reset (void);
Stephen Georgef110fe92011-07-20 09:47:26 -0500351#ifdef CONFIG_SYS_DCSRBAR_PHYS
352 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
353#endif
Ruchika Gupta7065b7d2010-12-15 17:02:08 +0000354#if defined(CONFIG_SECURE_BOOT)
355 struct law_entry law;
356#endif
Peter Tysera2cd50e2008-11-11 10:17:10 -0600357#ifdef CONFIG_MPC8548
358 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
359 uint svr = get_svr();
360
361 /*
362 * CPU2 errata workaround: A core hang possible while executing
363 * a msync instruction and a snoopable transaction from an I/O
364 * master tagged to make quick forward progress is present.
365 * Fixed in silicon rev 2.1.
366 */
367 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
368 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
369#endif
wdenk42d1f032003-10-15 23:53:47 +0000370
Kumar Gala87163182008-01-16 22:38:34 -0600371 disable_tlb(14);
372 disable_tlb(15);
373
Ruchika Gupta7065b7d2010-12-15 17:02:08 +0000374#if defined(CONFIG_SECURE_BOOT)
375 /* Disable the LAW created for NOR flash by the PBI commands */
376 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
377 if (law.index != -1)
378 disable_law(law.index);
Aneesh Bansalfb4a2402014-03-18 23:40:26 +0530379
380#if defined(CONFIG_SYS_CPC_REINIT_F)
381 disable_cpc_sram();
382#endif
Ruchika Gupta7065b7d2010-12-15 17:02:08 +0000383#endif
384
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500385#ifdef CONFIG_CPM2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
wdenk42d1f032003-10-15 23:53:47 +0000387#endif
388
Becky Brucef51cdaf2010-06-17 11:37:20 -0500389 init_early_memctl_regs();
wdenk42d1f032003-10-15 23:53:47 +0000390
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500391#if defined(CONFIG_CPM2)
wdenk42d1f032003-10-15 23:53:47 +0000392 m8560_cpm_reset();
393#endif
Zhao Qiang2a44efe2014-03-21 16:21:45 +0800394
395#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
Andy Flemingda9d4612007-08-14 00:14:25 -0500396 /* Config QE ioports */
397 config_qe_ioports();
398#endif
Zhao Qiang2a44efe2014-03-21 16:21:45 +0800399
Peter Tyser79f43332009-06-30 17:15:47 -0500400#if defined(CONFIG_FSL_DMA)
401 dma_init();
402#endif
Kumar Gala3c2a67e2009-09-17 01:52:37 -0500403#ifdef CONFIG_FSL_CORENET
404 corenet_tb_init();
405#endif
Kumar Gala94e94112009-11-12 10:26:16 -0600406 init_used_tlb_cams();
Kumar Gala6aba33e2009-03-19 03:40:08 -0500407
408 /* Invalidate the CPC before DDR gets enabled */
409 invalidate_cpc();
Stephen Georgef110fe92011-07-20 09:47:26 -0500410
411 #ifdef CONFIG_SYS_DCSRBAR_PHYS
412 /* set DCSRCR so that DCSR space is 1G */
413 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
414 in_be32(&gur->dcsrcr);
415#endif
416
York Sunc3678b02014-03-28 15:07:27 -0700417#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
418 fsl_erratum_a007212_workaround();
419#endif
420
wdenk42d1f032003-10-15 23:53:47 +0000421}
422
Kumar Gala35079aa2010-12-15 03:50:47 -0600423/* Implement a dummy function for those platforms w/o SERDES */
424static void __fsl_serdes__init(void)
425{
426 return ;
427}
428__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500429
Prabhakar Kushwahae9827462013-08-29 13:10:38 +0530430#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
York Sun6d2b9da2012-10-08 07:44:08 +0000431int enable_cluster_l2(void)
432{
433 int i = 0;
434 u32 cluster;
435 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
436 struct ccsr_cluster_l2 __iomem *l2cache;
437
438 cluster = in_be32(&gur->tp_cluster[i].lower);
439 if (cluster & TP_CLUSTER_EOC)
440 return 0;
441
442 /* The first cache has already been set up, so skip it */
443 i++;
444
445 /* Look through the remaining clusters, and set up their caches */
446 do {
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000447 int j, cluster_valid = 0;
448
York Sun6d2b9da2012-10-08 07:44:08 +0000449 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000450
York Sun6d2b9da2012-10-08 07:44:08 +0000451 cluster = in_be32(&gur->tp_cluster[i].lower);
452
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000453 /* check that at least one core/accel is enabled in cluster */
454 for (j = 0; j < 4; j++) {
455 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
456 u32 type = in_be32(&gur->tp_ityp[idx]);
York Sun6d2b9da2012-10-08 07:44:08 +0000457
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000458 if (type & TP_ITYP_AV)
459 cluster_valid = 1;
460 }
York Sun6d2b9da2012-10-08 07:44:08 +0000461
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000462 if (cluster_valid) {
463 /* set stash ID to (cluster) * 2 + 32 + 1 */
464 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
465
466 printf("enable l2 for cluster %d %p\n", i, l2cache);
467
468 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
469 while ((in_be32(&l2cache->l2csr0)
470 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
471 ;
James Yang9cd95ac2013-03-25 07:40:03 +0000472 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000473 }
York Sun6d2b9da2012-10-08 07:44:08 +0000474 i++;
475 } while (!(cluster & TP_CLUSTER_EOC));
476
477 return 0;
478}
479#endif
480
wdenk42d1f032003-10-15 23:53:47 +0000481/*
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500482 * Initialize L2 as cache.
483 *
484 * The newer 8548, etc, parts have twice as much cache, but
485 * use the same bit-encoding as the older 8555, etc, parts.
486 *
wdenk42d1f032003-10-15 23:53:47 +0000487 */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500488int cpu_init_r(void)
wdenk42d1f032003-10-15 23:53:47 +0000489{
Timur Tabifbc20aa2011-11-21 17:10:23 -0600490 __maybe_unused u32 svr = get_svr();
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500491#ifdef CONFIG_SYS_LBC_LCRR
York Sun6d2b9da2012-10-08 07:44:08 +0000492 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
493#endif
494#ifdef CONFIG_L2_CACHE
495 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
Prabhakar Kushwahae9827462013-08-29 13:10:38 +0530496#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
York Sun6d2b9da2012-10-08 07:44:08 +0000497 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500498#endif
York Sunafbfdf52012-11-08 12:33:39 +0000499#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
York Sun2a5fcb82012-10-28 08:12:54 +0000500 extern int spin_table_compat;
501 const char *spin;
502#endif
Shengzhou Liu424bf942013-08-15 09:31:47 +0800503#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
504 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
505#endif
York Sun5e23ab02012-05-07 07:26:47 +0000506#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
507 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
508 /*
York Sun57125f22012-08-08 18:04:53 +0000509 * CPU22 and NMG_CPU_A011 share the same workaround.
York Sun5e23ab02012-05-07 07:26:47 +0000510 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
511 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
York Sun57125f22012-08-08 18:04:53 +0000512 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
513 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
514 * be disabled by hwconfig with syntax:
515 *
516 * fsl_cpu_a011:disable
York Sun5e23ab02012-05-07 07:26:47 +0000517 */
York Sun57125f22012-08-08 18:04:53 +0000518 extern int enable_cpu_a011_workaround;
519#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
520 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
521#else
522 char buffer[HWCONFIG_BUFFER_SIZE];
523 char *buf = NULL;
524 int n, res;
525
526 n = getenv_f("hwconfig", buffer, sizeof(buffer));
527 if (n > 0)
528 buf = buffer;
529
530 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
531 if (res > 0)
532 enable_cpu_a011_workaround = 0;
533 else {
534 if (n >= HWCONFIG_BUFFER_SIZE) {
535 printf("fsl_cpu_a011 was not found. hwconfig variable "
536 "may be too long\n");
537 }
538 enable_cpu_a011_workaround =
539 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
540 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
541 }
542#endif
543 if (enable_cpu_a011_workaround) {
York Sun1e9ea852012-05-07 07:26:45 +0000544 flush_dcache();
545 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
546 sync();
547 }
Kumar Galafd3c9be2010-05-05 22:35:27 -0500548#endif
York Sund217a9a2013-06-25 11:37:49 -0700549#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
550 /*
551 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
552 * in write shadow mode. Checking DCWS before setting SPR 976.
553 */
554 if (mfspr(L1CSR2) & L1CSR2_DCWS)
555 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
556#endif
Kumar Galafd3c9be2010-05-05 22:35:27 -0500557
York Sunafbfdf52012-11-08 12:33:39 +0000558#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
York Sun2a5fcb82012-10-28 08:12:54 +0000559 spin = getenv("spin_table_compat");
560 if (spin && (*spin == 'n'))
561 spin_table_compat = 0;
562 else
563 spin_table_compat = 1;
564#endif
565
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200566 puts ("L2: ");
567
wdenk42d1f032003-10-15 23:53:47 +0000568#if defined(CONFIG_L2_CACHE)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500569 volatile uint cache_ctl;
Timur Tabifbc20aa2011-11-21 17:10:23 -0600570 uint ver;
Kumar Gala73f15a02008-07-14 14:07:00 -0500571 u32 l2siz_field;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500572
Kumar Galaf3e04bd2008-04-08 10:45:50 -0500573 ver = SVR_SOC_VER(svr);
wdenk42d1f032003-10-15 23:53:47 +0000574
575 asm("msync;isync");
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500576 cache_ctl = l2cache->l2ctl;
Mingkai Hu7da53352009-09-11 14:19:10 +0800577
578#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
579 if (cache_ctl & MPC85xx_L2CTL_L2E) {
580 /* Clear L2 SRAM memory-mapped base address */
581 out_be32(&l2cache->l2srbar0, 0x0);
582 out_be32(&l2cache->l2srbar1, 0x0);
583
584 /* set MBECCDIS=0, SBECCDIS=0 */
585 clrbits_be32(&l2cache->l2errdis,
586 (MPC85xx_L2ERRDIS_MBECC |
587 MPC85xx_L2ERRDIS_SBECC));
588
589 /* set L2E=0, L2SRAM=0 */
590 clrbits_be32(&l2cache->l2ctl,
591 (MPC85xx_L2CTL_L2E |
592 MPC85xx_L2CTL_L2SRAM_ENTIRE));
593 }
594#endif
595
Kumar Gala73f15a02008-07-14 14:07:00 -0500596 l2siz_field = (cache_ctl >> 28) & 0x3;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500597
Kumar Gala73f15a02008-07-14 14:07:00 -0500598 switch (l2siz_field) {
599 case 0x0:
600 printf(" unknown size (0x%08x)\n", cache_ctl);
601 return -1;
602 break;
603 case 0x1:
604 if (ver == SVR_8540 || ver == SVR_8560 ||
York Sun48f6a5c2012-07-06 17:10:33 -0500605 ver == SVR_8541 || ver == SVR_8555) {
Shruti Kanetkar6b44d9e2013-08-15 11:25:38 -0500606 puts("128 KiB ");
607 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
Kumar Gala73f15a02008-07-14 14:07:00 -0500608 cache_ctl = 0xc4000000;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500609 } else {
Shruti Kanetkar6b44d9e2013-08-15 11:25:38 -0500610 puts("256 KiB ");
Ed Swarthout29372ff2007-07-27 01:50:47 -0500611 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
612 }
613 break;
Kumar Gala73f15a02008-07-14 14:07:00 -0500614 case 0x2:
615 if (ver == SVR_8540 || ver == SVR_8560 ||
York Sun48f6a5c2012-07-06 17:10:33 -0500616 ver == SVR_8541 || ver == SVR_8555) {
Shruti Kanetkar6b44d9e2013-08-15 11:25:38 -0500617 puts("256 KiB ");
618 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
Kumar Gala73f15a02008-07-14 14:07:00 -0500619 cache_ctl = 0xc8000000;
620 } else {
Shruti Kanetkar6b44d9e2013-08-15 11:25:38 -0500621 puts("512 KiB ");
Kumar Gala73f15a02008-07-14 14:07:00 -0500622 /* set L2E=1, L2I=1, & L2SRAM=0 */
623 cache_ctl = 0xc0000000;
624 }
625 break;
626 case 0x3:
Shruti Kanetkar6b44d9e2013-08-15 11:25:38 -0500627 puts("1024 KiB ");
Kumar Gala73f15a02008-07-14 14:07:00 -0500628 /* set L2E=1, L2I=1, & L2SRAM=0 */
629 cache_ctl = 0xc0000000;
630 break;
Jon Loeligerd65cfe82005-07-25 10:58:39 -0500631 }
632
Mingkai Hu76b474e2009-08-18 15:37:15 +0800633 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200634 puts("already enabled");
Haiying Wang888279b2010-12-01 10:35:30 -0500635#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
Kumar Galae4c9a352011-11-09 09:56:41 -0600636 u32 l2srbar = l2cache->l2srbar0;
Mingkai Hu76b474e2009-08-18 15:37:15 +0800637 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
638 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200639 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
Ed Swarthout29372ff2007-07-27 01:50:47 -0500640 l2cache->l2srbar0 = l2srbar;
Scott Wood9a511bd2012-10-29 19:00:41 -0500641 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
Ed Swarthout29372ff2007-07-27 01:50:47 -0500642 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200643#endif /* CONFIG_SYS_INIT_L2_ADDR */
Ed Swarthout29372ff2007-07-27 01:50:47 -0500644 puts("\n");
645 } else {
646 asm("msync;isync");
647 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
648 asm("msync;isync");
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200649 puts("enabled\n");
Ed Swarthout29372ff2007-07-27 01:50:47 -0500650 }
Kumar Gala1b3e4042009-03-19 09:16:10 -0500651#elif defined(CONFIG_BACKSIDE_L2_CACHE)
York Sun48f6a5c2012-07-06 17:10:33 -0500652 if (SVR_SOC_VER(svr) == SVR_P2040) {
Kumar Galaacf3f8d2011-07-21 00:20:21 -0500653 puts("N/A\n");
654 goto skip_l2;
655 }
656
Kumar Gala1b3e4042009-03-19 09:16:10 -0500657 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
658
659 /* invalidate the L2 cache */
Kumar Gala25bacf72009-09-22 15:45:44 -0500660 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
661 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
Kumar Gala1b3e4042009-03-19 09:16:10 -0500662 ;
663
Kumar Gala82fd1f82009-03-19 02:53:01 -0500664#ifdef CONFIG_SYS_CACHE_STASHING
665 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
666 mtspr(SPRN_L2CSR1, (32 + 1));
667#endif
668
Kumar Gala1b3e4042009-03-19 09:16:10 -0500669 /* enable the cache */
670 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
671
Dave Liu654ea1f2009-10-22 00:10:23 -0500672 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
673 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
674 ;
Shruti Kanetkar2f848f92013-08-15 11:25:37 -0500675 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
Dave Liu654ea1f2009-10-22 00:10:23 -0500676 }
Kumar Galaacf3f8d2011-07-21 00:20:21 -0500677
678skip_l2:
Prabhakar Kushwahae9827462013-08-29 13:10:38 +0530679#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
York Sun6d2b9da2012-10-08 07:44:08 +0000680 if (l2cache->l2csr0 & L2CSR0_L2E)
Shruti Kanetkar2f848f92013-08-15 11:25:37 -0500681 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
682 " enabled\n");
York Sun6d2b9da2012-10-08 07:44:08 +0000683
684 enable_cluster_l2();
wdenk42d1f032003-10-15 23:53:47 +0000685#else
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200686 puts("disabled\n");
wdenk42d1f032003-10-15 23:53:47 +0000687#endif
Kumar Gala6aba33e2009-03-19 03:40:08 -0500688
Aneesh Bansalfb4a2402014-03-18 23:40:26 +0530689#if defined(CONFIG_RAMBOOT_PBL)
690 disable_cpc_sram();
691#endif
Kumar Gala6aba33e2009-03-19 03:40:08 -0500692 enable_cpc();
693
York Suncb930712013-06-25 11:37:41 -0700694#ifndef CONFIG_SYS_FSL_NO_SERDES
Kumar Galaaf025062010-05-22 13:21:39 -0500695 /* needs to be in ram since code uses global static vars */
696 fsl_serdes_init();
York Suncb930712013-06-25 11:37:41 -0700697#endif
Kumar Galaaf025062010-05-22 13:21:39 -0500698
Shengzhou Liu424bf942013-08-15 09:31:47 +0800699#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
700#define MCFGR_AXIPIPE 0x000000f0
701 if (IS_SVR_REV(svr, 1, 0))
702 clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE);
703#endif
704
Shengzhou Liu72bd83c2013-01-23 19:56:23 +0000705#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
706 if (IS_SVR_REV(svr, 1, 0)) {
707 int i;
708 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
709
710 for (i = 0; i < 12; i++) {
711 p += i + (i > 5 ? 11 : 0);
712 out_be32(p, 0x2);
713 }
714 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
715 out_be32(p, 0x34);
716 }
717#endif
718
Kumar Galaa09b9b62010-12-30 12:09:53 -0600719#ifdef CONFIG_SYS_SRIO
720 srio_init();
Liu Gangc8b28152013-05-07 16:30:46 +0800721#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
Liu Gangff65f122012-08-09 05:09:59 +0000722 char *s = getenv("bootmaster");
723 if (s) {
724 if (!strcmp(s, "SRIO1")) {
725 srio_boot_master(1);
726 srio_boot_master_release_slave(1);
727 }
728 if (!strcmp(s, "SRIO2")) {
729 srio_boot_master(2);
730 srio_boot_master_release_slave(2);
731 }
732 }
Liu Gang5ffa88e2012-03-08 00:33:17 +0000733#endif
Kumar Galaa09b9b62010-12-30 12:09:53 -0600734#endif
735
Kumar Galaec2b74f2008-01-17 16:48:33 -0600736#if defined(CONFIG_MP)
737 setup_mp();
738#endif
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500739
Zang Roy-R619114e0be342012-09-18 09:50:08 +0000740#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
Roy Zangae026ff2011-01-07 00:24:27 -0600741 {
Zang Roy-R619114e0be342012-09-18 09:50:08 +0000742 if (SVR_MAJ(svr) < 3) {
743 void *p;
744 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
745 setbits_be32(p, 1 << (31 - 14));
746 }
Roy Zangae026ff2011-01-07 00:24:27 -0600747 }
748#endif
749
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500750#ifdef CONFIG_SYS_LBC_LCRR
751 /*
752 * Modify the CLKDIV field of LCRR register to improve the writing
753 * speed for NOR flash.
754 */
755 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
756 __raw_readl(&lbc->lcrr);
757 isync();
Kumar Gala2b3a1cd2011-10-03 08:37:57 -0500758#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
759 udelay(100);
760#endif
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500761#endif
762
Roy Zang86221f02011-04-13 00:08:51 -0500763#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
764 {
ramneek mehresh9dee2052013-08-05 16:00:16 +0530765 struct ccsr_usb_phy __iomem *usb_phy1 =
Roy Zang86221f02011-04-13 00:08:51 -0500766 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
Suresh Gupta9c641a82014-02-26 14:29:12 +0530767#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
768 if (has_erratum_a006261())
769 fsl_erratum_a006261_workaround(usb_phy1);
770#endif
Roy Zang86221f02011-04-13 00:08:51 -0500771 out_be32(&usb_phy1->usb_enable_override,
772 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
773 }
774#endif
775#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
776 {
ramneek mehresh9dee2052013-08-05 16:00:16 +0530777 struct ccsr_usb_phy __iomem *usb_phy2 =
Roy Zang86221f02011-04-13 00:08:51 -0500778 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
Suresh Gupta9c641a82014-02-26 14:29:12 +0530779#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
780 if (has_erratum_a006261())
781 fsl_erratum_a006261_workaround(usb_phy2);
782#endif
Roy Zang86221f02011-04-13 00:08:51 -0500783 out_be32(&usb_phy2->usb_enable_override,
784 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
785 }
786#endif
787
Xulei99d7b0a2013-03-11 17:56:34 +0000788#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
789 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
790 * multi-bit ECC errors which has impact on performance, so software
791 * should disable all ECC reporting from USB1 and USB2.
792 */
793 if (IS_SVR_REV(get_svr(), 1, 0)) {
794 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
795 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
796 setbits_be32(&dcfg->ecccr1,
797 (DCSR_DCFG_ECC_DISABLE_USB1 |
798 DCSR_DCFG_ECC_DISABLE_USB2));
799 }
800#endif
801
Roy Zang3fa75c82013-03-25 07:39:33 +0000802#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
ramneek mehresh9dee2052013-08-05 16:00:16 +0530803 struct ccsr_usb_phy __iomem *usb_phy =
Roy Zang3fa75c82013-03-25 07:39:33 +0000804 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
805 setbits_be32(&usb_phy->pllprg[1],
806 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
807 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
808 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
809 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
810 setbits_be32(&usb_phy->port1.ctrl,
811 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
812 setbits_be32(&usb_phy->port1.drvvbuscfg,
813 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
814 setbits_be32(&usb_phy->port1.pwrfltcfg,
815 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
816 setbits_be32(&usb_phy->port2.ctrl,
817 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
818 setbits_be32(&usb_phy->port2.drvvbuscfg,
819 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
820 setbits_be32(&usb_phy->port2.pwrfltcfg,
821 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
Suresh Gupta9c641a82014-02-26 14:29:12 +0530822
823#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
824 if (has_erratum_a006261())
825 fsl_erratum_a006261_workaround(usb_phy);
Roy Zang3fa75c82013-03-25 07:39:33 +0000826#endif
827
Suresh Gupta9c641a82014-02-26 14:29:12 +0530828#endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
829
Kumar Galac916d7c2011-04-13 08:37:44 -0500830#ifdef CONFIG_FMAN_ENET
831 fman_enet_init();
832#endif
833
Timur Tabifbc20aa2011-11-21 17:10:23 -0600834#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
835 /*
836 * For P1022/1013 Rev1.0 silicon, after power on SATA host
837 * controller is configured in legacy mode instead of the
838 * expected enterprise mode. Software needs to clear bit[28]
839 * of HControl register to change to enterprise mode from
840 * legacy mode. We assume that the controller is offline.
841 */
842 if (IS_SVR_REV(svr, 1, 0) &&
843 ((SVR_SOC_VER(svr) == SVR_P1022) ||
York Sun48f6a5c2012-07-06 17:10:33 -0500844 (SVR_SOC_VER(svr) == SVR_P1013))) {
Timur Tabifbc20aa2011-11-21 17:10:23 -0600845 fsl_sata_reg_t *reg;
846
847 /* first SATA controller */
848 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
849 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
850
851 /* second SATA controller */
852 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
853 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
854 }
855#endif
856
857
wdenk42d1f032003-10-15 23:53:47 +0000858 return 0;
859}
Kumar Gala26f4cdba2009-08-14 13:37:54 -0500860
Kumar Gala26f4cdba2009-08-14 13:37:54 -0500861void arch_preboot_os(void)
862{
Kumar Gala15fba322009-09-11 15:28:41 -0500863 u32 msr;
864
865 /*
866 * We are changing interrupt offsets and are about to boot the OS so
867 * we need to make sure we disable all async interrupts. EE is already
868 * disabled by the time we get called.
869 */
870 msr = mfmsr();
Prabhakar Kushwaha5344f7a2012-04-29 23:56:30 +0000871 msr &= ~(MSR_ME|MSR_CE);
Kumar Gala15fba322009-09-11 15:28:41 -0500872 mtmsr(msr);
Kumar Gala26f4cdba2009-08-14 13:37:54 -0500873}
Kumar Galaf54fe872010-04-20 10:21:25 -0500874
875#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
876int sata_initialize(void)
877{
878 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
879 return __sata_initialize();
880
881 return 1;
882}
883#endif
Kumar Galaf9a33f12011-02-02 11:23:50 -0600884
885void cpu_secondary_init_r(void)
886{
Zhao Qiang2a44efe2014-03-21 16:21:45 +0800887#ifdef CONFIG_U_QE
888 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
889#elif defined CONFIG_QE
Kumar Galaf9a33f12011-02-02 11:23:50 -0600890 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
Zhao Qiang2a44efe2014-03-21 16:21:45 +0800891#endif
892
893#ifdef CONFIG_QE
Timur Tabif2717b42011-11-22 09:21:25 -0600894#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
Haiying Wanga7b1e1b2011-02-07 16:14:15 -0500895 int ret;
Timur Tabif2717b42011-11-22 09:21:25 -0600896 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
Haiying Wanga7b1e1b2011-02-07 16:14:15 -0500897
898 /* load QE firmware from NAND flash to DDR first */
Timur Tabif2717b42011-11-22 09:21:25 -0600899 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800900 &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
Haiying Wanga7b1e1b2011-02-07 16:14:15 -0500901
902 if (ret && ret == -EUCLEAN) {
903 printf ("NAND read for QE firmware at offset %x failed %d\n",
Timur Tabif2717b42011-11-22 09:21:25 -0600904 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
Haiying Wanga7b1e1b2011-02-07 16:14:15 -0500905 }
906#endif
Kumar Galaf9a33f12011-02-02 11:23:50 -0600907 qe_init(qe_base);
908 qe_reset();
909#endif
910}