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gerrit.cesnet.cz / github / trini / u-boot / 3e17ffbb44cd24c53504179ff51a835502b183ed / . / arch / sandbox / dts / test.dts
blob: 9c8c4e270907448ad16fb43bf180c2e97fb21f63 [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]14 gpio1 = &gpio_a;
15 gpio2 = &gpio_b;
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]16 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]17 mmc0 = "/mmc0";
18 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]19 pci0 = &pci0;
20 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]21 pci2 = &pci2;
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]22 remoteproc1 = &rproc_1;
23 remoteproc2 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]24 rtc0 = &rtc_0;
25 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]26 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +0200[diff] [blame]27 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]28 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
Eugeniu Rosca507cef32018-05-19 14:13:55 +0200[diff] [blame]34 fdt-dummy0 = "/translation-test@8000/dev@0,0";
35 fdt-dummy1 = "/translation-test@8000/dev@1,100";
36 fdt-dummy2 = "/translation-test@8000/dev@2,200";
37 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]38 usb0 = &usb_0;
39 usb1 = &usb_1;
40 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +0200[diff] [blame]41 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +0200[diff] [blame]42 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]43 };
44
Simon Glassce6d99a2018-12-10 10:37:33 -0700[diff] [blame]45 audio: audio-codec {
46 compatible = "sandbox,audio-codec";
47 #sound-dai-cells = <1>;
48 };
49
Simon Glasse96fa6c2018-12-10 10:37:34 -0700[diff] [blame]50 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -0600[diff] [blame]51 reg = <0 0>;
52 compatible = "google,cros-ec-sandbox";
53
54 /*
55 * This describes the flash memory within the EC. Note
56 * that the STM32L flash erases to 0, not 0xff.
57 */
58 flash {
59 image-pos = <0x08000000>;
60 size = <0x20000>;
61 erase-value = <0>;
62
63 /* Information for sandbox */
64 ro {
65 image-pos = <0>;
66 size = <0xf000>;
67 };
68 wp-ro {
69 image-pos = <0xf000>;
70 size = <0x1000>;
71 };
72 rw {
73 image-pos = <0x10000>;
74 size = <0x10000>;
75 };
76 };
77 };
78
Yannick Fertré23f965a2019-10-07 15:29:05 +0200[diff] [blame]79 dsi_host: dsi_host {
80 compatible = "sandbox,dsi-host";
81 };
82
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]83 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]84 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]85 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]86 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]87 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]88 u-boot,dm-pre-reloc;
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]89 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
90 <0>, <&gpio_a 12>;
91 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
92 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
93 <&gpio_b 9 0xc 3 2 1>;
Simon Glassa1b17e42018-12-10 10:37:37 -0700[diff] [blame]94 int-value = <1234>;
95 uint-value = <(-1234)>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]96 };
97
98 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]99 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]100 compatible = "not,compatible";
101 };
102
103 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]104 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]105 };
106
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]107 backlight: backlight {
108 compatible = "pwm-backlight";
109 enable-gpios = <&gpio_a 1>;
110 power-supply = <&ldo_1>;
111 pwms = <&pwm 0 1000>;
112 default-brightness-level = <5>;
113 brightness-levels = <0 16 32 64 128 170 202 234 255>;
114 };
115
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200[diff] [blame]116 bind-test {
117 bind-test-child1 {
118 compatible = "sandbox,phy";
119 #phy-cells = <1>;
120 };
121
122 bind-test-child2 {
123 compatible = "simple-bus";
124 };
125 };
126
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]127 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]128 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]129 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]130 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]131 ping-add = <3>;
132 };
133
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200[diff] [blame]134 phy_provider0: gen_phy@0 {
135 compatible = "sandbox,phy";
136 #phy-cells = <1>;
137 };
138
139 phy_provider1: gen_phy@1 {
140 compatible = "sandbox,phy";
141 #phy-cells = <0>;
142 broken;
143 };
144
145 gen_phy_user: gen_phy_user {
146 compatible = "simple-bus";
147 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
148 phy-names = "phy1", "phy2", "phy3";
149 };
150
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]151 some-bus {
152 #address-cells = <1>;
153 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]154 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]155 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]156 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]157 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]158 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]159 compatible = "denx,u-boot-fdt-test";
160 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]161 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]162 ping-add = <5>;
163 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]164 c-test@0 {
165 compatible = "denx,u-boot-fdt-test";
166 reg = <0>;
167 ping-expect = <6>;
168 ping-add = <6>;
169 };
170 c-test@1 {
171 compatible = "denx,u-boot-fdt-test";
172 reg = <1>;
173 ping-expect = <7>;
174 ping-add = <7>;
175 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]176 };
177
178 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]179 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600[diff] [blame]180 ping-expect = <6>;
181 ping-add = <6>;
182 compatible = "google,another-fdt-test";
183 };
184
185 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]186 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]187 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]188 ping-add = <6>;
189 compatible = "google,another-fdt-test";
190 };
191
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]192 f-test {
193 compatible = "denx,u-boot-fdt-test";
194 };
195
196 g-test {
197 compatible = "denx,u-boot-fdt-test";
198 };
199
Bin Meng2786cd72018-10-10 22:07:01 -0700[diff] [blame]200 h-test {
201 compatible = "denx,u-boot-fdt-test1";
202 };
203
Patrice Chotardee87a092017-09-04 14:55:57 +0200[diff] [blame]204 clocks {
205 clk_fixed: clk-fixed {
206 compatible = "fixed-clock";
207 #clock-cells = <0>;
208 clock-frequency = <1234>;
209 };
Anup Patelb630d572019-02-25 08:14:55 +0000[diff] [blame]210
211 clk_fixed_factor: clk-fixed-factor {
212 compatible = "fixed-factor-clock";
213 #clock-cells = <0>;
214 clock-div = <3>;
215 clock-mult = <2>;
216 clocks = <&clk_fixed>;
217 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200[diff] [blame]218
219 osc {
220 compatible = "fixed-clock";
221 #clock-cells = <0>;
222 clock-frequency = <20000000>;
223 };
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]224 };
225
226 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]227 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]228 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200[diff] [blame]229 assigned-clocks = <&clk_sandbox 3>;
230 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]231 };
232
233 clk-test {
234 compatible = "sandbox,clk-test";
235 clocks = <&clk_fixed>,
236 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200[diff] [blame]237 <&clk_sandbox 0>,
238 <&clk_sandbox 3>,
239 <&clk_sandbox 2>;
240 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]241 };
242
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200[diff] [blame]243 ccf: clk-ccf {
244 compatible = "sandbox,clk-ccf";
245 };
246
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]247 eth@10002000 {
248 compatible = "sandbox,eth";
249 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]250 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]251 };
252
253 eth_5: eth@10003000 {
254 compatible = "sandbox,eth";
255 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]256 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]257 };
258
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]259 eth_3: sbe5 {
260 compatible = "sandbox,eth";
261 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]262 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]263 };
264
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]265 eth@10004000 {
266 compatible = "sandbox,eth";
267 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]268 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]269 };
270
Rajan Vaja31b82172018-09-19 03:43:46 -0700[diff] [blame]271 firmware {
272 sandbox_firmware: sandbox-firmware {
273 compatible = "sandbox,firmware";
274 };
275 };
276
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]277 gpio_a: base-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]278 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]279 gpio-controller;
280 #gpio-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]281 gpio-bank-name = "a";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]282 sandbox,gpio-count = <20>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]283 };
284
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]285 gpio_b: extra-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]286 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]287 gpio-controller;
288 #gpio-cells = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]289 gpio-bank-name = "b";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]290 sandbox,gpio-count = <10>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]291 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]292
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]293 i2c@0 {
294 #address-cells = <1>;
295 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]296 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]297 compatible = "sandbox,i2c";
298 clock-frequency = <100000>;
299 eeprom@2c {
300 reg = <0x2c>;
301 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]302 sandbox,emul = <&emul_eeprom>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]303 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]304
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]305 rtc_0: rtc@43 {
306 reg = <0x43>;
307 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]308 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]309 };
310
311 rtc_1: rtc@61 {
312 reg = <0x61>;
313 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]314 sandbox,emul = <&emul1>;
315 };
316
317 i2c_emul: emul {
318 reg = <0xff>;
319 compatible = "sandbox,i2c-emul-parent";
320 emul_eeprom: emul-eeprom {
321 compatible = "sandbox,i2c-eeprom";
322 sandbox,filename = "i2c.bin";
323 sandbox,size = <256>;
324 };
325 emul0: emul0 {
326 compatible = "sandbox,i2c-rtc";
327 };
328 emul1: emull {
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]329 compatible = "sandbox,i2c-rtc";
330 };
331 };
332
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]333 sandbox_pmic: sandbox_pmic {
334 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]335 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]336 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200[diff] [blame]337
338 mc34708: pmic@41 {
339 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]340 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200[diff] [blame]341 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]342 };
343
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100[diff] [blame]344 bootcount@0 {
345 compatible = "u-boot,bootcount-rtc";
346 rtc = <&rtc_1>;
347 offset = <0x13>;
348 };
349
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100[diff] [blame]350 adc@0 {
351 compatible = "sandbox,adc";
352 vdd-supply = <&buck2>;
353 vss-microvolts = <0>;
354 };
355
Simon Glass3c97c4f2016-01-18 19:52:26 -0700[diff] [blame]356 lcd {
357 u-boot,dm-pre-reloc;
358 compatible = "sandbox,lcd-sdl";
359 xres = <1366>;
360 yres = <768>;
361 };
362
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]363 leds {
364 compatible = "gpio-leds";
365
366 iracibble {
367 gpios = <&gpio_a 1 0>;
368 label = "sandbox:red";
369 };
370
371 martinet {
372 gpios = <&gpio_a 2 0>;
373 label = "sandbox:green";
374 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200[diff] [blame]375
376 default_on {
377 gpios = <&gpio_a 5 0>;
378 label = "sandbox:default_on";
379 default-state = "on";
380 };
381
382 default_off {
383 gpios = <&gpio_a 6 0>;
384 label = "sandbox:default_off";
385 default-state = "off";
386 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]387 };
388
Stephen Warren8961b522016-05-16 17:41:37 -0600[diff] [blame]389 mbox: mbox {
390 compatible = "sandbox,mbox";
391 #mbox-cells = <1>;
392 };
393
394 mbox-test {
395 compatible = "sandbox,mbox-test";
396 mboxes = <&mbox 100>, <&mbox 1>;
397 mbox-names = "other", "test";
398 };
399
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900[diff] [blame]400 cpus {
401 cpu-test1 {
402 compatible = "sandbox,cpu_sandbox";
403 u-boot,dm-pre-reloc;
404 };
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]405
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900[diff] [blame]406 cpu-test2 {
407 compatible = "sandbox,cpu_sandbox";
408 u-boot,dm-pre-reloc;
409 };
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]410
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900[diff] [blame]411 cpu-test3 {
412 compatible = "sandbox,cpu_sandbox";
413 u-boot,dm-pre-reloc;
414 };
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]415 };
416
Simon Glasse96fa6c2018-12-10 10:37:34 -0700[diff] [blame]417 i2s: i2s {
418 compatible = "sandbox,i2s";
419 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700[diff] [blame]420 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700[diff] [blame]421 };
422
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200[diff] [blame]423 nop-test_0 {
424 compatible = "sandbox,nop_sandbox1";
425 nop-test_1 {
426 compatible = "sandbox,nop_sandbox2";
427 bind = "True";
428 };
429 nop-test_2 {
430 compatible = "sandbox,nop_sandbox2";
431 bind = "False";
432 };
433 };
434
Mario Six004e67c2018-07-31 14:24:14 +0200[diff] [blame]435 misc-test {
436 compatible = "sandbox,misc_sandbox";
437 };
438
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]439 mmc2 {
440 compatible = "sandbox,mmc";
441 };
442
443 mmc1 {
444 compatible = "sandbox,mmc";
445 };
446
447 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600[diff] [blame]448 compatible = "sandbox,mmc";
449 };
450
Simon Glassb45c8332019-02-16 20:24:50 -0700[diff] [blame]451 pch {
452 compatible = "sandbox,pch";
453 };
454
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]455 pci0: pci-controller0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]456 compatible = "sandbox,pci";
457 device_type = "pci";
458 #address-cells = <3>;
459 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600[diff] [blame]460 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]461 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700[diff] [blame]462 pci@0,0 {
463 compatible = "pci-generic";
464 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600[diff] [blame]465 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700[diff] [blame]466 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300[diff] [blame]467 pci@1,0 {
468 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600[diff] [blame]469 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
470 reg = <0x02000814 0 0 0 0
471 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600[diff] [blame]472 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300[diff] [blame]473 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700[diff] [blame^]474 p2sb-pci@2,0 {
475 compatible = "sandbox,p2sb";
476 reg = <0x02001010 0 0 0 0>;
477 sandbox,emul = <&p2sb_emul>;
478
479 adder {
480 intel,p2sb-port-id = <3>;
481 compatible = "sandbox,adder";
482 };
483 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700[diff] [blame]484 pci@1e,0 {
485 compatible = "sandbox,pmc";
486 reg = <0xf000 0 0 0 0>;
487 sandbox,emul = <&pmc_emul1e>;
488 acpi-base = <0x400>;
489 gpe0-dwx-mask = <0xf>;
490 gpe0-dwx-shift-base = <4>;
491 gpe0-dw = <6 7 9>;
492 gpe0-sts = <0x20>;
493 gpe0-en = <0x30>;
494 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]495 pci@1f,0 {
496 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600[diff] [blame]497 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
498 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600[diff] [blame]499 sandbox,emul = <&swap_case_emul0_1f>;
500 };
501 };
502
503 pci-emul0 {
504 compatible = "sandbox,pci-emul-parent";
505 swap_case_emul0_0: emul0@0,0 {
506 compatible = "sandbox,swap-case";
507 };
508 swap_case_emul0_1: emul0@1,0 {
509 compatible = "sandbox,swap-case";
510 use-ea;
511 };
512 swap_case_emul0_1f: emul0@1f,0 {
513 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]514 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700[diff] [blame^]515 p2sb_emul: emul@2,0 {
516 compatible = "sandbox,p2sb-emul";
517 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700[diff] [blame]518 pmc_emul1e: emul@1e,0 {
519 compatible = "sandbox,pmc-emul";
520 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]521 };
522
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]523 pci1: pci-controller1 {
524 compatible = "sandbox,pci";
525 device_type = "pci";
526 #address-cells = <3>;
527 #size-cells = <2>;
528 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
529 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700[diff] [blame]530 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200[diff] [blame]531 0x0c 0x00 0x1234 0x5678
532 0x10 0x00 0x1234 0x5678>;
533 pci@10,0 {
534 reg = <0x8000 0 0 0 0>;
535 };
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]536 };
537
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]538 pci2: pci-controller2 {
539 compatible = "sandbox,pci";
540 device_type = "pci";
541 #address-cells = <3>;
542 #size-cells = <2>;
543 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
544 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
545 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
546 pci@1f,0 {
547 compatible = "pci-generic";
548 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600[diff] [blame]549 sandbox,emul = <&swap_case_emul2_1f>;
550 };
551 };
552
553 pci-emul2 {
554 compatible = "sandbox,pci-emul-parent";
555 swap_case_emul2_1f: emul2@1f,0 {
556 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]557 };
558 };
559
Ramon Friedbb413332019-04-27 11:15:23 +0300[diff] [blame]560 pci_ep: pci_ep {
561 compatible = "sandbox,pci_ep";
562 };
563
Simon Glass98561572017-04-23 20:10:44 -0600[diff] [blame]564 probing {
565 compatible = "simple-bus";
566 test1 {
567 compatible = "denx,u-boot-probe-test";
568 };
569
570 test2 {
571 compatible = "denx,u-boot-probe-test";
572 };
573
574 test3 {
575 compatible = "denx,u-boot-probe-test";
576 };
577
578 test4 {
579 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100[diff] [blame]580 first-syscon = <&syscon0>;
581 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +0100[diff] [blame]582 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -0600[diff] [blame]583 };
584 };
585
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600[diff] [blame]586 pwrdom: power-domain {
587 compatible = "sandbox,power-domain";
588 #power-domain-cells = <1>;
589 };
590
591 power-domain-test {
592 compatible = "sandbox,power-domain-test";
593 power-domains = <&pwrdom 2>;
594 };
595
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]596 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]597 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]598 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]599 };
600
601 pwm2 {
602 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]603 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]604 };
605
Simon Glass64ce0ca2015-07-06 12:54:31 -0600[diff] [blame]606 ram {
607 compatible = "sandbox,ram";
608 };
609
Simon Glass5010d982015-07-06 12:54:29 -0600[diff] [blame]610 reset@0 {
611 compatible = "sandbox,warm-reset";
612 };
613
614 reset@1 {
615 compatible = "sandbox,reset";
616 };
617
Stephen Warren4581b712016-06-17 09:43:59 -0600[diff] [blame]618 resetc: reset-ctl {
619 compatible = "sandbox,reset-ctl";
620 #reset-cells = <1>;
621 };
622
623 reset-ctl-test {
624 compatible = "sandbox,reset-ctl-test";
625 resets = <&resetc 100>, <&resetc 2>;
626 reset-names = "other", "test";
627 };
628
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]629 rproc_1: rproc@1 {
630 compatible = "sandbox,test-processor";
631 remoteproc-name = "remoteproc-test-dev1";
632 };
633
634 rproc_2: rproc@2 {
635 compatible = "sandbox,test-processor";
636 internal-memory-mapped;
637 remoteproc-name = "remoteproc-test-dev2";
638 };
639
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]640 panel {
641 compatible = "simple-panel";
642 backlight = <&backlight 0 100>;
643 };
644
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300[diff] [blame]645 smem@0 {
646 compatible = "sandbox,smem";
647 };
648
Simon Glassd4901892018-12-10 10:37:36 -0700[diff] [blame]649 sound {
650 compatible = "sandbox,sound";
651 cpu {
652 sound-dai = <&i2s 0>;
653 };
654
655 codec {
656 sound-dai = <&audio 0>;
657 };
658 };
659
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]660 spi@0 {
661 #address-cells = <1>;
662 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]663 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]664 compatible = "sandbox,spi";
665 cs-gpios = <0>, <&gpio_a 0>;
666 spi.bin@0 {
667 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +0000[diff] [blame]668 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]669 spi-max-frequency = <40000000>;
670 sandbox,filename = "spi.bin";
671 };
672 };
673
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100[diff] [blame]674 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]675 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +0200[diff] [blame]676 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]677 };
678
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100[diff] [blame]679 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]680 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]681 reg = <0x20 5
682 0x28 6
683 0x30 7
684 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]685 };
686
Patrick Delaunaya442e612019-03-07 09:57:13 +0100[diff] [blame]687 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +0900[diff] [blame]688 compatible = "simple-mfd", "syscon";
689 reg = <0x40 5
690 0x48 6
691 0x50 7
692 0x58 8>;
693 };
694
Thomas Choue7cc8d12015-12-11 16:27:34 +0800[diff] [blame]695 timer {
696 compatible = "sandbox,timer";
697 clock-frequency = <1000000>;
698 };
699
Miquel Raynalb91ad162018-05-15 11:57:27 +0200[diff] [blame]700 tpm2 {
701 compatible = "sandbox,tpm2";
702 };
703
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]704 uart0: serial {
705 compatible = "sandbox,serial";
706 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500[diff] [blame]707 };
708
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]709 usb_0: usb@0 {
710 compatible = "sandbox,usb";
711 status = "disabled";
712 hub {
713 compatible = "sandbox,usb-hub";
714 #address-cells = <1>;
715 #size-cells = <0>;
716 flash-stick {
717 reg = <0>;
718 compatible = "sandbox,usb-flash";
719 };
720 };
721 };
722
723 usb_1: usb@1 {
724 compatible = "sandbox,usb";
725 hub {
726 compatible = "usb-hub";
727 usb,device-class = <9>;
728 hub-emul {
729 compatible = "sandbox,usb-hub";
730 #address-cells = <1>;
731 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]732 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]733 reg = <0>;
734 compatible = "sandbox,usb-flash";
735 sandbox,filepath = "testflash.bin";
736 };
737
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]738 flash-stick@1 {
739 reg = <1>;
740 compatible = "sandbox,usb-flash";
741 sandbox,filepath = "testflash1.bin";
742 };
743
744 flash-stick@2 {
745 reg = <2>;
746 compatible = "sandbox,usb-flash";
747 sandbox,filepath = "testflash2.bin";
748 };
749
Simon Glassbff1a712015-11-08 23:48:08 -0700[diff] [blame]750 keyb@3 {
751 reg = <3>;
752 compatible = "sandbox,usb-keyb";
753 };
754
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]755 };
756 };
757 };
758
759 usb_2: usb@2 {
760 compatible = "sandbox,usb";
761 status = "disabled";
762 };
763
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200[diff] [blame]764 spmi: spmi@0 {
765 compatible = "sandbox,spmi";
766 #address-cells = <0x1>;
767 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -0600[diff] [blame]768 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200[diff] [blame]769 pm8916@0 {
770 compatible = "qcom,spmi-pmic";
771 reg = <0x0 0x1>;
772 #address-cells = <0x1>;
773 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -0600[diff] [blame]774 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200[diff] [blame]775
776 spmi_gpios: gpios@c000 {
777 compatible = "qcom,pm8916-gpio";
778 reg = <0xc000 0x400>;
779 gpio-controller;
780 gpio-count = <4>;
781 #gpio-cells = <2>;
782 gpio-bank-name="spmi";
783 };
784 };
785 };
maxims@google.com0753bc22017-04-17 12:00:21 -0700[diff] [blame]786
787 wdt0: wdt@0 {
788 compatible = "sandbox,wdt";
789 };
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]790
Mario Six957983e2018-08-09 14:51:19 +0200[diff] [blame]791 axi: axi@0 {
792 compatible = "sandbox,axi";
793 #address-cells = <0x1>;
794 #size-cells = <0x1>;
795 store@0 {
796 compatible = "sandbox,sandbox_store";
797 reg = <0x0 0x400>;
798 };
799 };
800
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]801 chosen {
Simon Glass7e878162018-02-03 10:36:58 -0700[diff] [blame]802 #address-cells = <1>;
803 #size-cells = <1>;
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]804 chosen-test {
805 compatible = "denx,u-boot-fdt-test";
806 reg = <9 1>;
807 };
808 };
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame]809
810 translation-test@8000 {
811 compatible = "simple-bus";
812 reg = <0x8000 0x4000>;
813
814 #address-cells = <0x2>;
815 #size-cells = <0x1>;
816
817 ranges = <0 0x0 0x8000 0x1000
818 1 0x100 0x9000 0x1000
819 2 0x200 0xA000 0x1000
820 3 0x300 0xB000 0x1000
821 >;
822
Fabien Dessenne641067f2019-05-31 15:11:30 +0200[diff] [blame]823 dma-ranges = <0 0x000 0x10000000 0x1000
824 1 0x100 0x20000000 0x1000
825 >;
826
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame]827 dev@0,0 {
828 compatible = "denx,u-boot-fdt-dummy";
829 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +0100[diff] [blame]830 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame]831 };
832
833 dev@1,100 {
834 compatible = "denx,u-boot-fdt-dummy";
835 reg = <1 0x100 0x1000>;
836
837 };
838
839 dev@2,200 {
840 compatible = "denx,u-boot-fdt-dummy";
841 reg = <2 0x200 0x1000>;
842 };
843
844
845 noxlatebus@3,300 {
846 compatible = "simple-bus";
847 reg = <3 0x300 0x1000>;
848
849 #address-cells = <0x1>;
850 #size-cells = <0x0>;
851
852 dev@42 {
853 compatible = "denx,u-boot-fdt-dummy";
854 reg = <0x42>;
855 };
856 };
857 };
Mario Six4eea5312018-09-27 09:19:31 +0200[diff] [blame]858
859 osd {
860 compatible = "sandbox,sandbox_osd";
861 };
Tom Rinid24c1d02018-09-30 18:16:51 -0400[diff] [blame]862
Mario Sixe6fd0182018-07-31 11:44:13 +0200[diff] [blame]863 board {
864 compatible = "sandbox,board_sandbox";
865 };
Jens Wiklanderfa830ae2018-09-25 16:40:16 +0200[diff] [blame]866
867 sandbox_tee {
868 compatible = "sandbox,tee";
869 };
Bin Meng4f89d492018-10-15 02:21:26 -0700[diff] [blame]870
871 sandbox_virtio1 {
872 compatible = "sandbox,virtio1";
873 };
874
875 sandbox_virtio2 {
876 compatible = "sandbox,virtio2";
877 };
Patrice Chotardf41a8242018-10-24 14:10:23 +0200[diff] [blame]878
879 pinctrl {
880 compatible = "sandbox,pinctrl";
881 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +0100[diff] [blame]882
883 hwspinlock@0 {
884 compatible = "sandbox,hwspinlock";
885 };
Grygorii Strashkob3309912018-11-28 19:17:51 +0100[diff] [blame]886
887 dma: dma {
888 compatible = "sandbox,dma";
889 #dma-cells = <1>;
890
891 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
892 dma-names = "m2m", "tx0", "rx0";
893 };
Alex Margineanec9594a2019-06-03 19:12:28 +0300[diff] [blame]894
Alex Margineanc3d9f3f2019-07-12 10:13:53 +0300[diff] [blame]895 /*
896 * keep mdio-mux ahead of mdio so that the mux is removed first at the
897 * end of the test. If parent mdio is removed first, clean-up of the
898 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
899 * active at the end of the test. That it turn doesn't allow the mdio
900 * class to be destroyed, triggering an error.
901 */
902 mdio-mux-test {
903 compatible = "sandbox,mdio-mux";
904 #address-cells = <1>;
905 #size-cells = <0>;
906 mdio-parent-bus = <&mdio>;
907
908 mdio-ch-test@0 {
909 reg = <0>;
910 };
911 mdio-ch-test@1 {
912 reg = <1>;
913 };
914 };
915
916 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +0300[diff] [blame]917 compatible = "sandbox,mdio";
918 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]919};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]920
921#include "sandbox_pmic.dtsi"