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gerrit.cesnet.cz / github / trini / u-boot / 7959882049a9b389c131eff9a128437ee8ebe08e / . / arch / sandbox / dts / test.dts
blob: 6722e18bc39c035e8fe6eac593c2f039030edeef [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]14 gpio1 = &gpio_a;
15 gpio2 = &gpio_b;
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]16 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]17 mmc0 = "/mmc0";
18 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]19 pci0 = &pci0;
20 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]21 pci2 = &pci2;
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]22 remoteproc1 = &rproc_1;
23 remoteproc2 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]24 rtc0 = &rtc_0;
25 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]26 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +0200[diff] [blame]27 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]28 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
Eugeniu Rosca507cef32018-05-19 14:13:55 +0200[diff] [blame]34 fdt-dummy0 = "/translation-test@8000/dev@0,0";
35 fdt-dummy1 = "/translation-test@8000/dev@1,100";
36 fdt-dummy2 = "/translation-test@8000/dev@2,200";
37 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]38 usb0 = &usb_0;
39 usb1 = &usb_1;
40 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +0200[diff] [blame]41 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +0200[diff] [blame]42 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]43 };
44
Simon Glasse6c5c942018-10-01 12:22:08 -0600[diff] [blame]45 cros_ec: cros-ec {
46 reg = <0 0>;
47 compatible = "google,cros-ec-sandbox";
48
49 /*
50 * This describes the flash memory within the EC. Note
51 * that the STM32L flash erases to 0, not 0xff.
52 */
53 flash {
54 image-pos = <0x08000000>;
55 size = <0x20000>;
56 erase-value = <0>;
57
58 /* Information for sandbox */
59 ro {
60 image-pos = <0>;
61 size = <0xf000>;
62 };
63 wp-ro {
64 image-pos = <0xf000>;
65 size = <0x1000>;
66 };
67 rw {
68 image-pos = <0x10000>;
69 size = <0x10000>;
70 };
71 };
72 };
73
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]74 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]75 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]76 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]77 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]78 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]79 u-boot,dm-pre-reloc;
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]80 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
81 <0>, <&gpio_a 12>;
82 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
83 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
84 <&gpio_b 9 0xc 3 2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]85 };
86
87 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]88 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]89 compatible = "not,compatible";
90 };
91
92 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]93 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]94 };
95
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]96 backlight: backlight {
97 compatible = "pwm-backlight";
98 enable-gpios = <&gpio_a 1>;
99 power-supply = <&ldo_1>;
100 pwms = <&pwm 0 1000>;
101 default-brightness-level = <5>;
102 brightness-levels = <0 16 32 64 128 170 202 234 255>;
103 };
104
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200[diff] [blame]105 bind-test {
106 bind-test-child1 {
107 compatible = "sandbox,phy";
108 #phy-cells = <1>;
109 };
110
111 bind-test-child2 {
112 compatible = "simple-bus";
113 };
114 };
115
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]116 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]117 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]118 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]119 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]120 ping-add = <3>;
121 };
122
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200[diff] [blame]123 phy_provider0: gen_phy@0 {
124 compatible = "sandbox,phy";
125 #phy-cells = <1>;
126 };
127
128 phy_provider1: gen_phy@1 {
129 compatible = "sandbox,phy";
130 #phy-cells = <0>;
131 broken;
132 };
133
134 gen_phy_user: gen_phy_user {
135 compatible = "simple-bus";
136 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
137 phy-names = "phy1", "phy2", "phy3";
138 };
139
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]140 some-bus {
141 #address-cells = <1>;
142 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]143 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]144 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]145 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]146 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]147 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]148 compatible = "denx,u-boot-fdt-test";
149 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]150 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]151 ping-add = <5>;
152 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]153 c-test@0 {
154 compatible = "denx,u-boot-fdt-test";
155 reg = <0>;
156 ping-expect = <6>;
157 ping-add = <6>;
158 };
159 c-test@1 {
160 compatible = "denx,u-boot-fdt-test";
161 reg = <1>;
162 ping-expect = <7>;
163 ping-add = <7>;
164 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]165 };
166
167 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]168 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600[diff] [blame]169 ping-expect = <6>;
170 ping-add = <6>;
171 compatible = "google,another-fdt-test";
172 };
173
174 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]175 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]176 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]177 ping-add = <6>;
178 compatible = "google,another-fdt-test";
179 };
180
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]181 f-test {
182 compatible = "denx,u-boot-fdt-test";
183 };
184
185 g-test {
186 compatible = "denx,u-boot-fdt-test";
187 };
188
Bin Meng2786cd72018-10-10 22:07:01 -0700[diff] [blame]189 h-test {
190 compatible = "denx,u-boot-fdt-test1";
191 };
192
Patrice Chotardee87a092017-09-04 14:55:57 +0200[diff] [blame]193 clocks {
194 clk_fixed: clk-fixed {
195 compatible = "fixed-clock";
196 #clock-cells = <0>;
197 clock-frequency = <1234>;
198 };
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]199 };
200
201 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]202 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]203 #clock-cells = <1>;
204 };
205
206 clk-test {
207 compatible = "sandbox,clk-test";
208 clocks = <&clk_fixed>,
209 <&clk_sandbox 1>,
210 <&clk_sandbox 0>;
211 clock-names = "fixed", "i2c", "spi";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]212 };
213
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]214 eth@10002000 {
215 compatible = "sandbox,eth";
216 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]217 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]218 };
219
220 eth_5: eth@10003000 {
221 compatible = "sandbox,eth";
222 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]223 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]224 };
225
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]226 eth_3: sbe5 {
227 compatible = "sandbox,eth";
228 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]229 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]230 };
231
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]232 eth@10004000 {
233 compatible = "sandbox,eth";
234 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]235 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]236 };
237
Rajan Vaja31b82172018-09-19 03:43:46 -0700[diff] [blame]238 firmware {
239 sandbox_firmware: sandbox-firmware {
240 compatible = "sandbox,firmware";
241 };
242 };
243
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]244 gpio_a: base-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]245 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]246 gpio-controller;
247 #gpio-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]248 gpio-bank-name = "a";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]249 sandbox,gpio-count = <20>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]250 };
251
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]252 gpio_b: extra-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]253 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]254 gpio-controller;
255 #gpio-cells = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]256 gpio-bank-name = "b";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]257 sandbox,gpio-count = <10>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]258 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]259
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]260 i2c@0 {
261 #address-cells = <1>;
262 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]263 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]264 compatible = "sandbox,i2c";
265 clock-frequency = <100000>;
266 eeprom@2c {
267 reg = <0x2c>;
268 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]269 sandbox,emul = <&emul_eeprom>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]270 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]271
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]272 rtc_0: rtc@43 {
273 reg = <0x43>;
274 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]275 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]276 };
277
278 rtc_1: rtc@61 {
279 reg = <0x61>;
280 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]281 sandbox,emul = <&emul1>;
282 };
283
284 i2c_emul: emul {
285 reg = <0xff>;
286 compatible = "sandbox,i2c-emul-parent";
287 emul_eeprom: emul-eeprom {
288 compatible = "sandbox,i2c-eeprom";
289 sandbox,filename = "i2c.bin";
290 sandbox,size = <256>;
291 };
292 emul0: emul0 {
293 compatible = "sandbox,i2c-rtc";
294 };
295 emul1: emull {
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]296 compatible = "sandbox,i2c-rtc";
297 };
298 };
299
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]300 sandbox_pmic: sandbox_pmic {
301 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]302 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]303 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200[diff] [blame]304
305 mc34708: pmic@41 {
306 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]307 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200[diff] [blame]308 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]309 };
310
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100[diff] [blame]311 adc@0 {
312 compatible = "sandbox,adc";
313 vdd-supply = <&buck2>;
314 vss-microvolts = <0>;
315 };
316
Simon Glass3c97c4f2016-01-18 19:52:26 -0700[diff] [blame]317 lcd {
318 u-boot,dm-pre-reloc;
319 compatible = "sandbox,lcd-sdl";
320 xres = <1366>;
321 yres = <768>;
322 };
323
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]324 leds {
325 compatible = "gpio-leds";
326
327 iracibble {
328 gpios = <&gpio_a 1 0>;
329 label = "sandbox:red";
330 };
331
332 martinet {
333 gpios = <&gpio_a 2 0>;
334 label = "sandbox:green";
335 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200[diff] [blame]336
337 default_on {
338 gpios = <&gpio_a 5 0>;
339 label = "sandbox:default_on";
340 default-state = "on";
341 };
342
343 default_off {
344 gpios = <&gpio_a 6 0>;
345 label = "sandbox:default_off";
346 default-state = "off";
347 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]348 };
349
Stephen Warren8961b522016-05-16 17:41:37 -0600[diff] [blame]350 mbox: mbox {
351 compatible = "sandbox,mbox";
352 #mbox-cells = <1>;
353 };
354
355 mbox-test {
356 compatible = "sandbox,mbox-test";
357 mboxes = <&mbox 100>, <&mbox 1>;
358 mbox-names = "other", "test";
359 };
360
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]361 cpu-test1 {
362 compatible = "sandbox,cpu_sandbox";
Bin Meng25d0fe72018-10-14 01:07:20 -0700[diff] [blame]363 u-boot,dm-pre-reloc;
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]364 };
365
366 cpu-test2 {
367 compatible = "sandbox,cpu_sandbox";
Bin Meng25d0fe72018-10-14 01:07:20 -0700[diff] [blame]368 u-boot,dm-pre-reloc;
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]369 };
370
371 cpu-test3 {
372 compatible = "sandbox,cpu_sandbox";
Bin Meng25d0fe72018-10-14 01:07:20 -0700[diff] [blame]373 u-boot,dm-pre-reloc;
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]374 };
375
Mario Six004e67c2018-07-31 14:24:14 +0200[diff] [blame]376 misc-test {
377 compatible = "sandbox,misc_sandbox";
378 };
379
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]380 mmc2 {
381 compatible = "sandbox,mmc";
382 };
383
384 mmc1 {
385 compatible = "sandbox,mmc";
386 };
387
388 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600[diff] [blame]389 compatible = "sandbox,mmc";
390 };
391
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]392 pci0: pci-controller0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]393 compatible = "sandbox,pci";
394 device_type = "pci";
395 #address-cells = <3>;
396 #size-cells = <2>;
397 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
398 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700[diff] [blame]399 pci@0,0 {
400 compatible = "pci-generic";
401 reg = <0x0000 0 0 0 0>;
402 emul@0,0 {
403 compatible = "sandbox,swap-case";
404 };
405 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]406 pci@1f,0 {
407 compatible = "pci-generic";
408 reg = <0xf800 0 0 0 0>;
409 emul@1f,0 {
410 compatible = "sandbox,swap-case";
411 };
412 };
413 };
414
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]415 pci1: pci-controller1 {
416 compatible = "sandbox,pci";
417 device_type = "pci";
418 #address-cells = <3>;
419 #size-cells = <2>;
420 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
421 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700[diff] [blame]422 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200[diff] [blame]423 0x0c 0x00 0x1234 0x5678
424 0x10 0x00 0x1234 0x5678>;
425 pci@10,0 {
426 reg = <0x8000 0 0 0 0>;
427 };
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]428 };
429
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]430 pci2: pci-controller2 {
431 compatible = "sandbox,pci";
432 device_type = "pci";
433 #address-cells = <3>;
434 #size-cells = <2>;
435 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
436 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
437 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
438 pci@1f,0 {
439 compatible = "pci-generic";
440 reg = <0xf800 0 0 0 0>;
441 emul@1f,0 {
442 compatible = "sandbox,swap-case";
443 };
444 };
445 };
446
Simon Glass98561572017-04-23 20:10:44 -0600[diff] [blame]447 probing {
448 compatible = "simple-bus";
449 test1 {
450 compatible = "denx,u-boot-probe-test";
451 };
452
453 test2 {
454 compatible = "denx,u-boot-probe-test";
455 };
456
457 test3 {
458 compatible = "denx,u-boot-probe-test";
459 };
460
461 test4 {
462 compatible = "denx,u-boot-probe-test";
463 };
464 };
465
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600[diff] [blame]466 pwrdom: power-domain {
467 compatible = "sandbox,power-domain";
468 #power-domain-cells = <1>;
469 };
470
471 power-domain-test {
472 compatible = "sandbox,power-domain-test";
473 power-domains = <&pwrdom 2>;
474 };
475
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]476 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]477 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]478 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]479 };
480
481 pwm2 {
482 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]483 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]484 };
485
Simon Glass64ce0ca2015-07-06 12:54:31 -0600[diff] [blame]486 ram {
487 compatible = "sandbox,ram";
488 };
489
Simon Glass5010d982015-07-06 12:54:29 -0600[diff] [blame]490 reset@0 {
491 compatible = "sandbox,warm-reset";
492 };
493
494 reset@1 {
495 compatible = "sandbox,reset";
496 };
497
Stephen Warren4581b712016-06-17 09:43:59 -0600[diff] [blame]498 resetc: reset-ctl {
499 compatible = "sandbox,reset-ctl";
500 #reset-cells = <1>;
501 };
502
503 reset-ctl-test {
504 compatible = "sandbox,reset-ctl-test";
505 resets = <&resetc 100>, <&resetc 2>;
506 reset-names = "other", "test";
507 };
508
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]509 rproc_1: rproc@1 {
510 compatible = "sandbox,test-processor";
511 remoteproc-name = "remoteproc-test-dev1";
512 };
513
514 rproc_2: rproc@2 {
515 compatible = "sandbox,test-processor";
516 internal-memory-mapped;
517 remoteproc-name = "remoteproc-test-dev2";
518 };
519
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]520 panel {
521 compatible = "simple-panel";
522 backlight = <&backlight 0 100>;
523 };
524
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300[diff] [blame]525 smem@0 {
526 compatible = "sandbox,smem";
527 };
528
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]529 spi@0 {
530 #address-cells = <1>;
531 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]532 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]533 compatible = "sandbox,spi";
534 cs-gpios = <0>, <&gpio_a 0>;
535 spi.bin@0 {
536 reg = <0>;
537 compatible = "spansion,m25p16", "spi-flash";
538 spi-max-frequency = <40000000>;
539 sandbox,filename = "spi.bin";
540 };
541 };
542
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]543 syscon@0 {
544 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +0200[diff] [blame]545 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]546 };
547
548 syscon@1 {
549 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]550 reg = <0x20 5
551 0x28 6
552 0x30 7
553 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]554 };
555
Masahiro Yamada99552c32018-04-23 13:26:53 +0900[diff] [blame]556 syscon@2 {
557 compatible = "simple-mfd", "syscon";
558 reg = <0x40 5
559 0x48 6
560 0x50 7
561 0x58 8>;
562 };
563
Thomas Choue7cc8d12015-12-11 16:27:34 +0800[diff] [blame]564 timer {
565 compatible = "sandbox,timer";
566 clock-frequency = <1000000>;
567 };
568
Miquel Raynalb91ad162018-05-15 11:57:27 +0200[diff] [blame]569 tpm2 {
570 compatible = "sandbox,tpm2";
571 };
572
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]573 uart0: serial {
574 compatible = "sandbox,serial";
575 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500[diff] [blame]576 };
577
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]578 usb_0: usb@0 {
579 compatible = "sandbox,usb";
580 status = "disabled";
581 hub {
582 compatible = "sandbox,usb-hub";
583 #address-cells = <1>;
584 #size-cells = <0>;
585 flash-stick {
586 reg = <0>;
587 compatible = "sandbox,usb-flash";
588 };
589 };
590 };
591
592 usb_1: usb@1 {
593 compatible = "sandbox,usb";
594 hub {
595 compatible = "usb-hub";
596 usb,device-class = <9>;
597 hub-emul {
598 compatible = "sandbox,usb-hub";
599 #address-cells = <1>;
600 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]601 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]602 reg = <0>;
603 compatible = "sandbox,usb-flash";
604 sandbox,filepath = "testflash.bin";
605 };
606
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]607 flash-stick@1 {
608 reg = <1>;
609 compatible = "sandbox,usb-flash";
610 sandbox,filepath = "testflash1.bin";
611 };
612
613 flash-stick@2 {
614 reg = <2>;
615 compatible = "sandbox,usb-flash";
616 sandbox,filepath = "testflash2.bin";
617 };
618
Simon Glassbff1a712015-11-08 23:48:08 -0700[diff] [blame]619 keyb@3 {
620 reg = <3>;
621 compatible = "sandbox,usb-keyb";
622 };
623
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]624 };
625 };
626 };
627
628 usb_2: usb@2 {
629 compatible = "sandbox,usb";
630 status = "disabled";
631 };
632
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200[diff] [blame]633 spmi: spmi@0 {
634 compatible = "sandbox,spmi";
635 #address-cells = <0x1>;
636 #size-cells = <0x1>;
637 pm8916@0 {
638 compatible = "qcom,spmi-pmic";
639 reg = <0x0 0x1>;
640 #address-cells = <0x1>;
641 #size-cells = <0x1>;
642
643 spmi_gpios: gpios@c000 {
644 compatible = "qcom,pm8916-gpio";
645 reg = <0xc000 0x400>;
646 gpio-controller;
647 gpio-count = <4>;
648 #gpio-cells = <2>;
649 gpio-bank-name="spmi";
650 };
651 };
652 };
maxims@google.com0753bc22017-04-17 12:00:21 -0700[diff] [blame]653
654 wdt0: wdt@0 {
655 compatible = "sandbox,wdt";
656 };
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]657
Mario Six957983e2018-08-09 14:51:19 +0200[diff] [blame]658 axi: axi@0 {
659 compatible = "sandbox,axi";
660 #address-cells = <0x1>;
661 #size-cells = <0x1>;
662 store@0 {
663 compatible = "sandbox,sandbox_store";
664 reg = <0x0 0x400>;
665 };
666 };
667
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]668 chosen {
Simon Glass7e878162018-02-03 10:36:58 -0700[diff] [blame]669 #address-cells = <1>;
670 #size-cells = <1>;
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]671 chosen-test {
672 compatible = "denx,u-boot-fdt-test";
673 reg = <9 1>;
674 };
675 };
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame]676
677 translation-test@8000 {
678 compatible = "simple-bus";
679 reg = <0x8000 0x4000>;
680
681 #address-cells = <0x2>;
682 #size-cells = <0x1>;
683
684 ranges = <0 0x0 0x8000 0x1000
685 1 0x100 0x9000 0x1000
686 2 0x200 0xA000 0x1000
687 3 0x300 0xB000 0x1000
688 >;
689
690 dev@0,0 {
691 compatible = "denx,u-boot-fdt-dummy";
692 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +0100[diff] [blame^]693 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame]694 };
695
696 dev@1,100 {
697 compatible = "denx,u-boot-fdt-dummy";
698 reg = <1 0x100 0x1000>;
699
700 };
701
702 dev@2,200 {
703 compatible = "denx,u-boot-fdt-dummy";
704 reg = <2 0x200 0x1000>;
705 };
706
707
708 noxlatebus@3,300 {
709 compatible = "simple-bus";
710 reg = <3 0x300 0x1000>;
711
712 #address-cells = <0x1>;
713 #size-cells = <0x0>;
714
715 dev@42 {
716 compatible = "denx,u-boot-fdt-dummy";
717 reg = <0x42>;
718 };
719 };
720 };
Mario Six4eea5312018-09-27 09:19:31 +0200[diff] [blame]721
722 osd {
723 compatible = "sandbox,sandbox_osd";
724 };
Tom Rinid24c1d02018-09-30 18:16:51 -0400[diff] [blame]725
Mario Sixe6fd0182018-07-31 11:44:13 +0200[diff] [blame]726 board {
727 compatible = "sandbox,board_sandbox";
728 };
Jens Wiklanderfa830ae2018-09-25 16:40:16 +0200[diff] [blame]729
730 sandbox_tee {
731 compatible = "sandbox,tee";
732 };
Bin Meng4f89d492018-10-15 02:21:26 -0700[diff] [blame]733
734 sandbox_virtio1 {
735 compatible = "sandbox,virtio1";
736 };
737
738 sandbox_virtio2 {
739 compatible = "sandbox,virtio2";
740 };
Patrice Chotardf41a8242018-10-24 14:10:23 +0200[diff] [blame]741
742 pinctrl {
743 compatible = "sandbox,pinctrl";
744 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]745};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]746
747#include "sandbox_pmic.dtsi"