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gerrit.cesnet.cz / github / trini / u-boot / 4eea531859edc7e23fcffadee47757a0c6e0959f / . / arch / sandbox / dts / test.dts
blob: cfa47bcd0dec792101179b43c6924ca00c694de9 [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]14 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]15 mmc0 = "/mmc0";
16 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]17 pci0 = &pci0;
18 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]19 pci2 = &pci2;
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]20 remoteproc1 = &rproc_1;
21 remoteproc2 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]22 rtc0 = &rtc_0;
23 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]24 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +0200[diff] [blame]25 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]26 testbus3 = "/some-bus";
27 testfdt0 = "/some-bus/c-test@0";
28 testfdt1 = "/some-bus/c-test@1";
29 testfdt3 = "/b-test";
30 testfdt5 = "/some-bus/c-test@5";
31 testfdt8 = "/a-test";
Eugeniu Rosca507cef32018-05-19 14:13:55 +0200[diff] [blame]32 fdt-dummy0 = "/translation-test@8000/dev@0,0";
33 fdt-dummy1 = "/translation-test@8000/dev@1,100";
34 fdt-dummy2 = "/translation-test@8000/dev@2,200";
35 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]36 usb0 = &usb_0;
37 usb1 = &usb_1;
38 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +0200[diff] [blame]39 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +0200[diff] [blame^]40 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]41 };
42
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]43 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]44 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]45 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]46 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]47 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]48 u-boot,dm-pre-reloc;
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]49 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
50 <0>, <&gpio_a 12>;
51 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
52 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
53 <&gpio_b 9 0xc 3 2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]54 };
55
56 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]57 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]58 compatible = "not,compatible";
59 };
60
61 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]62 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]63 };
64
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200[diff] [blame]65 bind-test {
66 bind-test-child1 {
67 compatible = "sandbox,phy";
68 #phy-cells = <1>;
69 };
70
71 bind-test-child2 {
72 compatible = "simple-bus";
73 };
74 };
75
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]76 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]77 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]78 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]79 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]80 ping-add = <3>;
81 };
82
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200[diff] [blame]83 phy_provider0: gen_phy@0 {
84 compatible = "sandbox,phy";
85 #phy-cells = <1>;
86 };
87
88 phy_provider1: gen_phy@1 {
89 compatible = "sandbox,phy";
90 #phy-cells = <0>;
91 broken;
92 };
93
94 gen_phy_user: gen_phy_user {
95 compatible = "simple-bus";
96 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
97 phy-names = "phy1", "phy2", "phy3";
98 };
99
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]100 some-bus {
101 #address-cells = <1>;
102 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]103 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]104 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]105 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]106 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]107 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]108 compatible = "denx,u-boot-fdt-test";
109 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]110 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]111 ping-add = <5>;
112 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]113 c-test@0 {
114 compatible = "denx,u-boot-fdt-test";
115 reg = <0>;
116 ping-expect = <6>;
117 ping-add = <6>;
118 };
119 c-test@1 {
120 compatible = "denx,u-boot-fdt-test";
121 reg = <1>;
122 ping-expect = <7>;
123 ping-add = <7>;
124 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]125 };
126
127 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]128 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600[diff] [blame]129 ping-expect = <6>;
130 ping-add = <6>;
131 compatible = "google,another-fdt-test";
132 };
133
134 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]135 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]136 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]137 ping-add = <6>;
138 compatible = "google,another-fdt-test";
139 };
140
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]141 f-test {
142 compatible = "denx,u-boot-fdt-test";
143 };
144
145 g-test {
146 compatible = "denx,u-boot-fdt-test";
147 };
148
Patrice Chotardee87a092017-09-04 14:55:57 +0200[diff] [blame]149 clocks {
150 clk_fixed: clk-fixed {
151 compatible = "fixed-clock";
152 #clock-cells = <0>;
153 clock-frequency = <1234>;
154 };
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]155 };
156
157 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]158 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]159 #clock-cells = <1>;
160 };
161
162 clk-test {
163 compatible = "sandbox,clk-test";
164 clocks = <&clk_fixed>,
165 <&clk_sandbox 1>,
166 <&clk_sandbox 0>;
167 clock-names = "fixed", "i2c", "spi";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]168 };
169
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]170 eth@10002000 {
171 compatible = "sandbox,eth";
172 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]173 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]174 };
175
176 eth_5: eth@10003000 {
177 compatible = "sandbox,eth";
178 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]179 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]180 };
181
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]182 eth_3: sbe5 {
183 compatible = "sandbox,eth";
184 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]185 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]186 };
187
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]188 eth@10004000 {
189 compatible = "sandbox,eth";
190 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]191 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]192 };
193
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]194 gpio_a: base-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]195 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]196 gpio-controller;
197 #gpio-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]198 gpio-bank-name = "a";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]199 sandbox,gpio-count = <20>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]200 };
201
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]202 gpio_b: extra-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]203 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]204 gpio-controller;
205 #gpio-cells = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]206 gpio-bank-name = "b";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]207 sandbox,gpio-count = <10>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]208 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]209
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]210 i2c@0 {
211 #address-cells = <1>;
212 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]213 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]214 compatible = "sandbox,i2c";
215 clock-frequency = <100000>;
216 eeprom@2c {
217 reg = <0x2c>;
218 compatible = "i2c-eeprom";
219 emul {
220 compatible = "sandbox,i2c-eeprom";
221 sandbox,filename = "i2c.bin";
222 sandbox,size = <256>;
223 };
224 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]225
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]226 rtc_0: rtc@43 {
227 reg = <0x43>;
228 compatible = "sandbox-rtc";
229 emul {
230 compatible = "sandbox,i2c-rtc";
231 };
232 };
233
234 rtc_1: rtc@61 {
235 reg = <0x61>;
236 compatible = "sandbox-rtc";
237 emul {
238 compatible = "sandbox,i2c-rtc";
239 };
240 };
241
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]242 sandbox_pmic: sandbox_pmic {
243 reg = <0x40>;
244 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200[diff] [blame]245
246 mc34708: pmic@41 {
247 reg = <0x41>;
248 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]249 };
250
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100[diff] [blame]251 adc@0 {
252 compatible = "sandbox,adc";
253 vdd-supply = <&buck2>;
254 vss-microvolts = <0>;
255 };
256
Simon Glass3c97c4f2016-01-18 19:52:26 -0700[diff] [blame]257 lcd {
258 u-boot,dm-pre-reloc;
259 compatible = "sandbox,lcd-sdl";
260 xres = <1366>;
261 yres = <768>;
262 };
263
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]264 leds {
265 compatible = "gpio-leds";
266
267 iracibble {
268 gpios = <&gpio_a 1 0>;
269 label = "sandbox:red";
270 };
271
272 martinet {
273 gpios = <&gpio_a 2 0>;
274 label = "sandbox:green";
275 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200[diff] [blame]276
277 default_on {
278 gpios = <&gpio_a 5 0>;
279 label = "sandbox:default_on";
280 default-state = "on";
281 };
282
283 default_off {
284 gpios = <&gpio_a 6 0>;
285 label = "sandbox:default_off";
286 default-state = "off";
287 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]288 };
289
Stephen Warren8961b522016-05-16 17:41:37 -0600[diff] [blame]290 mbox: mbox {
291 compatible = "sandbox,mbox";
292 #mbox-cells = <1>;
293 };
294
295 mbox-test {
296 compatible = "sandbox,mbox-test";
297 mboxes = <&mbox 100>, <&mbox 1>;
298 mbox-names = "other", "test";
299 };
300
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]301 cpu-test1 {
302 compatible = "sandbox,cpu_sandbox";
303 };
304
305 cpu-test2 {
306 compatible = "sandbox,cpu_sandbox";
307 };
308
309 cpu-test3 {
310 compatible = "sandbox,cpu_sandbox";
311 };
312
Mario Six004e67c2018-07-31 14:24:14 +0200[diff] [blame]313 misc-test {
314 compatible = "sandbox,misc_sandbox";
315 };
316
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]317 mmc2 {
318 compatible = "sandbox,mmc";
319 };
320
321 mmc1 {
322 compatible = "sandbox,mmc";
323 };
324
325 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600[diff] [blame]326 compatible = "sandbox,mmc";
327 };
328
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]329 pci0: pci-controller0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]330 compatible = "sandbox,pci";
331 device_type = "pci";
332 #address-cells = <3>;
333 #size-cells = <2>;
334 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
335 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700[diff] [blame]336 pci@0,0 {
337 compatible = "pci-generic";
338 reg = <0x0000 0 0 0 0>;
339 emul@0,0 {
340 compatible = "sandbox,swap-case";
341 };
342 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]343 pci@1f,0 {
344 compatible = "pci-generic";
345 reg = <0xf800 0 0 0 0>;
346 emul@1f,0 {
347 compatible = "sandbox,swap-case";
348 };
349 };
350 };
351
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]352 pci1: pci-controller1 {
353 compatible = "sandbox,pci";
354 device_type = "pci";
355 #address-cells = <3>;
356 #size-cells = <2>;
357 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
358 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700[diff] [blame]359 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
360 0x0c 0x00 0x1234 0x5678>;
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]361 };
362
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]363 pci2: pci-controller2 {
364 compatible = "sandbox,pci";
365 device_type = "pci";
366 #address-cells = <3>;
367 #size-cells = <2>;
368 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
369 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
370 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
371 pci@1f,0 {
372 compatible = "pci-generic";
373 reg = <0xf800 0 0 0 0>;
374 emul@1f,0 {
375 compatible = "sandbox,swap-case";
376 };
377 };
378 };
379
Simon Glass98561572017-04-23 20:10:44 -0600[diff] [blame]380 probing {
381 compatible = "simple-bus";
382 test1 {
383 compatible = "denx,u-boot-probe-test";
384 };
385
386 test2 {
387 compatible = "denx,u-boot-probe-test";
388 };
389
390 test3 {
391 compatible = "denx,u-boot-probe-test";
392 };
393
394 test4 {
395 compatible = "denx,u-boot-probe-test";
396 };
397 };
398
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600[diff] [blame]399 pwrdom: power-domain {
400 compatible = "sandbox,power-domain";
401 #power-domain-cells = <1>;
402 };
403
404 power-domain-test {
405 compatible = "sandbox,power-domain-test";
406 power-domains = <&pwrdom 2>;
407 };
408
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]409 pwm {
410 compatible = "sandbox,pwm";
411 };
412
413 pwm2 {
414 compatible = "sandbox,pwm";
415 };
416
Simon Glass64ce0ca2015-07-06 12:54:31 -0600[diff] [blame]417 ram {
418 compatible = "sandbox,ram";
419 };
420
Simon Glass5010d982015-07-06 12:54:29 -0600[diff] [blame]421 reset@0 {
422 compatible = "sandbox,warm-reset";
423 };
424
425 reset@1 {
426 compatible = "sandbox,reset";
427 };
428
Stephen Warren4581b712016-06-17 09:43:59 -0600[diff] [blame]429 resetc: reset-ctl {
430 compatible = "sandbox,reset-ctl";
431 #reset-cells = <1>;
432 };
433
434 reset-ctl-test {
435 compatible = "sandbox,reset-ctl-test";
436 resets = <&resetc 100>, <&resetc 2>;
437 reset-names = "other", "test";
438 };
439
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]440 rproc_1: rproc@1 {
441 compatible = "sandbox,test-processor";
442 remoteproc-name = "remoteproc-test-dev1";
443 };
444
445 rproc_2: rproc@2 {
446 compatible = "sandbox,test-processor";
447 internal-memory-mapped;
448 remoteproc-name = "remoteproc-test-dev2";
449 };
450
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300[diff] [blame]451 smem@0 {
452 compatible = "sandbox,smem";
453 };
454
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]455 spi@0 {
456 #address-cells = <1>;
457 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]458 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]459 compatible = "sandbox,spi";
460 cs-gpios = <0>, <&gpio_a 0>;
461 spi.bin@0 {
462 reg = <0>;
463 compatible = "spansion,m25p16", "spi-flash";
464 spi-max-frequency = <40000000>;
465 sandbox,filename = "spi.bin";
466 };
467 };
468
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]469 syscon@0 {
470 compatible = "sandbox,syscon0";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]471 reg = <0x10 4>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]472 };
473
474 syscon@1 {
475 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]476 reg = <0x20 5
477 0x28 6
478 0x30 7
479 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]480 };
481
Masahiro Yamada99552c32018-04-23 13:26:53 +0900[diff] [blame]482 syscon@2 {
483 compatible = "simple-mfd", "syscon";
484 reg = <0x40 5
485 0x48 6
486 0x50 7
487 0x58 8>;
488 };
489
Thomas Choue7cc8d12015-12-11 16:27:34 +0800[diff] [blame]490 timer {
491 compatible = "sandbox,timer";
492 clock-frequency = <1000000>;
493 };
494
Miquel Raynalb91ad162018-05-15 11:57:27 +0200[diff] [blame]495 tpm2 {
496 compatible = "sandbox,tpm2";
497 };
498
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]499 uart0: serial {
500 compatible = "sandbox,serial";
501 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500[diff] [blame]502 };
503
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]504 usb_0: usb@0 {
505 compatible = "sandbox,usb";
506 status = "disabled";
507 hub {
508 compatible = "sandbox,usb-hub";
509 #address-cells = <1>;
510 #size-cells = <0>;
511 flash-stick {
512 reg = <0>;
513 compatible = "sandbox,usb-flash";
514 };
515 };
516 };
517
518 usb_1: usb@1 {
519 compatible = "sandbox,usb";
520 hub {
521 compatible = "usb-hub";
522 usb,device-class = <9>;
523 hub-emul {
524 compatible = "sandbox,usb-hub";
525 #address-cells = <1>;
526 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]527 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]528 reg = <0>;
529 compatible = "sandbox,usb-flash";
530 sandbox,filepath = "testflash.bin";
531 };
532
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]533 flash-stick@1 {
534 reg = <1>;
535 compatible = "sandbox,usb-flash";
536 sandbox,filepath = "testflash1.bin";
537 };
538
539 flash-stick@2 {
540 reg = <2>;
541 compatible = "sandbox,usb-flash";
542 sandbox,filepath = "testflash2.bin";
543 };
544
Simon Glassbff1a712015-11-08 23:48:08 -0700[diff] [blame]545 keyb@3 {
546 reg = <3>;
547 compatible = "sandbox,usb-keyb";
548 };
549
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]550 };
551 };
552 };
553
554 usb_2: usb@2 {
555 compatible = "sandbox,usb";
556 status = "disabled";
557 };
558
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200[diff] [blame]559 spmi: spmi@0 {
560 compatible = "sandbox,spmi";
561 #address-cells = <0x1>;
562 #size-cells = <0x1>;
563 pm8916@0 {
564 compatible = "qcom,spmi-pmic";
565 reg = <0x0 0x1>;
566 #address-cells = <0x1>;
567 #size-cells = <0x1>;
568
569 spmi_gpios: gpios@c000 {
570 compatible = "qcom,pm8916-gpio";
571 reg = <0xc000 0x400>;
572 gpio-controller;
573 gpio-count = <4>;
574 #gpio-cells = <2>;
575 gpio-bank-name="spmi";
576 };
577 };
578 };
maxims@google.com0753bc22017-04-17 12:00:21 -0700[diff] [blame]579
580 wdt0: wdt@0 {
581 compatible = "sandbox,wdt";
582 };
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]583
Mario Six957983e2018-08-09 14:51:19 +0200[diff] [blame]584 axi: axi@0 {
585 compatible = "sandbox,axi";
586 #address-cells = <0x1>;
587 #size-cells = <0x1>;
588 store@0 {
589 compatible = "sandbox,sandbox_store";
590 reg = <0x0 0x400>;
591 };
592 };
593
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]594 chosen {
Simon Glass7e878162018-02-03 10:36:58 -0700[diff] [blame]595 #address-cells = <1>;
596 #size-cells = <1>;
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]597 chosen-test {
598 compatible = "denx,u-boot-fdt-test";
599 reg = <9 1>;
600 };
601 };
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame]602
603 translation-test@8000 {
604 compatible = "simple-bus";
605 reg = <0x8000 0x4000>;
606
607 #address-cells = <0x2>;
608 #size-cells = <0x1>;
609
610 ranges = <0 0x0 0x8000 0x1000
611 1 0x100 0x9000 0x1000
612 2 0x200 0xA000 0x1000
613 3 0x300 0xB000 0x1000
614 >;
615
616 dev@0,0 {
617 compatible = "denx,u-boot-fdt-dummy";
618 reg = <0 0x0 0x1000>;
619 };
620
621 dev@1,100 {
622 compatible = "denx,u-boot-fdt-dummy";
623 reg = <1 0x100 0x1000>;
624
625 };
626
627 dev@2,200 {
628 compatible = "denx,u-boot-fdt-dummy";
629 reg = <2 0x200 0x1000>;
630 };
631
632
633 noxlatebus@3,300 {
634 compatible = "simple-bus";
635 reg = <3 0x300 0x1000>;
636
637 #address-cells = <0x1>;
638 #size-cells = <0x0>;
639
640 dev@42 {
641 compatible = "denx,u-boot-fdt-dummy";
642 reg = <0x42>;
643 };
644 };
645 };
Mario Six4eea5312018-09-27 09:19:31 +0200[diff] [blame^]646
647 osd {
648 compatible = "sandbox,sandbox_osd";
649 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]650};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]651
652#include "sandbox_pmic.dtsi"