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gerrit.cesnet.cz / github / trini / u-boot / 4f89d4947c9ecb2e859f70a6aed2e0c18d63fb54 / . / arch / sandbox / dts / test.dts
blob: 6b54115f9b28025d799b0b4c69e05d78c0fc4b90 [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]14 gpio1 = &gpio_a;
15 gpio2 = &gpio_b;
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]16 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]17 mmc0 = "/mmc0";
18 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]19 pci0 = &pci0;
20 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]21 pci2 = &pci2;
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]22 remoteproc1 = &rproc_1;
23 remoteproc2 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]24 rtc0 = &rtc_0;
25 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]26 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +0200[diff] [blame]27 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]28 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
Eugeniu Rosca507cef32018-05-19 14:13:55 +0200[diff] [blame]34 fdt-dummy0 = "/translation-test@8000/dev@0,0";
35 fdt-dummy1 = "/translation-test@8000/dev@1,100";
36 fdt-dummy2 = "/translation-test@8000/dev@2,200";
37 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]38 usb0 = &usb_0;
39 usb1 = &usb_1;
40 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +0200[diff] [blame]41 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +0200[diff] [blame]42 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]43 };
44
Simon Glasse6c5c942018-10-01 12:22:08 -0600[diff] [blame]45 cros_ec: cros-ec {
46 reg = <0 0>;
47 compatible = "google,cros-ec-sandbox";
48
49 /*
50 * This describes the flash memory within the EC. Note
51 * that the STM32L flash erases to 0, not 0xff.
52 */
53 flash {
54 image-pos = <0x08000000>;
55 size = <0x20000>;
56 erase-value = <0>;
57
58 /* Information for sandbox */
59 ro {
60 image-pos = <0>;
61 size = <0xf000>;
62 };
63 wp-ro {
64 image-pos = <0xf000>;
65 size = <0x1000>;
66 };
67 rw {
68 image-pos = <0x10000>;
69 size = <0x10000>;
70 };
71 };
72 };
73
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]74 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]75 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]76 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]77 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]78 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]79 u-boot,dm-pre-reloc;
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]80 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
81 <0>, <&gpio_a 12>;
82 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
83 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
84 <&gpio_b 9 0xc 3 2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]85 };
86
87 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]88 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]89 compatible = "not,compatible";
90 };
91
92 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]93 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]94 };
95
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]96 backlight: backlight {
97 compatible = "pwm-backlight";
98 enable-gpios = <&gpio_a 1>;
99 power-supply = <&ldo_1>;
100 pwms = <&pwm 0 1000>;
101 default-brightness-level = <5>;
102 brightness-levels = <0 16 32 64 128 170 202 234 255>;
103 };
104
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200[diff] [blame]105 bind-test {
106 bind-test-child1 {
107 compatible = "sandbox,phy";
108 #phy-cells = <1>;
109 };
110
111 bind-test-child2 {
112 compatible = "simple-bus";
113 };
114 };
115
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]116 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]117 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]118 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]119 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]120 ping-add = <3>;
121 };
122
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200[diff] [blame]123 phy_provider0: gen_phy@0 {
124 compatible = "sandbox,phy";
125 #phy-cells = <1>;
126 };
127
128 phy_provider1: gen_phy@1 {
129 compatible = "sandbox,phy";
130 #phy-cells = <0>;
131 broken;
132 };
133
134 gen_phy_user: gen_phy_user {
135 compatible = "simple-bus";
136 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
137 phy-names = "phy1", "phy2", "phy3";
138 };
139
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]140 some-bus {
141 #address-cells = <1>;
142 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]143 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]144 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]145 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]146 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]147 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]148 compatible = "denx,u-boot-fdt-test";
149 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]150 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]151 ping-add = <5>;
152 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]153 c-test@0 {
154 compatible = "denx,u-boot-fdt-test";
155 reg = <0>;
156 ping-expect = <6>;
157 ping-add = <6>;
158 };
159 c-test@1 {
160 compatible = "denx,u-boot-fdt-test";
161 reg = <1>;
162 ping-expect = <7>;
163 ping-add = <7>;
164 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]165 };
166
167 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]168 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600[diff] [blame]169 ping-expect = <6>;
170 ping-add = <6>;
171 compatible = "google,another-fdt-test";
172 };
173
174 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]175 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]176 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]177 ping-add = <6>;
178 compatible = "google,another-fdt-test";
179 };
180
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]181 f-test {
182 compatible = "denx,u-boot-fdt-test";
183 };
184
185 g-test {
186 compatible = "denx,u-boot-fdt-test";
187 };
188
Bin Meng2786cd72018-10-10 22:07:01 -0700[diff] [blame]189 h-test {
190 compatible = "denx,u-boot-fdt-test1";
191 };
192
Patrice Chotardee87a092017-09-04 14:55:57 +0200[diff] [blame]193 clocks {
194 clk_fixed: clk-fixed {
195 compatible = "fixed-clock";
196 #clock-cells = <0>;
197 clock-frequency = <1234>;
198 };
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]199 };
200
201 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]202 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]203 #clock-cells = <1>;
204 };
205
206 clk-test {
207 compatible = "sandbox,clk-test";
208 clocks = <&clk_fixed>,
209 <&clk_sandbox 1>,
210 <&clk_sandbox 0>;
211 clock-names = "fixed", "i2c", "spi";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]212 };
213
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]214 eth@10002000 {
215 compatible = "sandbox,eth";
216 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]217 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]218 };
219
220 eth_5: eth@10003000 {
221 compatible = "sandbox,eth";
222 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]223 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]224 };
225
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]226 eth_3: sbe5 {
227 compatible = "sandbox,eth";
228 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]229 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]230 };
231
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]232 eth@10004000 {
233 compatible = "sandbox,eth";
234 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]235 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]236 };
237
Rajan Vaja31b82172018-09-19 03:43:46 -0700[diff] [blame]238 firmware {
239 sandbox_firmware: sandbox-firmware {
240 compatible = "sandbox,firmware";
241 };
242 };
243
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]244 gpio_a: base-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]245 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]246 gpio-controller;
247 #gpio-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]248 gpio-bank-name = "a";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]249 sandbox,gpio-count = <20>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]250 };
251
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]252 gpio_b: extra-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]253 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]254 gpio-controller;
255 #gpio-cells = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]256 gpio-bank-name = "b";
Simon Glass995b60b2018-02-03 10:36:59 -0700[diff] [blame]257 sandbox,gpio-count = <10>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]258 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]259
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]260 i2c@0 {
261 #address-cells = <1>;
262 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]263 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]264 compatible = "sandbox,i2c";
265 clock-frequency = <100000>;
266 eeprom@2c {
267 reg = <0x2c>;
268 compatible = "i2c-eeprom";
269 emul {
270 compatible = "sandbox,i2c-eeprom";
271 sandbox,filename = "i2c.bin";
272 sandbox,size = <256>;
273 };
274 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]275
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]276 rtc_0: rtc@43 {
277 reg = <0x43>;
278 compatible = "sandbox-rtc";
279 emul {
280 compatible = "sandbox,i2c-rtc";
281 };
282 };
283
284 rtc_1: rtc@61 {
285 reg = <0x61>;
286 compatible = "sandbox-rtc";
287 emul {
288 compatible = "sandbox,i2c-rtc";
289 };
290 };
291
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]292 sandbox_pmic: sandbox_pmic {
293 reg = <0x40>;
294 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200[diff] [blame]295
296 mc34708: pmic@41 {
297 reg = <0x41>;
298 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]299 };
300
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100[diff] [blame]301 adc@0 {
302 compatible = "sandbox,adc";
303 vdd-supply = <&buck2>;
304 vss-microvolts = <0>;
305 };
306
Simon Glass3c97c4f2016-01-18 19:52:26 -0700[diff] [blame]307 lcd {
308 u-boot,dm-pre-reloc;
309 compatible = "sandbox,lcd-sdl";
310 xres = <1366>;
311 yres = <768>;
312 };
313
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]314 leds {
315 compatible = "gpio-leds";
316
317 iracibble {
318 gpios = <&gpio_a 1 0>;
319 label = "sandbox:red";
320 };
321
322 martinet {
323 gpios = <&gpio_a 2 0>;
324 label = "sandbox:green";
325 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200[diff] [blame]326
327 default_on {
328 gpios = <&gpio_a 5 0>;
329 label = "sandbox:default_on";
330 default-state = "on";
331 };
332
333 default_off {
334 gpios = <&gpio_a 6 0>;
335 label = "sandbox:default_off";
336 default-state = "off";
337 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]338 };
339
Stephen Warren8961b522016-05-16 17:41:37 -0600[diff] [blame]340 mbox: mbox {
341 compatible = "sandbox,mbox";
342 #mbox-cells = <1>;
343 };
344
345 mbox-test {
346 compatible = "sandbox,mbox-test";
347 mboxes = <&mbox 100>, <&mbox 1>;
348 mbox-names = "other", "test";
349 };
350
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]351 cpu-test1 {
352 compatible = "sandbox,cpu_sandbox";
353 };
354
355 cpu-test2 {
356 compatible = "sandbox,cpu_sandbox";
357 };
358
359 cpu-test3 {
360 compatible = "sandbox,cpu_sandbox";
361 };
362
Mario Six004e67c2018-07-31 14:24:14 +0200[diff] [blame]363 misc-test {
364 compatible = "sandbox,misc_sandbox";
365 };
366
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]367 mmc2 {
368 compatible = "sandbox,mmc";
369 };
370
371 mmc1 {
372 compatible = "sandbox,mmc";
373 };
374
375 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600[diff] [blame]376 compatible = "sandbox,mmc";
377 };
378
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]379 pci0: pci-controller0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]380 compatible = "sandbox,pci";
381 device_type = "pci";
382 #address-cells = <3>;
383 #size-cells = <2>;
384 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
385 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700[diff] [blame]386 pci@0,0 {
387 compatible = "pci-generic";
388 reg = <0x0000 0 0 0 0>;
389 emul@0,0 {
390 compatible = "sandbox,swap-case";
391 };
392 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]393 pci@1f,0 {
394 compatible = "pci-generic";
395 reg = <0xf800 0 0 0 0>;
396 emul@1f,0 {
397 compatible = "sandbox,swap-case";
398 };
399 };
400 };
401
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]402 pci1: pci-controller1 {
403 compatible = "sandbox,pci";
404 device_type = "pci";
405 #address-cells = <3>;
406 #size-cells = <2>;
407 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
408 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700[diff] [blame]409 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200[diff] [blame]410 0x0c 0x00 0x1234 0x5678
411 0x10 0x00 0x1234 0x5678>;
412 pci@10,0 {
413 reg = <0x8000 0 0 0 0>;
414 };
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]415 };
416
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]417 pci2: pci-controller2 {
418 compatible = "sandbox,pci";
419 device_type = "pci";
420 #address-cells = <3>;
421 #size-cells = <2>;
422 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
423 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
424 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
425 pci@1f,0 {
426 compatible = "pci-generic";
427 reg = <0xf800 0 0 0 0>;
428 emul@1f,0 {
429 compatible = "sandbox,swap-case";
430 };
431 };
432 };
433
Simon Glass98561572017-04-23 20:10:44 -0600[diff] [blame]434 probing {
435 compatible = "simple-bus";
436 test1 {
437 compatible = "denx,u-boot-probe-test";
438 };
439
440 test2 {
441 compatible = "denx,u-boot-probe-test";
442 };
443
444 test3 {
445 compatible = "denx,u-boot-probe-test";
446 };
447
448 test4 {
449 compatible = "denx,u-boot-probe-test";
450 };
451 };
452
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600[diff] [blame]453 pwrdom: power-domain {
454 compatible = "sandbox,power-domain";
455 #power-domain-cells = <1>;
456 };
457
458 power-domain-test {
459 compatible = "sandbox,power-domain-test";
460 power-domains = <&pwrdom 2>;
461 };
462
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]463 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]464 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]465 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]466 };
467
468 pwm2 {
469 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]470 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]471 };
472
Simon Glass64ce0ca2015-07-06 12:54:31 -0600[diff] [blame]473 ram {
474 compatible = "sandbox,ram";
475 };
476
Simon Glass5010d982015-07-06 12:54:29 -0600[diff] [blame]477 reset@0 {
478 compatible = "sandbox,warm-reset";
479 };
480
481 reset@1 {
482 compatible = "sandbox,reset";
483 };
484
Stephen Warren4581b712016-06-17 09:43:59 -0600[diff] [blame]485 resetc: reset-ctl {
486 compatible = "sandbox,reset-ctl";
487 #reset-cells = <1>;
488 };
489
490 reset-ctl-test {
491 compatible = "sandbox,reset-ctl-test";
492 resets = <&resetc 100>, <&resetc 2>;
493 reset-names = "other", "test";
494 };
495
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]496 rproc_1: rproc@1 {
497 compatible = "sandbox,test-processor";
498 remoteproc-name = "remoteproc-test-dev1";
499 };
500
501 rproc_2: rproc@2 {
502 compatible = "sandbox,test-processor";
503 internal-memory-mapped;
504 remoteproc-name = "remoteproc-test-dev2";
505 };
506
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]507 panel {
508 compatible = "simple-panel";
509 backlight = <&backlight 0 100>;
510 };
511
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300[diff] [blame]512 smem@0 {
513 compatible = "sandbox,smem";
514 };
515
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]516 spi@0 {
517 #address-cells = <1>;
518 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]519 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]520 compatible = "sandbox,spi";
521 cs-gpios = <0>, <&gpio_a 0>;
522 spi.bin@0 {
523 reg = <0>;
524 compatible = "spansion,m25p16", "spi-flash";
525 spi-max-frequency = <40000000>;
526 sandbox,filename = "spi.bin";
527 };
528 };
529
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]530 syscon@0 {
531 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +0200[diff] [blame]532 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]533 };
534
535 syscon@1 {
536 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]537 reg = <0x20 5
538 0x28 6
539 0x30 7
540 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]541 };
542
Masahiro Yamada99552c32018-04-23 13:26:53 +0900[diff] [blame]543 syscon@2 {
544 compatible = "simple-mfd", "syscon";
545 reg = <0x40 5
546 0x48 6
547 0x50 7
548 0x58 8>;
549 };
550
Thomas Choue7cc8d12015-12-11 16:27:34 +0800[diff] [blame]551 timer {
552 compatible = "sandbox,timer";
553 clock-frequency = <1000000>;
554 };
555
Miquel Raynalb91ad162018-05-15 11:57:27 +0200[diff] [blame]556 tpm2 {
557 compatible = "sandbox,tpm2";
558 };
559
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]560 uart0: serial {
561 compatible = "sandbox,serial";
562 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500[diff] [blame]563 };
564
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]565 usb_0: usb@0 {
566 compatible = "sandbox,usb";
567 status = "disabled";
568 hub {
569 compatible = "sandbox,usb-hub";
570 #address-cells = <1>;
571 #size-cells = <0>;
572 flash-stick {
573 reg = <0>;
574 compatible = "sandbox,usb-flash";
575 };
576 };
577 };
578
579 usb_1: usb@1 {
580 compatible = "sandbox,usb";
581 hub {
582 compatible = "usb-hub";
583 usb,device-class = <9>;
584 hub-emul {
585 compatible = "sandbox,usb-hub";
586 #address-cells = <1>;
587 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]588 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]589 reg = <0>;
590 compatible = "sandbox,usb-flash";
591 sandbox,filepath = "testflash.bin";
592 };
593
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]594 flash-stick@1 {
595 reg = <1>;
596 compatible = "sandbox,usb-flash";
597 sandbox,filepath = "testflash1.bin";
598 };
599
600 flash-stick@2 {
601 reg = <2>;
602 compatible = "sandbox,usb-flash";
603 sandbox,filepath = "testflash2.bin";
604 };
605
Simon Glassbff1a712015-11-08 23:48:08 -0700[diff] [blame]606 keyb@3 {
607 reg = <3>;
608 compatible = "sandbox,usb-keyb";
609 };
610
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]611 };
612 };
613 };
614
615 usb_2: usb@2 {
616 compatible = "sandbox,usb";
617 status = "disabled";
618 };
619
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200[diff] [blame]620 spmi: spmi@0 {
621 compatible = "sandbox,spmi";
622 #address-cells = <0x1>;
623 #size-cells = <0x1>;
624 pm8916@0 {
625 compatible = "qcom,spmi-pmic";
626 reg = <0x0 0x1>;
627 #address-cells = <0x1>;
628 #size-cells = <0x1>;
629
630 spmi_gpios: gpios@c000 {
631 compatible = "qcom,pm8916-gpio";
632 reg = <0xc000 0x400>;
633 gpio-controller;
634 gpio-count = <4>;
635 #gpio-cells = <2>;
636 gpio-bank-name="spmi";
637 };
638 };
639 };
maxims@google.com0753bc22017-04-17 12:00:21 -0700[diff] [blame]640
641 wdt0: wdt@0 {
642 compatible = "sandbox,wdt";
643 };
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]644
Mario Six957983e2018-08-09 14:51:19 +0200[diff] [blame]645 axi: axi@0 {
646 compatible = "sandbox,axi";
647 #address-cells = <0x1>;
648 #size-cells = <0x1>;
649 store@0 {
650 compatible = "sandbox,sandbox_store";
651 reg = <0x0 0x400>;
652 };
653 };
654
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]655 chosen {
Simon Glass7e878162018-02-03 10:36:58 -0700[diff] [blame]656 #address-cells = <1>;
657 #size-cells = <1>;
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]658 chosen-test {
659 compatible = "denx,u-boot-fdt-test";
660 reg = <9 1>;
661 };
662 };
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame]663
664 translation-test@8000 {
665 compatible = "simple-bus";
666 reg = <0x8000 0x4000>;
667
668 #address-cells = <0x2>;
669 #size-cells = <0x1>;
670
671 ranges = <0 0x0 0x8000 0x1000
672 1 0x100 0x9000 0x1000
673 2 0x200 0xA000 0x1000
674 3 0x300 0xB000 0x1000
675 >;
676
677 dev@0,0 {
678 compatible = "denx,u-boot-fdt-dummy";
679 reg = <0 0x0 0x1000>;
680 };
681
682 dev@1,100 {
683 compatible = "denx,u-boot-fdt-dummy";
684 reg = <1 0x100 0x1000>;
685
686 };
687
688 dev@2,200 {
689 compatible = "denx,u-boot-fdt-dummy";
690 reg = <2 0x200 0x1000>;
691 };
692
693
694 noxlatebus@3,300 {
695 compatible = "simple-bus";
696 reg = <3 0x300 0x1000>;
697
698 #address-cells = <0x1>;
699 #size-cells = <0x0>;
700
701 dev@42 {
702 compatible = "denx,u-boot-fdt-dummy";
703 reg = <0x42>;
704 };
705 };
706 };
Mario Six4eea5312018-09-27 09:19:31 +0200[diff] [blame]707
708 osd {
709 compatible = "sandbox,sandbox_osd";
710 };
Tom Rinid24c1d02018-09-30 18:16:51 -0400[diff] [blame]711
Mario Sixe6fd0182018-07-31 11:44:13 +0200[diff] [blame]712 board {
713 compatible = "sandbox,board_sandbox";
714 };
Jens Wiklanderfa830ae2018-09-25 16:40:16 +0200[diff] [blame]715
716 sandbox_tee {
717 compatible = "sandbox,tee";
718 };
Bin Meng4f89d492018-10-15 02:21:26 -0700[diff] [blame^]719
720 sandbox_virtio1 {
721 compatible = "sandbox,virtio1";
722 };
723
724 sandbox_virtio2 {
725 compatible = "sandbox,virtio2";
726 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]727};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]728
729#include "sandbox_pmic.dtsi"