wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1 | /* |
Kumar Gala | a09b9b6 | 2010-12-30 12:09:53 -0600 | [diff] [blame] | 2 | * Copyright 2007-2011 Freescale Semiconductor, Inc. |
Ed Swarthout | 29372ff | 2007-07-27 01:50:47 -0500 | [diff] [blame] | 3 | * |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 4 | * (C) Copyright 2003 Motorola Inc. |
| 5 | * Modified by Xianghua Xiao, X.Xiao@motorola.com |
| 6 | * |
| 7 | * (C) Copyright 2000 |
| 8 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 9 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 10 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #include <common.h> |
| 14 | #include <watchdog.h> |
| 15 | #include <asm/processor.h> |
| 16 | #include <ioports.h> |
Kumar Gala | f54fe87 | 2010-04-20 10:21:25 -0500 | [diff] [blame] | 17 | #include <sata.h> |
Kumar Gala | c916d7c | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 18 | #include <fm_eth.h> |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 19 | #include <asm/io.h> |
Kumar Gala | fd3c9be | 2010-05-05 22:35:27 -0500 | [diff] [blame] | 20 | #include <asm/cache.h> |
Kumar Gala | 8716318 | 2008-01-16 22:38:34 -0600 | [diff] [blame] | 21 | #include <asm/mmu.h> |
Shengzhou Liu | a07bdad | 2015-11-20 15:52:03 +0800 | [diff] [blame] | 22 | #include <fsl_errata.h> |
Kumar Gala | 83d40df | 2008-01-16 01:13:58 -0600 | [diff] [blame] | 23 | #include <asm/fsl_law.h> |
Kumar Gala | f54fe87 | 2010-04-20 10:21:25 -0500 | [diff] [blame] | 24 | #include <asm/fsl_serdes.h> |
Liu Gang | 5ffa88e | 2012-03-08 00:33:17 +0000 | [diff] [blame] | 25 | #include <asm/fsl_srio.h> |
Prabhakar Kushwaha | 2c0d697 | 2016-01-22 14:34:44 +0530 | [diff] [blame] | 26 | #ifdef CONFIG_FSL_CORENET |
| 27 | #include <asm/fsl_portals.h> |
| 28 | #include <asm/fsl_liodn.h> |
| 29 | #endif |
ramneek mehresh | 9dee205 | 2013-08-05 16:00:16 +0530 | [diff] [blame] | 30 | #include <fsl_usb.h> |
York Sun | 57125f2 | 2012-08-08 18:04:53 +0000 | [diff] [blame] | 31 | #include <hwconfig.h> |
Timur Tabi | fbc20aa | 2011-11-21 17:10:23 -0600 | [diff] [blame] | 32 | #include <linux/compiler.h> |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 33 | #include "mp.h" |
Aneesh Bansal | d0a6d7c | 2016-01-22 16:37:27 +0530 | [diff] [blame] | 34 | #ifdef CONFIG_CHAIN_OF_TRUST |
| 35 | #include <fsl_validate.h> |
| 36 | #endif |
Ruchika Gupta | b9eebfa | 2014-10-15 11:35:30 +0530 | [diff] [blame] | 37 | #ifdef CONFIG_FSL_CAAM |
| 38 | #include <fsl_sec.h> |
| 39 | #endif |
Aneesh Bansal | f698e9f | 2016-01-22 17:05:59 +0530 | [diff] [blame] | 40 | #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET) |
| 41 | #include <asm/fsl_pamu.h> |
| 42 | #include <fsl_secboot_err.h> |
| 43 | #endif |
Timur Tabi | f2717b4 | 2011-11-22 09:21:25 -0600 | [diff] [blame] | 44 | #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND |
Haiying Wang | a7b1e1b | 2011-02-07 16:14:15 -0500 | [diff] [blame] | 45 | #include <nand.h> |
| 46 | #include <errno.h> |
| 47 | #endif |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 48 | |
Timur Tabi | fbc20aa | 2011-11-21 17:10:23 -0600 | [diff] [blame] | 49 | #include "../../../../drivers/block/fsl_sata.h" |
Zhao Qiang | 2a44efe | 2014-03-21 16:21:45 +0800 | [diff] [blame] | 50 | #ifdef CONFIG_U_QE |
Qianyu Gong | 2459afb | 2016-02-18 13:01:59 +0800 | [diff] [blame^] | 51 | #include <fsl_qe.h> |
Zhao Qiang | 2a44efe | 2014-03-21 16:21:45 +0800 | [diff] [blame] | 52 | #endif |
Timur Tabi | fbc20aa | 2011-11-21 17:10:23 -0600 | [diff] [blame] | 53 | |
Wolfgang Denk | d87080b | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 54 | DECLARE_GLOBAL_DATA_PTR; |
| 55 | |
Nikhil Badola | d1c561c | 2014-04-15 14:44:52 +0530 | [diff] [blame] | 56 | #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK |
| 57 | /* |
| 58 | * For deriving usb clock from 100MHz sysclk, reference divisor is set |
| 59 | * to a value of 5, which gives an intermediate value 20(100/5). The |
| 60 | * multiplication factor integer is set to 24, which when multiplied to |
| 61 | * above intermediate value provides clock for usb ip. |
| 62 | */ |
| 63 | void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy) |
| 64 | { |
| 65 | sys_info_t sysinfo; |
| 66 | |
| 67 | get_sys_info(&sysinfo); |
| 68 | if (sysinfo.diff_sysclk == 1) { |
| 69 | clrbits_be32(&usb_phy->pllprg[1], |
| 70 | CONFIG_SYS_FSL_USB_PLLPRG2_MFI); |
| 71 | setbits_be32(&usb_phy->pllprg[1], |
| 72 | CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK | |
| 73 | CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK | |
| 74 | CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN); |
| 75 | } |
| 76 | } |
| 77 | #endif |
| 78 | |
Suresh Gupta | 9c641a8 | 2014-02-26 14:29:12 +0530 | [diff] [blame] | 79 | #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 |
| 80 | void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) |
| 81 | { |
| 82 | #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE |
| 83 | u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg); |
| 84 | |
| 85 | /* Increase Disconnect Threshold by 50mV */ |
| 86 | xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | |
| 87 | INC_DCNT_THRESHOLD_50MV; |
| 88 | /* Enable programming of USB High speed Disconnect threshold */ |
| 89 | xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; |
| 90 | out_be32(&usb_phy->port1.xcvrprg, xcvrprg); |
| 91 | |
| 92 | xcvrprg = in_be32(&usb_phy->port2.xcvrprg); |
| 93 | /* Increase Disconnect Threshold by 50mV */ |
| 94 | xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | |
| 95 | INC_DCNT_THRESHOLD_50MV; |
| 96 | /* Enable programming of USB High speed Disconnect threshold */ |
| 97 | xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; |
| 98 | out_be32(&usb_phy->port2.xcvrprg, xcvrprg); |
| 99 | #else |
| 100 | |
| 101 | u32 temp = 0; |
| 102 | u32 status = in_be32(&usb_phy->status1); |
| 103 | |
| 104 | u32 squelch_prog_rd_0_2 = |
| 105 | (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0) |
| 106 | & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; |
| 107 | |
| 108 | u32 squelch_prog_rd_3_5 = |
| 109 | (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3) |
| 110 | & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; |
| 111 | |
| 112 | setbits_be32(&usb_phy->config1, |
| 113 | CONFIG_SYS_FSL_USB_HS_DISCNCT_INC); |
| 114 | setbits_be32(&usb_phy->config2, |
| 115 | CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL); |
| 116 | |
| 117 | temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0; |
| 118 | out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); |
| 119 | |
| 120 | temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; |
| 121 | out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); |
| 122 | #endif |
| 123 | } |
| 124 | #endif |
| 125 | |
| 126 | |
Zhao Qiang | 2a44efe | 2014-03-21 16:21:45 +0800 | [diff] [blame] | 127 | #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) |
Andy Fleming | da9d461 | 2007-08-14 00:14:25 -0500 | [diff] [blame] | 128 | extern qe_iop_conf_t qe_iop_conf_tab[]; |
| 129 | extern void qe_config_iopin(u8 port, u8 pin, int dir, |
| 130 | int open_drain, int assign); |
| 131 | extern void qe_init(uint qe_base); |
| 132 | extern void qe_reset(void); |
| 133 | |
| 134 | static void config_qe_ioports(void) |
| 135 | { |
| 136 | u8 port, pin; |
| 137 | int dir, open_drain, assign; |
| 138 | int i; |
| 139 | |
| 140 | for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { |
| 141 | port = qe_iop_conf_tab[i].port; |
| 142 | pin = qe_iop_conf_tab[i].pin; |
| 143 | dir = qe_iop_conf_tab[i].dir; |
| 144 | open_drain = qe_iop_conf_tab[i].open_drain; |
| 145 | assign = qe_iop_conf_tab[i].assign; |
| 146 | qe_config_iopin(port, pin, dir, open_drain, assign); |
| 147 | } |
| 148 | } |
| 149 | #endif |
Matthew McClintock | 40d5fa3 | 2006-06-28 10:43:36 -0500 | [diff] [blame] | 150 | |
Jon Loeliger | 9c4c5ae | 2005-07-23 10:37:35 -0500 | [diff] [blame] | 151 | #ifdef CONFIG_CPM2 |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 152 | void config_8560_ioports (volatile ccsr_cpm_t * cpm) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 153 | { |
| 154 | int portnum; |
| 155 | |
| 156 | for (portnum = 0; portnum < 4; portnum++) { |
| 157 | uint pmsk = 0, |
| 158 | ppar = 0, |
| 159 | psor = 0, |
| 160 | pdir = 0, |
| 161 | podr = 0, |
| 162 | pdat = 0; |
| 163 | iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; |
| 164 | iop_conf_t *eiopc = iopc + 32; |
| 165 | uint msk = 1; |
| 166 | |
| 167 | /* |
| 168 | * NOTE: |
| 169 | * index 0 refers to pin 31, |
| 170 | * index 31 refers to pin 0 |
| 171 | */ |
| 172 | while (iopc < eiopc) { |
| 173 | if (iopc->conf) { |
| 174 | pmsk |= msk; |
| 175 | if (iopc->ppar) |
| 176 | ppar |= msk; |
| 177 | if (iopc->psor) |
| 178 | psor |= msk; |
| 179 | if (iopc->pdir) |
| 180 | pdir |= msk; |
| 181 | if (iopc->podr) |
| 182 | podr |= msk; |
| 183 | if (iopc->pdat) |
| 184 | pdat |= msk; |
| 185 | } |
| 186 | |
| 187 | msk <<= 1; |
| 188 | iopc++; |
| 189 | } |
| 190 | |
| 191 | if (pmsk != 0) { |
Kumar Gala | aafeefb | 2007-11-28 00:36:33 -0600 | [diff] [blame] | 192 | volatile ioport_t *iop = ioport_addr (cpm, portnum); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 193 | uint tpmsk = ~pmsk; |
| 194 | |
| 195 | /* |
| 196 | * the (somewhat confused) paragraph at the |
| 197 | * bottom of page 35-5 warns that there might |
| 198 | * be "unknown behaviour" when programming |
| 199 | * PSORx and PDIRx, if PPARx = 1, so I |
| 200 | * decided this meant I had to disable the |
| 201 | * dedicated function first, and enable it |
| 202 | * last. |
| 203 | */ |
| 204 | iop->ppar &= tpmsk; |
| 205 | iop->psor = (iop->psor & tpmsk) | psor; |
| 206 | iop->podr = (iop->podr & tpmsk) | podr; |
| 207 | iop->pdat = (iop->pdat & tpmsk) | pdat; |
| 208 | iop->pdir = (iop->pdir & tpmsk) | pdir; |
| 209 | iop->ppar |= ppar; |
| 210 | } |
| 211 | } |
| 212 | } |
| 213 | #endif |
| 214 | |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 215 | #ifdef CONFIG_SYS_FSL_CPC |
Aneesh Bansal | fb4a240 | 2014-03-18 23:40:26 +0530 | [diff] [blame] | 216 | #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F) |
Tang Yuantian | 7cb7272 | 2014-07-04 17:39:26 +0800 | [diff] [blame] | 217 | void disable_cpc_sram(void) |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 218 | { |
| 219 | int i; |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 220 | |
| 221 | cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; |
| 222 | |
| 223 | for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { |
Shaohui Xie | 2a9fab8 | 2011-03-16 10:10:32 +0800 | [diff] [blame] | 224 | if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { |
| 225 | /* find and disable LAW of SRAM */ |
| 226 | struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); |
| 227 | |
| 228 | if (law.index == -1) { |
| 229 | printf("\nFatal error happened\n"); |
| 230 | return; |
| 231 | } |
| 232 | disable_law(law.index); |
| 233 | |
| 234 | clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); |
| 235 | out_be32(&cpc->cpccsr0, 0); |
| 236 | out_be32(&cpc->cpcsrcr0, 0); |
| 237 | } |
Aneesh Bansal | fb4a240 | 2014-03-18 23:40:26 +0530 | [diff] [blame] | 238 | } |
| 239 | } |
Shaohui Xie | 2a9fab8 | 2011-03-16 10:10:32 +0800 | [diff] [blame] | 240 | #endif |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 241 | |
Sandeep Singh | 377ffcf | 2014-06-05 18:49:57 +0530 | [diff] [blame] | 242 | #if defined(T1040_TDM_QUIRK_CCSR_BASE) |
| 243 | #ifdef CONFIG_POST |
| 244 | #error POST memory test cannot be enabled with TDM |
| 245 | #endif |
| 246 | static void enable_tdm_law(void) |
| 247 | { |
| 248 | int ret; |
| 249 | char buffer[HWCONFIG_BUFFER_SIZE] = {0}; |
| 250 | int tdm_hwconfig_enabled = 0; |
| 251 | |
| 252 | /* |
| 253 | * Extract hwconfig from environment since environment |
| 254 | * is not setup properly yet. Search for tdm entry in |
| 255 | * hwconfig. |
| 256 | */ |
| 257 | ret = getenv_f("hwconfig", buffer, sizeof(buffer)); |
| 258 | if (ret > 0) { |
| 259 | tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); |
| 260 | /* If tdm is defined in hwconfig, set law for tdm workaround */ |
| 261 | if (tdm_hwconfig_enabled) |
| 262 | set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M, |
| 263 | LAW_TRGT_IF_CCSR); |
| 264 | } |
| 265 | } |
| 266 | #endif |
| 267 | |
Tang Yuantian | 7cb7272 | 2014-07-04 17:39:26 +0800 | [diff] [blame] | 268 | void enable_cpc(void) |
Aneesh Bansal | fb4a240 | 2014-03-18 23:40:26 +0530 | [diff] [blame] | 269 | { |
| 270 | int i; |
Shaveta Leekha | 390619d | 2014-07-02 11:44:15 +0530 | [diff] [blame] | 271 | int ret; |
Aneesh Bansal | fb4a240 | 2014-03-18 23:40:26 +0530 | [diff] [blame] | 272 | u32 size = 0; |
Shaveta Leekha | 390619d | 2014-07-02 11:44:15 +0530 | [diff] [blame] | 273 | u32 cpccfg0; |
| 274 | char buffer[HWCONFIG_BUFFER_SIZE]; |
| 275 | char cpc_subarg[16]; |
| 276 | bool have_hwconfig = false; |
| 277 | int cpc_args = 0; |
Aneesh Bansal | fb4a240 | 2014-03-18 23:40:26 +0530 | [diff] [blame] | 278 | cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; |
| 279 | |
Shaveta Leekha | 390619d | 2014-07-02 11:44:15 +0530 | [diff] [blame] | 280 | /* Extract hwconfig from environment */ |
| 281 | ret = getenv_f("hwconfig", buffer, sizeof(buffer)); |
| 282 | if (ret > 0) { |
| 283 | /* |
| 284 | * If "en_cpc" is not defined in hwconfig then by default all |
| 285 | * cpcs are enable. If this config is defined then individual |
| 286 | * cpcs which have to be enabled should also be defined. |
| 287 | * e.g en_cpc:cpc1,cpc2; |
| 288 | */ |
| 289 | if (hwconfig_f("en_cpc", buffer)) |
| 290 | have_hwconfig = true; |
| 291 | } |
| 292 | |
Aneesh Bansal | fb4a240 | 2014-03-18 23:40:26 +0530 | [diff] [blame] | 293 | for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { |
Shaveta Leekha | 390619d | 2014-07-02 11:44:15 +0530 | [diff] [blame] | 294 | if (have_hwconfig) { |
| 295 | sprintf(cpc_subarg, "cpc%u", i + 1); |
| 296 | cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer); |
| 297 | if (cpc_args == 0) |
| 298 | continue; |
| 299 | } |
| 300 | cpccfg0 = in_be32(&cpc->cpccfg0); |
Aneesh Bansal | fb4a240 | 2014-03-18 23:40:26 +0530 | [diff] [blame] | 301 | size += CPC_CFG0_SZ_K(cpccfg0); |
| 302 | |
Kumar Gala | 1d2c2a6 | 2011-01-13 01:54:01 -0600 | [diff] [blame] | 303 | #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 |
| 304 | setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); |
| 305 | #endif |
Kumar Gala | 868da59 | 2011-01-13 01:56:18 -0600 | [diff] [blame] | 306 | #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 |
| 307 | setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); |
| 308 | #endif |
Scott Wood | 8212519 | 2013-05-15 17:50:13 -0500 | [diff] [blame] | 309 | #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 |
| 310 | setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); |
| 311 | #endif |
York Sun | 133fbfa | 2013-09-16 12:49:31 -0700 | [diff] [blame] | 312 | #ifdef CONFIG_SYS_FSL_ERRATUM_A006379 |
| 313 | if (has_erratum_a006379()) { |
| 314 | setbits_be32(&cpc->cpchdbcr0, |
| 315 | CPC_HDBCR0_SPLRU_LEVEL_EN); |
| 316 | } |
| 317 | #endif |
Kumar Gala | 1d2c2a6 | 2011-01-13 01:54:01 -0600 | [diff] [blame] | 318 | |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 319 | out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); |
| 320 | /* Read back to sync write */ |
| 321 | in_be32(&cpc->cpccsr0); |
| 322 | |
| 323 | } |
| 324 | |
Shruti Kanetkar | 2f848f9 | 2013-08-15 11:25:37 -0500 | [diff] [blame] | 325 | puts("Corenet Platform Cache: "); |
| 326 | print_size(size * 1024, " enabled\n"); |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 327 | } |
| 328 | |
Kim Phillips | e56143e | 2012-10-29 13:34:38 +0000 | [diff] [blame] | 329 | static void invalidate_cpc(void) |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 330 | { |
| 331 | int i; |
| 332 | cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; |
| 333 | |
| 334 | for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { |
Shaohui Xie | 2a9fab8 | 2011-03-16 10:10:32 +0800 | [diff] [blame] | 335 | /* skip CPC when it used as all SRAM */ |
| 336 | if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) |
| 337 | continue; |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 338 | /* Flash invalidate the CPC and clear all the locks */ |
| 339 | out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); |
| 340 | while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) |
| 341 | ; |
| 342 | } |
| 343 | } |
| 344 | #else |
| 345 | #define enable_cpc() |
| 346 | #define invalidate_cpc() |
Tang Yuantian | 7cb7272 | 2014-07-04 17:39:26 +0800 | [diff] [blame] | 347 | #define disable_cpc_sram() |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 348 | #endif /* CONFIG_SYS_FSL_CPC */ |
| 349 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 350 | /* |
| 351 | * Breathe some life into the CPU... |
| 352 | * |
| 353 | * Set up the memory map |
| 354 | * initialize a bunch of registers |
| 355 | */ |
| 356 | |
Kumar Gala | 3c2a67e | 2009-09-17 01:52:37 -0500 | [diff] [blame] | 357 | #ifdef CONFIG_FSL_CORENET |
| 358 | static void corenet_tb_init(void) |
| 359 | { |
| 360 | volatile ccsr_rcpm_t *rcpm = |
| 361 | (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); |
| 362 | volatile ccsr_pic_t *pic = |
Kim Phillips | 680c613 | 2010-08-09 18:39:57 -0500 | [diff] [blame] | 363 | (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); |
Kumar Gala | 3c2a67e | 2009-09-17 01:52:37 -0500 | [diff] [blame] | 364 | u32 whoami = in_be32(&pic->whoami); |
| 365 | |
| 366 | /* Enable the timebase register for this core */ |
| 367 | out_be32(&rcpm->ctbenrl, (1 << whoami)); |
| 368 | } |
| 369 | #endif |
| 370 | |
York Sun | c3678b0 | 2014-03-28 15:07:27 -0700 | [diff] [blame] | 371 | #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 |
| 372 | void fsl_erratum_a007212_workaround(void) |
| 373 | { |
| 374 | ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 375 | u32 ddr_pll_ratio; |
| 376 | u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); |
| 377 | u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); |
| 378 | u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); |
| 379 | #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) |
| 380 | u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); |
| 381 | u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); |
| 382 | #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) |
| 383 | u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); |
| 384 | u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); |
| 385 | #endif |
| 386 | #endif |
| 387 | /* |
| 388 | * Even this workaround applies to selected version of SoCs, it is |
| 389 | * safe to apply to all versions, with the limitation of odd ratios. |
| 390 | * If RCW has disabled DDR PLL, we have to apply this workaround, |
| 391 | * otherwise DDR will not work. |
| 392 | */ |
| 393 | ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> |
| 394 | FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & |
| 395 | FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; |
| 396 | /* check if RCW sets ratio to 0, required by this workaround */ |
| 397 | if (ddr_pll_ratio != 0) |
| 398 | return; |
| 399 | ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> |
| 400 | FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & |
| 401 | FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; |
| 402 | /* check if reserved bits have the desired ratio */ |
| 403 | if (ddr_pll_ratio == 0) { |
| 404 | printf("Error: Unknown DDR PLL ratio!\n"); |
| 405 | return; |
| 406 | } |
| 407 | ddr_pll_ratio >>= 1; |
| 408 | |
| 409 | setbits_be32(plldadcr1, 0x02000001); |
| 410 | #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) |
| 411 | setbits_be32(plldadcr2, 0x02000001); |
| 412 | #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) |
| 413 | setbits_be32(plldadcr3, 0x02000001); |
| 414 | #endif |
| 415 | #endif |
| 416 | setbits_be32(dpdovrcr4, 0xe0000000); |
| 417 | out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1)); |
| 418 | #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) |
| 419 | out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1)); |
| 420 | #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) |
| 421 | out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1)); |
| 422 | #endif |
| 423 | #endif |
| 424 | udelay(100); |
| 425 | clrbits_be32(plldadcr1, 0x02000001); |
| 426 | #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) |
| 427 | clrbits_be32(plldadcr2, 0x02000001); |
| 428 | #if (CONFIG_NUM_DDR_CONTROLLERS >= 3) |
| 429 | clrbits_be32(plldadcr3, 0x02000001); |
| 430 | #endif |
| 431 | #endif |
| 432 | clrbits_be32(dpdovrcr4, 0xe0000000); |
| 433 | } |
| 434 | #endif |
| 435 | |
York Sun | 701e640 | 2014-04-30 14:43:47 -0700 | [diff] [blame] | 436 | ulong cpu_init_f(void) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 437 | { |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 438 | extern void m8560_cpm_reset (void); |
Aneesh Bansal | f698e9f | 2016-01-22 17:05:59 +0530 | [diff] [blame] | 439 | #ifdef CONFIG_SYS_DCSRBAR_PHYS |
Stephen George | f110fe9 | 2011-07-20 09:47:26 -0500 | [diff] [blame] | 440 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 441 | #endif |
Ruchika Gupta | 7065b7d | 2010-12-15 17:02:08 +0000 | [diff] [blame] | 442 | #if defined(CONFIG_SECURE_BOOT) |
| 443 | struct law_entry law; |
| 444 | #endif |
Peter Tyser | a2cd50e | 2008-11-11 10:17:10 -0600 | [diff] [blame] | 445 | #ifdef CONFIG_MPC8548 |
| 446 | ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); |
| 447 | uint svr = get_svr(); |
| 448 | |
| 449 | /* |
| 450 | * CPU2 errata workaround: A core hang possible while executing |
| 451 | * a msync instruction and a snoopable transaction from an I/O |
| 452 | * master tagged to make quick forward progress is present. |
| 453 | * Fixed in silicon rev 2.1. |
| 454 | */ |
| 455 | if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) |
| 456 | out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); |
| 457 | #endif |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 458 | |
Kumar Gala | 8716318 | 2008-01-16 22:38:34 -0600 | [diff] [blame] | 459 | disable_tlb(14); |
| 460 | disable_tlb(15); |
| 461 | |
Ruchika Gupta | 7065b7d | 2010-12-15 17:02:08 +0000 | [diff] [blame] | 462 | #if defined(CONFIG_SECURE_BOOT) |
| 463 | /* Disable the LAW created for NOR flash by the PBI commands */ |
| 464 | law = find_law(CONFIG_SYS_PBI_FLASH_BASE); |
| 465 | if (law.index != -1) |
| 466 | disable_law(law.index); |
Aneesh Bansal | fb4a240 | 2014-03-18 23:40:26 +0530 | [diff] [blame] | 467 | |
| 468 | #if defined(CONFIG_SYS_CPC_REINIT_F) |
| 469 | disable_cpc_sram(); |
| 470 | #endif |
Ruchika Gupta | 7065b7d | 2010-12-15 17:02:08 +0000 | [diff] [blame] | 471 | #endif |
| 472 | |
Jon Loeliger | 9c4c5ae | 2005-07-23 10:37:35 -0500 | [diff] [blame] | 473 | #ifdef CONFIG_CPM2 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 474 | config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 475 | #endif |
| 476 | |
Becky Bruce | f51cdaf | 2010-06-17 11:37:20 -0500 | [diff] [blame] | 477 | init_early_memctl_regs(); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 478 | |
Jon Loeliger | 9c4c5ae | 2005-07-23 10:37:35 -0500 | [diff] [blame] | 479 | #if defined(CONFIG_CPM2) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 480 | m8560_cpm_reset(); |
| 481 | #endif |
Zhao Qiang | 2a44efe | 2014-03-21 16:21:45 +0800 | [diff] [blame] | 482 | |
| 483 | #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) |
Andy Fleming | da9d461 | 2007-08-14 00:14:25 -0500 | [diff] [blame] | 484 | /* Config QE ioports */ |
| 485 | config_qe_ioports(); |
| 486 | #endif |
Zhao Qiang | 2a44efe | 2014-03-21 16:21:45 +0800 | [diff] [blame] | 487 | |
Peter Tyser | 79f4333 | 2009-06-30 17:15:47 -0500 | [diff] [blame] | 488 | #if defined(CONFIG_FSL_DMA) |
| 489 | dma_init(); |
| 490 | #endif |
Kumar Gala | 3c2a67e | 2009-09-17 01:52:37 -0500 | [diff] [blame] | 491 | #ifdef CONFIG_FSL_CORENET |
| 492 | corenet_tb_init(); |
| 493 | #endif |
Kumar Gala | 94e9411 | 2009-11-12 10:26:16 -0600 | [diff] [blame] | 494 | init_used_tlb_cams(); |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 495 | |
| 496 | /* Invalidate the CPC before DDR gets enabled */ |
| 497 | invalidate_cpc(); |
Stephen George | f110fe9 | 2011-07-20 09:47:26 -0500 | [diff] [blame] | 498 | |
| 499 | #ifdef CONFIG_SYS_DCSRBAR_PHYS |
| 500 | /* set DCSRCR so that DCSR space is 1G */ |
| 501 | setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); |
| 502 | in_be32(&gur->dcsrcr); |
| 503 | #endif |
| 504 | |
York Sun | c3678b0 | 2014-03-28 15:07:27 -0700 | [diff] [blame] | 505 | #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 |
| 506 | fsl_erratum_a007212_workaround(); |
| 507 | #endif |
| 508 | |
tang yuantian | 59d34ed | 2014-12-18 10:26:34 +0800 | [diff] [blame] | 509 | return 0; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 510 | } |
| 511 | |
Kumar Gala | 35079aa | 2010-12-15 03:50:47 -0600 | [diff] [blame] | 512 | /* Implement a dummy function for those platforms w/o SERDES */ |
| 513 | static void __fsl_serdes__init(void) |
| 514 | { |
| 515 | return ; |
| 516 | } |
| 517 | __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 518 | |
Prabhakar Kushwaha | e982746 | 2013-08-29 13:10:38 +0530 | [diff] [blame] | 519 | #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 520 | int enable_cluster_l2(void) |
| 521 | { |
| 522 | int i = 0; |
Shengzhou Liu | 5122dfa | 2014-04-25 16:31:22 +0800 | [diff] [blame] | 523 | u32 cluster, svr = get_svr(); |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 524 | ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 525 | struct ccsr_cluster_l2 __iomem *l2cache; |
| 526 | |
Shengzhou Liu | 5122dfa | 2014-04-25 16:31:22 +0800 | [diff] [blame] | 527 | /* only the L2 of first cluster should be enabled as expected on T4080, |
| 528 | * but there is no EOC in the first cluster as HW sake, so return here |
| 529 | * to skip enabling L2 cache of the 2nd cluster. |
| 530 | */ |
| 531 | if (SVR_SOC_VER(svr) == SVR_T4080) |
| 532 | return 0; |
| 533 | |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 534 | cluster = in_be32(&gur->tp_cluster[i].lower); |
| 535 | if (cluster & TP_CLUSTER_EOC) |
| 536 | return 0; |
| 537 | |
| 538 | /* The first cache has already been set up, so skip it */ |
| 539 | i++; |
| 540 | |
| 541 | /* Look through the remaining clusters, and set up their caches */ |
| 542 | do { |
Prabhakar Kushwaha | db9a807 | 2012-12-23 19:25:18 +0000 | [diff] [blame] | 543 | int j, cluster_valid = 0; |
| 544 | |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 545 | l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); |
Prabhakar Kushwaha | db9a807 | 2012-12-23 19:25:18 +0000 | [diff] [blame] | 546 | |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 547 | cluster = in_be32(&gur->tp_cluster[i].lower); |
| 548 | |
Prabhakar Kushwaha | db9a807 | 2012-12-23 19:25:18 +0000 | [diff] [blame] | 549 | /* check that at least one core/accel is enabled in cluster */ |
| 550 | for (j = 0; j < 4; j++) { |
| 551 | u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; |
| 552 | u32 type = in_be32(&gur->tp_ityp[idx]); |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 553 | |
Shaveta Leekha | a1399a9 | 2014-07-02 11:44:54 +0530 | [diff] [blame] | 554 | if ((type & TP_ITYP_AV) && |
| 555 | TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC) |
Prabhakar Kushwaha | db9a807 | 2012-12-23 19:25:18 +0000 | [diff] [blame] | 556 | cluster_valid = 1; |
| 557 | } |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 558 | |
Prabhakar Kushwaha | db9a807 | 2012-12-23 19:25:18 +0000 | [diff] [blame] | 559 | if (cluster_valid) { |
| 560 | /* set stash ID to (cluster) * 2 + 32 + 1 */ |
| 561 | clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); |
| 562 | |
| 563 | printf("enable l2 for cluster %d %p\n", i, l2cache); |
| 564 | |
| 565 | out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); |
| 566 | while ((in_be32(&l2cache->l2csr0) |
| 567 | & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) |
| 568 | ; |
James Yang | 9cd95ac | 2013-03-25 07:40:03 +0000 | [diff] [blame] | 569 | out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); |
Prabhakar Kushwaha | db9a807 | 2012-12-23 19:25:18 +0000 | [diff] [blame] | 570 | } |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 571 | i++; |
| 572 | } while (!(cluster & TP_CLUSTER_EOC)); |
| 573 | |
| 574 | return 0; |
| 575 | } |
| 576 | #endif |
| 577 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 578 | /* |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 579 | * Initialize L2 as cache. |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 580 | */ |
Tang Yuantian | 7cb7272 | 2014-07-04 17:39:26 +0800 | [diff] [blame] | 581 | int l2cache_init(void) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 582 | { |
Timur Tabi | fbc20aa | 2011-11-21 17:10:23 -0600 | [diff] [blame] | 583 | __maybe_unused u32 svr = get_svr(); |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 584 | #ifdef CONFIG_L2_CACHE |
| 585 | ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; |
Prabhakar Kushwaha | e982746 | 2013-08-29 13:10:38 +0530 | [diff] [blame] | 586 | #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 587 | struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; |
Lan Chunhe | 3f0202e | 2010-04-21 07:40:50 -0500 | [diff] [blame] | 588 | #endif |
York Sun | 2a5fcb8 | 2012-10-28 08:12:54 +0000 | [diff] [blame] | 589 | |
Wolfgang Grandegger | 6beecfb | 2008-06-05 13:11:59 +0200 | [diff] [blame] | 590 | puts ("L2: "); |
| 591 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 592 | #if defined(CONFIG_L2_CACHE) |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 593 | volatile uint cache_ctl; |
Timur Tabi | fbc20aa | 2011-11-21 17:10:23 -0600 | [diff] [blame] | 594 | uint ver; |
Kumar Gala | 73f15a0 | 2008-07-14 14:07:00 -0500 | [diff] [blame] | 595 | u32 l2siz_field; |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 596 | |
Kumar Gala | f3e04bd | 2008-04-08 10:45:50 -0500 | [diff] [blame] | 597 | ver = SVR_SOC_VER(svr); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 598 | |
| 599 | asm("msync;isync"); |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 600 | cache_ctl = l2cache->l2ctl; |
Mingkai Hu | 7da5335 | 2009-09-11 14:19:10 +0800 | [diff] [blame] | 601 | |
| 602 | #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) |
| 603 | if (cache_ctl & MPC85xx_L2CTL_L2E) { |
| 604 | /* Clear L2 SRAM memory-mapped base address */ |
| 605 | out_be32(&l2cache->l2srbar0, 0x0); |
| 606 | out_be32(&l2cache->l2srbar1, 0x0); |
| 607 | |
| 608 | /* set MBECCDIS=0, SBECCDIS=0 */ |
| 609 | clrbits_be32(&l2cache->l2errdis, |
| 610 | (MPC85xx_L2ERRDIS_MBECC | |
| 611 | MPC85xx_L2ERRDIS_SBECC)); |
| 612 | |
| 613 | /* set L2E=0, L2SRAM=0 */ |
| 614 | clrbits_be32(&l2cache->l2ctl, |
| 615 | (MPC85xx_L2CTL_L2E | |
| 616 | MPC85xx_L2CTL_L2SRAM_ENTIRE)); |
| 617 | } |
| 618 | #endif |
| 619 | |
Kumar Gala | 73f15a0 | 2008-07-14 14:07:00 -0500 | [diff] [blame] | 620 | l2siz_field = (cache_ctl >> 28) & 0x3; |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 621 | |
Kumar Gala | 73f15a0 | 2008-07-14 14:07:00 -0500 | [diff] [blame] | 622 | switch (l2siz_field) { |
| 623 | case 0x0: |
| 624 | printf(" unknown size (0x%08x)\n", cache_ctl); |
| 625 | return -1; |
| 626 | break; |
| 627 | case 0x1: |
| 628 | if (ver == SVR_8540 || ver == SVR_8560 || |
York Sun | 48f6a5c | 2012-07-06 17:10:33 -0500 | [diff] [blame] | 629 | ver == SVR_8541 || ver == SVR_8555) { |
Shruti Kanetkar | 6b44d9e | 2013-08-15 11:25:38 -0500 | [diff] [blame] | 630 | puts("128 KiB "); |
| 631 | /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ |
Kumar Gala | 73f15a0 | 2008-07-14 14:07:00 -0500 | [diff] [blame] | 632 | cache_ctl = 0xc4000000; |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 633 | } else { |
Shruti Kanetkar | 6b44d9e | 2013-08-15 11:25:38 -0500 | [diff] [blame] | 634 | puts("256 KiB "); |
Ed Swarthout | 29372ff | 2007-07-27 01:50:47 -0500 | [diff] [blame] | 635 | cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ |
| 636 | } |
| 637 | break; |
Kumar Gala | 73f15a0 | 2008-07-14 14:07:00 -0500 | [diff] [blame] | 638 | case 0x2: |
| 639 | if (ver == SVR_8540 || ver == SVR_8560 || |
York Sun | 48f6a5c | 2012-07-06 17:10:33 -0500 | [diff] [blame] | 640 | ver == SVR_8541 || ver == SVR_8555) { |
Shruti Kanetkar | 6b44d9e | 2013-08-15 11:25:38 -0500 | [diff] [blame] | 641 | puts("256 KiB "); |
| 642 | /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ |
Kumar Gala | 73f15a0 | 2008-07-14 14:07:00 -0500 | [diff] [blame] | 643 | cache_ctl = 0xc8000000; |
| 644 | } else { |
Shruti Kanetkar | 6b44d9e | 2013-08-15 11:25:38 -0500 | [diff] [blame] | 645 | puts("512 KiB "); |
Kumar Gala | 73f15a0 | 2008-07-14 14:07:00 -0500 | [diff] [blame] | 646 | /* set L2E=1, L2I=1, & L2SRAM=0 */ |
| 647 | cache_ctl = 0xc0000000; |
| 648 | } |
| 649 | break; |
| 650 | case 0x3: |
Shruti Kanetkar | 6b44d9e | 2013-08-15 11:25:38 -0500 | [diff] [blame] | 651 | puts("1024 KiB "); |
Kumar Gala | 73f15a0 | 2008-07-14 14:07:00 -0500 | [diff] [blame] | 652 | /* set L2E=1, L2I=1, & L2SRAM=0 */ |
| 653 | cache_ctl = 0xc0000000; |
| 654 | break; |
Jon Loeliger | d65cfe8 | 2005-07-25 10:58:39 -0500 | [diff] [blame] | 655 | } |
| 656 | |
Mingkai Hu | 76b474e | 2009-08-18 15:37:15 +0800 | [diff] [blame] | 657 | if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { |
Wolfgang Grandegger | 6beecfb | 2008-06-05 13:11:59 +0200 | [diff] [blame] | 658 | puts("already enabled"); |
Haiying Wang | 888279b | 2010-12-01 10:35:30 -0500 | [diff] [blame] | 659 | #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) |
Kumar Gala | e4c9a35 | 2011-11-09 09:56:41 -0600 | [diff] [blame] | 660 | u32 l2srbar = l2cache->l2srbar0; |
Mingkai Hu | 76b474e | 2009-08-18 15:37:15 +0800 | [diff] [blame] | 661 | if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE |
| 662 | && l2srbar >= CONFIG_SYS_FLASH_BASE) { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 663 | l2srbar = CONFIG_SYS_INIT_L2_ADDR; |
Ed Swarthout | 29372ff | 2007-07-27 01:50:47 -0500 | [diff] [blame] | 664 | l2cache->l2srbar0 = l2srbar; |
Scott Wood | 9a511bd | 2012-10-29 19:00:41 -0500 | [diff] [blame] | 665 | printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); |
Ed Swarthout | 29372ff | 2007-07-27 01:50:47 -0500 | [diff] [blame] | 666 | } |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 667 | #endif /* CONFIG_SYS_INIT_L2_ADDR */ |
Ed Swarthout | 29372ff | 2007-07-27 01:50:47 -0500 | [diff] [blame] | 668 | puts("\n"); |
| 669 | } else { |
| 670 | asm("msync;isync"); |
| 671 | l2cache->l2ctl = cache_ctl; /* invalidate & enable */ |
| 672 | asm("msync;isync"); |
Wolfgang Grandegger | 6beecfb | 2008-06-05 13:11:59 +0200 | [diff] [blame] | 673 | puts("enabled\n"); |
Ed Swarthout | 29372ff | 2007-07-27 01:50:47 -0500 | [diff] [blame] | 674 | } |
Kumar Gala | 1b3e404 | 2009-03-19 09:16:10 -0500 | [diff] [blame] | 675 | #elif defined(CONFIG_BACKSIDE_L2_CACHE) |
York Sun | 48f6a5c | 2012-07-06 17:10:33 -0500 | [diff] [blame] | 676 | if (SVR_SOC_VER(svr) == SVR_P2040) { |
Kumar Gala | acf3f8d | 2011-07-21 00:20:21 -0500 | [diff] [blame] | 677 | puts("N/A\n"); |
| 678 | goto skip_l2; |
| 679 | } |
| 680 | |
Kumar Gala | 1b3e404 | 2009-03-19 09:16:10 -0500 | [diff] [blame] | 681 | u32 l2cfg0 = mfspr(SPRN_L2CFG0); |
| 682 | |
| 683 | /* invalidate the L2 cache */ |
Kumar Gala | 25bacf7 | 2009-09-22 15:45:44 -0500 | [diff] [blame] | 684 | mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); |
| 685 | while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) |
Kumar Gala | 1b3e404 | 2009-03-19 09:16:10 -0500 | [diff] [blame] | 686 | ; |
| 687 | |
Kumar Gala | 82fd1f8 | 2009-03-19 02:53:01 -0500 | [diff] [blame] | 688 | #ifdef CONFIG_SYS_CACHE_STASHING |
| 689 | /* set stash id to (coreID) * 2 + 32 + L2 (1) */ |
| 690 | mtspr(SPRN_L2CSR1, (32 + 1)); |
| 691 | #endif |
| 692 | |
Kumar Gala | 1b3e404 | 2009-03-19 09:16:10 -0500 | [diff] [blame] | 693 | /* enable the cache */ |
| 694 | mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); |
| 695 | |
Dave Liu | 654ea1f | 2009-10-22 00:10:23 -0500 | [diff] [blame] | 696 | if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { |
| 697 | while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) |
| 698 | ; |
Shruti Kanetkar | 2f848f9 | 2013-08-15 11:25:37 -0500 | [diff] [blame] | 699 | print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); |
Dave Liu | 654ea1f | 2009-10-22 00:10:23 -0500 | [diff] [blame] | 700 | } |
Kumar Gala | acf3f8d | 2011-07-21 00:20:21 -0500 | [diff] [blame] | 701 | |
| 702 | skip_l2: |
Prabhakar Kushwaha | e982746 | 2013-08-29 13:10:38 +0530 | [diff] [blame] | 703 | #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 704 | if (l2cache->l2csr0 & L2CSR0_L2E) |
Shruti Kanetkar | 2f848f9 | 2013-08-15 11:25:37 -0500 | [diff] [blame] | 705 | print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, |
| 706 | " enabled\n"); |
York Sun | 6d2b9da | 2012-10-08 07:44:08 +0000 | [diff] [blame] | 707 | |
| 708 | enable_cluster_l2(); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 709 | #else |
Wolfgang Grandegger | 6beecfb | 2008-06-05 13:11:59 +0200 | [diff] [blame] | 710 | puts("disabled\n"); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 711 | #endif |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 712 | |
Tang Yuantian | 7cb7272 | 2014-07-04 17:39:26 +0800 | [diff] [blame] | 713 | return 0; |
| 714 | } |
| 715 | |
| 716 | /* |
| 717 | * |
| 718 | * The newer 8548, etc, parts have twice as much cache, but |
| 719 | * use the same bit-encoding as the older 8555, etc, parts. |
| 720 | * |
| 721 | */ |
| 722 | int cpu_init_r(void) |
| 723 | { |
| 724 | __maybe_unused u32 svr = get_svr(); |
| 725 | #ifdef CONFIG_SYS_LBC_LCRR |
| 726 | fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; |
| 727 | #endif |
| 728 | #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) |
| 729 | extern int spin_table_compat; |
| 730 | const char *spin; |
| 731 | #endif |
| 732 | #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 |
| 733 | ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; |
| 734 | #endif |
| 735 | #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ |
| 736 | defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) |
| 737 | /* |
| 738 | * CPU22 and NMG_CPU_A011 share the same workaround. |
| 739 | * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 |
| 740 | * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 |
| 741 | * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both |
| 742 | * fixed in 2.0. NMG_CPU_A011 is activated by default and can |
| 743 | * be disabled by hwconfig with syntax: |
| 744 | * |
| 745 | * fsl_cpu_a011:disable |
| 746 | */ |
| 747 | extern int enable_cpu_a011_workaround; |
| 748 | #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 |
| 749 | enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); |
| 750 | #else |
| 751 | char buffer[HWCONFIG_BUFFER_SIZE]; |
| 752 | char *buf = NULL; |
| 753 | int n, res; |
| 754 | |
| 755 | n = getenv_f("hwconfig", buffer, sizeof(buffer)); |
| 756 | if (n > 0) |
| 757 | buf = buffer; |
| 758 | |
| 759 | res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); |
| 760 | if (res > 0) { |
| 761 | enable_cpu_a011_workaround = 0; |
| 762 | } else { |
| 763 | if (n >= HWCONFIG_BUFFER_SIZE) { |
| 764 | printf("fsl_cpu_a011 was not found. hwconfig variable " |
| 765 | "may be too long\n"); |
| 766 | } |
| 767 | enable_cpu_a011_workaround = |
| 768 | (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || |
| 769 | (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); |
| 770 | } |
| 771 | #endif |
| 772 | if (enable_cpu_a011_workaround) { |
| 773 | flush_dcache(); |
| 774 | mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); |
| 775 | sync(); |
| 776 | } |
| 777 | #endif |
| 778 | #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 |
| 779 | /* |
| 780 | * A-005812 workaround sets bit 32 of SPR 976 for SoCs running |
| 781 | * in write shadow mode. Checking DCWS before setting SPR 976. |
| 782 | */ |
| 783 | if (mfspr(L1CSR2) & L1CSR2_DCWS) |
| 784 | mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); |
| 785 | #endif |
| 786 | |
| 787 | #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) |
| 788 | spin = getenv("spin_table_compat"); |
| 789 | if (spin && (*spin == 'n')) |
| 790 | spin_table_compat = 0; |
| 791 | else |
| 792 | spin_table_compat = 1; |
| 793 | #endif |
| 794 | |
Prabhakar Kushwaha | 2c0d697 | 2016-01-22 14:34:44 +0530 | [diff] [blame] | 795 | #ifdef CONFIG_FSL_CORENET |
| 796 | set_liodns(); |
| 797 | #ifdef CONFIG_SYS_DPAA_QBMAN |
| 798 | setup_portals(); |
| 799 | #endif |
| 800 | #endif |
| 801 | |
Tang Yuantian | 7cb7272 | 2014-07-04 17:39:26 +0800 | [diff] [blame] | 802 | l2cache_init(); |
Aneesh Bansal | fb4a240 | 2014-03-18 23:40:26 +0530 | [diff] [blame] | 803 | #if defined(CONFIG_RAMBOOT_PBL) |
| 804 | disable_cpc_sram(); |
| 805 | #endif |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 806 | enable_cpc(); |
Sandeep Singh | 377ffcf | 2014-06-05 18:49:57 +0530 | [diff] [blame] | 807 | #if defined(T1040_TDM_QUIRK_CCSR_BASE) |
| 808 | enable_tdm_law(); |
| 809 | #endif |
Kumar Gala | 6aba33e | 2009-03-19 03:40:08 -0500 | [diff] [blame] | 810 | |
York Sun | cb93071 | 2013-06-25 11:37:41 -0700 | [diff] [blame] | 811 | #ifndef CONFIG_SYS_FSL_NO_SERDES |
Kumar Gala | af02506 | 2010-05-22 13:21:39 -0500 | [diff] [blame] | 812 | /* needs to be in ram since code uses global static vars */ |
| 813 | fsl_serdes_init(); |
York Sun | cb93071 | 2013-06-25 11:37:41 -0700 | [diff] [blame] | 814 | #endif |
Kumar Gala | af02506 | 2010-05-22 13:21:39 -0500 | [diff] [blame] | 815 | |
Shengzhou Liu | 424bf94 | 2013-08-15 09:31:47 +0800 | [diff] [blame] | 816 | #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 |
| 817 | #define MCFGR_AXIPIPE 0x000000f0 |
| 818 | if (IS_SVR_REV(svr, 1, 0)) |
Ruchika Gupta | 028dbb8 | 2014-09-09 11:50:31 +0530 | [diff] [blame] | 819 | sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE); |
Shengzhou Liu | 424bf94 | 2013-08-15 09:31:47 +0800 | [diff] [blame] | 820 | #endif |
| 821 | |
Shengzhou Liu | 72bd83c | 2013-01-23 19:56:23 +0000 | [diff] [blame] | 822 | #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 |
| 823 | if (IS_SVR_REV(svr, 1, 0)) { |
| 824 | int i; |
| 825 | __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; |
| 826 | |
| 827 | for (i = 0; i < 12; i++) { |
| 828 | p += i + (i > 5 ? 11 : 0); |
| 829 | out_be32(p, 0x2); |
| 830 | } |
| 831 | p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; |
| 832 | out_be32(p, 0x34); |
| 833 | } |
| 834 | #endif |
| 835 | |
Kumar Gala | a09b9b6 | 2010-12-30 12:09:53 -0600 | [diff] [blame] | 836 | #ifdef CONFIG_SYS_SRIO |
| 837 | srio_init(); |
Liu Gang | c8b2815 | 2013-05-07 16:30:46 +0800 | [diff] [blame] | 838 | #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER |
Liu Gang | ff65f12 | 2012-08-09 05:09:59 +0000 | [diff] [blame] | 839 | char *s = getenv("bootmaster"); |
| 840 | if (s) { |
| 841 | if (!strcmp(s, "SRIO1")) { |
| 842 | srio_boot_master(1); |
| 843 | srio_boot_master_release_slave(1); |
| 844 | } |
| 845 | if (!strcmp(s, "SRIO2")) { |
| 846 | srio_boot_master(2); |
| 847 | srio_boot_master_release_slave(2); |
| 848 | } |
| 849 | } |
Liu Gang | 5ffa88e | 2012-03-08 00:33:17 +0000 | [diff] [blame] | 850 | #endif |
Kumar Gala | a09b9b6 | 2010-12-30 12:09:53 -0600 | [diff] [blame] | 851 | #endif |
| 852 | |
Kumar Gala | ec2b74f | 2008-01-17 16:48:33 -0600 | [diff] [blame] | 853 | #if defined(CONFIG_MP) |
| 854 | setup_mp(); |
| 855 | #endif |
Lan Chunhe | 3f0202e | 2010-04-21 07:40:50 -0500 | [diff] [blame] | 856 | |
Zang Roy-R61911 | 4e0be34 | 2012-09-18 09:50:08 +0000 | [diff] [blame] | 857 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 |
Roy Zang | ae026ff | 2011-01-07 00:24:27 -0600 | [diff] [blame] | 858 | { |
Zang Roy-R61911 | 4e0be34 | 2012-09-18 09:50:08 +0000 | [diff] [blame] | 859 | if (SVR_MAJ(svr) < 3) { |
| 860 | void *p; |
| 861 | p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; |
| 862 | setbits_be32(p, 1 << (31 - 14)); |
| 863 | } |
Roy Zang | ae026ff | 2011-01-07 00:24:27 -0600 | [diff] [blame] | 864 | } |
| 865 | #endif |
| 866 | |
Lan Chunhe | 3f0202e | 2010-04-21 07:40:50 -0500 | [diff] [blame] | 867 | #ifdef CONFIG_SYS_LBC_LCRR |
| 868 | /* |
| 869 | * Modify the CLKDIV field of LCRR register to improve the writing |
| 870 | * speed for NOR flash. |
| 871 | */ |
| 872 | clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); |
| 873 | __raw_readl(&lbc->lcrr); |
| 874 | isync(); |
Kumar Gala | 2b3a1cd | 2011-10-03 08:37:57 -0500 | [diff] [blame] | 875 | #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 |
| 876 | udelay(100); |
| 877 | #endif |
Lan Chunhe | 3f0202e | 2010-04-21 07:40:50 -0500 | [diff] [blame] | 878 | #endif |
| 879 | |
Roy Zang | 86221f0 | 2011-04-13 00:08:51 -0500 | [diff] [blame] | 880 | #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE |
| 881 | { |
ramneek mehresh | 9dee205 | 2013-08-05 16:00:16 +0530 | [diff] [blame] | 882 | struct ccsr_usb_phy __iomem *usb_phy1 = |
Roy Zang | 86221f0 | 2011-04-13 00:08:51 -0500 | [diff] [blame] | 883 | (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; |
Suresh Gupta | 9c641a8 | 2014-02-26 14:29:12 +0530 | [diff] [blame] | 884 | #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 |
| 885 | if (has_erratum_a006261()) |
| 886 | fsl_erratum_a006261_workaround(usb_phy1); |
| 887 | #endif |
Roy Zang | 86221f0 | 2011-04-13 00:08:51 -0500 | [diff] [blame] | 888 | out_be32(&usb_phy1->usb_enable_override, |
| 889 | CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); |
| 890 | } |
| 891 | #endif |
| 892 | #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE |
| 893 | { |
ramneek mehresh | 9dee205 | 2013-08-05 16:00:16 +0530 | [diff] [blame] | 894 | struct ccsr_usb_phy __iomem *usb_phy2 = |
Roy Zang | 86221f0 | 2011-04-13 00:08:51 -0500 | [diff] [blame] | 895 | (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; |
Suresh Gupta | 9c641a8 | 2014-02-26 14:29:12 +0530 | [diff] [blame] | 896 | #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 |
| 897 | if (has_erratum_a006261()) |
| 898 | fsl_erratum_a006261_workaround(usb_phy2); |
| 899 | #endif |
Roy Zang | 86221f0 | 2011-04-13 00:08:51 -0500 | [diff] [blame] | 900 | out_be32(&usb_phy2->usb_enable_override, |
| 901 | CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); |
| 902 | } |
| 903 | #endif |
| 904 | |
Xulei | 99d7b0a | 2013-03-11 17:56:34 +0000 | [diff] [blame] | 905 | #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 |
| 906 | /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal |
| 907 | * multi-bit ECC errors which has impact on performance, so software |
| 908 | * should disable all ECC reporting from USB1 and USB2. |
| 909 | */ |
| 910 | if (IS_SVR_REV(get_svr(), 1, 0)) { |
| 911 | struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) |
| 912 | (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); |
| 913 | setbits_be32(&dcfg->ecccr1, |
| 914 | (DCSR_DCFG_ECC_DISABLE_USB1 | |
| 915 | DCSR_DCFG_ECC_DISABLE_USB2)); |
| 916 | } |
| 917 | #endif |
| 918 | |
Roy Zang | 3fa75c8 | 2013-03-25 07:39:33 +0000 | [diff] [blame] | 919 | #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) |
ramneek mehresh | 9dee205 | 2013-08-05 16:00:16 +0530 | [diff] [blame] | 920 | struct ccsr_usb_phy __iomem *usb_phy = |
Roy Zang | 3fa75c8 | 2013-03-25 07:39:33 +0000 | [diff] [blame] | 921 | (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; |
| 922 | setbits_be32(&usb_phy->pllprg[1], |
| 923 | CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | |
| 924 | CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | |
| 925 | CONFIG_SYS_FSL_USB_PLLPRG2_MFI | |
| 926 | CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); |
Nikhil Badola | d1c561c | 2014-04-15 14:44:52 +0530 | [diff] [blame] | 927 | #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK |
| 928 | usb_single_source_clk_configure(usb_phy); |
| 929 | #endif |
Roy Zang | 3fa75c8 | 2013-03-25 07:39:33 +0000 | [diff] [blame] | 930 | setbits_be32(&usb_phy->port1.ctrl, |
| 931 | CONFIG_SYS_FSL_USB_CTRL_PHY_EN); |
| 932 | setbits_be32(&usb_phy->port1.drvvbuscfg, |
| 933 | CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); |
| 934 | setbits_be32(&usb_phy->port1.pwrfltcfg, |
| 935 | CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); |
| 936 | setbits_be32(&usb_phy->port2.ctrl, |
| 937 | CONFIG_SYS_FSL_USB_CTRL_PHY_EN); |
| 938 | setbits_be32(&usb_phy->port2.drvvbuscfg, |
| 939 | CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); |
| 940 | setbits_be32(&usb_phy->port2.pwrfltcfg, |
| 941 | CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); |
Suresh Gupta | 9c641a8 | 2014-02-26 14:29:12 +0530 | [diff] [blame] | 942 | |
| 943 | #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 |
| 944 | if (has_erratum_a006261()) |
| 945 | fsl_erratum_a006261_workaround(usb_phy); |
Roy Zang | 3fa75c8 | 2013-03-25 07:39:33 +0000 | [diff] [blame] | 946 | #endif |
| 947 | |
Suresh Gupta | 9c641a8 | 2014-02-26 14:29:12 +0530 | [diff] [blame] | 948 | #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */ |
| 949 | |
Kumar Gala | c916d7c | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 950 | #ifdef CONFIG_FMAN_ENET |
| 951 | fman_enet_init(); |
| 952 | #endif |
| 953 | |
Aneesh Bansal | f698e9f | 2016-01-22 17:05:59 +0530 | [diff] [blame] | 954 | #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET) |
| 955 | if (pamu_init() < 0) |
| 956 | fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); |
| 957 | #endif |
| 958 | |
Ruchika Gupta | b9eebfa | 2014-10-15 11:35:30 +0530 | [diff] [blame] | 959 | #ifdef CONFIG_FSL_CAAM |
| 960 | sec_init(); |
| 961 | #endif |
| 962 | |
Timur Tabi | fbc20aa | 2011-11-21 17:10:23 -0600 | [diff] [blame] | 963 | #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) |
| 964 | /* |
| 965 | * For P1022/1013 Rev1.0 silicon, after power on SATA host |
| 966 | * controller is configured in legacy mode instead of the |
| 967 | * expected enterprise mode. Software needs to clear bit[28] |
| 968 | * of HControl register to change to enterprise mode from |
| 969 | * legacy mode. We assume that the controller is offline. |
| 970 | */ |
| 971 | if (IS_SVR_REV(svr, 1, 0) && |
| 972 | ((SVR_SOC_VER(svr) == SVR_P1022) || |
York Sun | 48f6a5c | 2012-07-06 17:10:33 -0500 | [diff] [blame] | 973 | (SVR_SOC_VER(svr) == SVR_P1013))) { |
Timur Tabi | fbc20aa | 2011-11-21 17:10:23 -0600 | [diff] [blame] | 974 | fsl_sata_reg_t *reg; |
| 975 | |
| 976 | /* first SATA controller */ |
| 977 | reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; |
| 978 | clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); |
| 979 | |
| 980 | /* second SATA controller */ |
| 981 | reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; |
| 982 | clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); |
| 983 | } |
| 984 | #endif |
| 985 | |
Alexander Graf | f13c915 | 2014-04-30 19:21:12 +0200 | [diff] [blame] | 986 | init_used_tlb_cams(); |
Timur Tabi | fbc20aa | 2011-11-21 17:10:23 -0600 | [diff] [blame] | 987 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 988 | return 0; |
| 989 | } |
Kumar Gala | 26f4cdba | 2009-08-14 13:37:54 -0500 | [diff] [blame] | 990 | |
Kumar Gala | 26f4cdba | 2009-08-14 13:37:54 -0500 | [diff] [blame] | 991 | void arch_preboot_os(void) |
| 992 | { |
Kumar Gala | 15fba32 | 2009-09-11 15:28:41 -0500 | [diff] [blame] | 993 | u32 msr; |
| 994 | |
| 995 | /* |
| 996 | * We are changing interrupt offsets and are about to boot the OS so |
| 997 | * we need to make sure we disable all async interrupts. EE is already |
| 998 | * disabled by the time we get called. |
| 999 | */ |
| 1000 | msr = mfmsr(); |
Prabhakar Kushwaha | 5344f7a | 2012-04-29 23:56:30 +0000 | [diff] [blame] | 1001 | msr &= ~(MSR_ME|MSR_CE); |
Kumar Gala | 15fba32 | 2009-09-11 15:28:41 -0500 | [diff] [blame] | 1002 | mtmsr(msr); |
Kumar Gala | 26f4cdba | 2009-08-14 13:37:54 -0500 | [diff] [blame] | 1003 | } |
Kumar Gala | f54fe87 | 2010-04-20 10:21:25 -0500 | [diff] [blame] | 1004 | |
| 1005 | #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) |
| 1006 | int sata_initialize(void) |
| 1007 | { |
| 1008 | if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) |
| 1009 | return __sata_initialize(); |
| 1010 | |
| 1011 | return 1; |
| 1012 | } |
| 1013 | #endif |
Kumar Gala | f9a33f1 | 2011-02-02 11:23:50 -0600 | [diff] [blame] | 1014 | |
| 1015 | void cpu_secondary_init_r(void) |
| 1016 | { |
Zhao Qiang | 2a44efe | 2014-03-21 16:21:45 +0800 | [diff] [blame] | 1017 | #ifdef CONFIG_U_QE |
| 1018 | uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */ |
| 1019 | #elif defined CONFIG_QE |
Kumar Gala | f9a33f1 | 2011-02-02 11:23:50 -0600 | [diff] [blame] | 1020 | uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ |
Zhao Qiang | 2a44efe | 2014-03-21 16:21:45 +0800 | [diff] [blame] | 1021 | #endif |
| 1022 | |
| 1023 | #ifdef CONFIG_QE |
Kumar Gala | f9a33f1 | 2011-02-02 11:23:50 -0600 | [diff] [blame] | 1024 | qe_init(qe_base); |
| 1025 | qe_reset(); |
| 1026 | #endif |
| 1027 | } |
Aneesh Bansal | d0a6d7c | 2016-01-22 16:37:27 +0530 | [diff] [blame] | 1028 | |
| 1029 | #ifdef CONFIG_BOARD_LATE_INIT |
| 1030 | int board_late_init(void) |
| 1031 | { |
| 1032 | #ifdef CONFIG_CHAIN_OF_TRUST |
| 1033 | fsl_setenv_chain_of_trust(); |
| 1034 | #endif |
| 1035 | |
| 1036 | return 0; |
| 1037 | } |
| 1038 | #endif |