blob: 3c54f5106ddb49ea5dda0f5418a9cc00348e5fe5 [file] [log] [blame]
Ian Campbell2c7e3b92014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Philipp Tomsichb5299932017-08-03 23:23:55 +02003config SPL_LDSCRIPT
4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
5
Siva Durga Prasad Paladugua4d88922016-07-29 15:31:47 +05306config IDENT_STRING
7 default " Allwinner Technology"
8
Jagan Tekidd928bf2018-01-10 16:03:34 +05309config DRAM_SUN4I
10 bool
11 help
12 Select this dram controller driver for Sun4/5/7i platforms,
13 like A10/A13/A20.
14
Jagan Tekifdfa9342018-03-17 00:16:36 +053015config DRAM_SUN6I
16 bool
17 help
18 Select this dram controller driver for Sun6i platforms,
19 like A31/A31s.
20
Jagan Tekiaf303932018-01-10 16:15:14 +053021config DRAM_SUN8I_A23
22 bool
23 help
24 Select this dram controller driver for Sun8i platforms,
25 for A23 SOC.
26
Jagan Tekic335e992018-01-10 16:17:39 +053027config DRAM_SUN8I_A33
28 bool
29 help
30 Select this dram controller driver for Sun8i platforms,
31 for A33 SOC.
32
Jagan Teki0354f4b2018-01-10 16:20:26 +053033config DRAM_SUN8I_A83T
34 bool
35 help
36 Select this dram controller driver for Sun8i platforms,
37 for A83T SOC.
38
Jagan Teki7d0b1652018-03-17 00:18:01 +053039config DRAM_SUN9I
40 bool
41 help
42 Select this dram controller driver for Sun9i platforms,
43 like A80.
44
Icenowy Zhengda261652018-07-23 06:13:34 +080045config DRAM_SUN50I_H6
46 bool
47 help
48 Select this dram controller driver for some sun50i platforms,
49 like H6.
50
Jagan Teki71d9edf2018-01-11 13:21:58 +053051config SUN6I_P2WI
52 bool "Allwinner sun6i internal P2WI controller"
53 help
54 If you say yes to this option, support will be included for the
55 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
56 SOCs.
57 The P2WI looks like an SMBus controller (which supports only byte
58 accesses), except that it only supports one slave device.
59 This interface is used to connect to specific PMIC devices (like the
60 AXP221).
61
Jagan Teki2aa697a2018-01-11 13:21:15 +053062config SUN6I_PRCM
63 bool
64 help
65 Support for the PRCM (Power/Reset/Clock Management) unit available
66 in A31 SoC.
67
Jagan Teki735fb252018-02-14 22:28:30 +053068config AXP_PMIC_BUS
69 bool "Sunxi AXP PMIC bus access helpers"
70 help
71 Select this PMIC bus access helpers for Sunxi platform PRCM or other
72 AXP family PMIC devices.
73
Jagan Teki6f6f8832018-01-11 13:23:52 +053074config SUN8I_RSB
75 bool "Allwinner sunXi Reduced Serial Bus Driver"
76 help
77 Say y here to enable support for Allwinner's Reduced Serial Bus
78 (RSB) support. This controller is responsible for communicating
79 with various RSB based devices, such as AXP223, AXP8XX PMICs,
80 and AC100/AC200 ICs.
81
Icenowy Zhengcadc7c22018-07-21 16:20:20 +080082config SUNXI_SRAM_ADDRESS
83 hex
84 default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
Icenowy Zheng6f796a92018-07-21 16:20:31 +080085 default 0x20000 if MACH_SUN50I_H6
Icenowy Zhengcadc7c22018-07-21 16:20:20 +080086 default 0x0
Andre Przywarabc613d82017-02-16 01:20:23 +000087 ---help---
88 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
89 with the first SRAM region being located at address 0.
90 Some newer SoCs map the boot ROM at address 0 instead and move the
Icenowy Zhengcadc7c22018-07-21 16:20:20 +080091 SRAM to a different address.
Andre Przywarabc613d82017-02-16 01:20:23 +000092
Andre Przywarabe0d2172018-06-27 01:42:53 +010093config SUNXI_A64_TIMER_ERRATUM
94 bool
95
Hans de Goede44d8ae52015-04-06 20:33:34 +020096# Note only one of these may be selected at a time! But hidden choices are
97# not supported by Kconfig
98config SUNXI_GEN_SUN4I
99 bool
100 ---help---
101 Select this for sunxi SoCs which have resets and clocks set up
102 as the original A10 (mach-sun4i).
103
104config SUNXI_GEN_SUN6I
105 bool
106 ---help---
107 Select this for sunxi SoCs which have sun6i like periphery, like
108 separate ahb reset control registers, custom pmic bus, new style
109 watchdog, etc.
110
Icenowy Zheng9934aba2017-06-03 17:10:14 +0800111config SUNXI_DRAM_DW
112 bool
113 ---help---
114 Select this for sunxi SoCs which uses a DRAM controller like the
115 DesignWare controller used in H3, mainly SoCs after H3, which do
116 not have official open-source DRAM initialization code, but can
117 use modified H3 DRAM initialization code.
Hans de Goede44d8ae52015-04-06 20:33:34 +0200118
Icenowy Zheng87098d72017-06-03 17:10:16 +0800119if SUNXI_DRAM_DW
120config SUNXI_DRAM_DW_16BIT
121 bool
122 ---help---
123 Select this for sunxi SoCs with DesignWare DRAM controller and
124 have only 16-bit memory buswidth.
125
126config SUNXI_DRAM_DW_32BIT
127 bool
128 ---help---
129 Select this for sunxi SoCs with DesignWare DRAM controller with
130 32-bit memory buswidth.
131endif
132
Andre Przywara7b82a222017-02-16 01:20:27 +0000133config MACH_SUNXI_H3_H5
134 bool
Jernej Skrabeca05a4542017-04-27 00:03:37 +0200135 select DM_I2C
Jagan Tekidd322812018-05-07 13:03:38 +0530136 select PHY_SUN4I_USB
Jernej Skrabec1ae5def2017-03-27 19:22:31 +0200137 select SUNXI_DE2
Icenowy Zheng9934aba2017-06-03 17:10:14 +0800138 select SUNXI_DRAM_DW
Icenowy Zheng87098d72017-06-03 17:10:16 +0800139 select SUNXI_DRAM_DW_32BIT
Andre Przywara7b82a222017-02-16 01:20:27 +0000140 select SUNXI_GEN_SUN6I
141 select SUPPORT_SPL
142
Icenowy Zhengf8aa3f82018-10-25 17:23:06 +0800143# TODO: try out A80's 8GiB DRAM space
144config SUNXI_DRAM_MAX_SIZE
145 hex
146 default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
147 default 0x80000000
148
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100149choice
150 prompt "Sunxi SoC Variant"
Hans de Goede3da95362016-06-12 11:57:07 +0200151 optional
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100152
Ian Campbellc3be2792014-10-24 21:20:45 +0100153config MACH_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100154 bool "sun4i (Allwinner A10)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530155 select CPU_V7A
Andre Przywara85db5832017-02-16 01:20:21 +0000156 select ARM_CORTEX_CPU_IS_UP
Adam Sampsondf63fcc2018-06-30 01:02:29 +0100157 select DM_MMC if MMC
158 select DM_SCSI if SCSI
Jagan Tekidd322812018-05-07 13:03:38 +0530159 select PHY_SUN4I_USB
Jagan Tekidd928bf2018-01-10 16:03:34 +0530160 select DRAM_SUN4I
Hans de Goede44d8ae52015-04-06 20:33:34 +0200161 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100162 select SUPPORT_SPL
163
Ian Campbellc3be2792014-10-24 21:20:45 +0100164config MACH_SUN5I
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100165 bool "sun5i (Allwinner A13)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530166 select CPU_V7A
Andre Przywara85db5832017-02-16 01:20:21 +0000167 select ARM_CORTEX_CPU_IS_UP
Jagan Tekidd928bf2018-01-10 16:03:34 +0530168 select DRAM_SUN4I
Jagan Tekidd322812018-05-07 13:03:38 +0530169 select PHY_SUN4I_USB
Hans de Goede44d8ae52015-04-06 20:33:34 +0200170 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100171 select SUPPORT_SPL
Tom Rini6f6b7cf2018-03-06 19:02:27 -0500172 imply CONS_INDEX_2 if !DM_SERIAL
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100173
Ian Campbellc3be2792014-10-24 21:20:45 +0100174config MACH_SUN6I
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100175 bool "sun6i (Allwinner A31)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530176 select CPU_V7A
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +0800177 select CPU_V7_HAS_NONSEC
178 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +0900179 select ARCH_SUPPORT_PSCI
Jagan Tekifdfa9342018-03-17 00:16:36 +0530180 select DRAM_SUN6I
Jagan Tekidd322812018-05-07 13:03:38 +0530181 select PHY_SUN4I_USB
Jagan Teki71d9edf2018-01-11 13:21:58 +0530182 select SUN6I_P2WI
Jagan Teki2aa697a2018-01-11 13:21:15 +0530183 select SUN6I_PRCM
Hans de Goede44d8ae52015-04-06 20:33:34 +0200184 select SUNXI_GEN_SUN6I
Hans de Goede8c2c9cf2014-10-25 20:18:10 +0200185 select SUPPORT_SPL
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +0800186 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100187
Ian Campbellc3be2792014-10-24 21:20:45 +0100188config MACH_SUN7I
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100189 bool "sun7i (Allwinner A20)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530190 select CPU_V7A
Hans de Goedeea624e12014-11-14 09:34:30 +0100191 select CPU_V7_HAS_NONSEC
192 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +0900193 select ARCH_SUPPORT_PSCI
Jagan Tekidd928bf2018-01-10 16:03:34 +0530194 select DRAM_SUN4I
Jagan Tekidd322812018-05-07 13:03:38 +0530195 select PHY_SUN4I_USB
Hans de Goede44d8ae52015-04-06 20:33:34 +0200196 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100197 select SUPPORT_SPL
Hans de Goedeb366fb92014-10-24 20:12:04 +0200198 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100199
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200200config MACH_SUN8I_A23
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100201 bool "sun8i (Allwinner A23)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530202 select CPU_V7A
Chen-Yu Tsai014414f2015-05-28 21:25:34 +0800203 select CPU_V7_HAS_NONSEC
204 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +0900205 select ARCH_SUPPORT_PSCI
Jagan Tekiaf303932018-01-10 16:15:14 +0530206 select DRAM_SUN8I_A23
Jagan Tekidd322812018-05-07 13:03:38 +0530207 select PHY_SUN4I_USB
Hans de Goede44d8ae52015-04-06 20:33:34 +0200208 select SUNXI_GEN_SUN6I
Hans de Goede08fd1472014-12-07 14:34:27 +0100209 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +0800210 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Tom Rini6f6b7cf2018-03-06 19:02:27 -0500211 imply CONS_INDEX_5 if !DM_SERIAL
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100212
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +0530213config MACH_SUN8I_A33
214 bool "sun8i (Allwinner A33)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530215 select CPU_V7A
Chen-Yu Tsai014414f2015-05-28 21:25:34 +0800216 select CPU_V7_HAS_NONSEC
217 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +0900218 select ARCH_SUPPORT_PSCI
Jagan Tekic335e992018-01-10 16:17:39 +0530219 select DRAM_SUN8I_A33
Jagan Tekidd322812018-05-07 13:03:38 +0530220 select PHY_SUN4I_USB
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +0530221 select SUNXI_GEN_SUN6I
222 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +0800223 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Tom Rini6f6b7cf2018-03-06 19:02:27 -0500224 imply CONS_INDEX_5 if !DM_SERIAL
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +0530225
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800226config MACH_SUN8I_A83T
227 bool "sun8i (Allwinner A83T)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530228 select CPU_V7A
Jagan Teki0354f4b2018-01-10 16:20:26 +0530229 select DRAM_SUN8I_A83T
Jagan Tekidd322812018-05-07 13:03:38 +0530230 select PHY_SUN4I_USB
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800231 select SUNXI_GEN_SUN6I
Maxime Ripard343ff162017-08-23 12:03:42 +0200232 select MMC_SUNXI_HAS_NEW_MODE
Vasily Khoruzhick2a8882e2018-11-09 20:41:44 -0800233 select MMC_SUNXI_HAS_MODE_SWITCH
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800234 select SUPPORT_SPL
235
Jens Kuske1c27b7d2015-11-17 15:12:58 +0100236config MACH_SUN8I_H3
237 bool "sun8i (Allwinner H3)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530238 select CPU_V7A
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +0800239 select CPU_V7_HAS_NONSEC
240 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +0900241 select ARCH_SUPPORT_PSCI
Andre Przywara7b82a222017-02-16 01:20:27 +0000242 select MACH_SUNXI_H3_H5
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +0800243 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuske1c27b7d2015-11-17 15:12:58 +0100244
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800245config MACH_SUN8I_R40
246 bool "sun8i (Allwinner R40)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530247 select CPU_V7A
Chen-Yu Tsai09186482017-03-01 11:03:15 +0800248 select CPU_V7_HAS_NONSEC
249 select CPU_V7_HAS_VIRT
250 select ARCH_SUPPORT_PSCI
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800251 select SUNXI_GEN_SUN6I
Chen-Yu Tsai50ae7ae2016-12-02 16:09:49 +0800252 select SUPPORT_SPL
Icenowy Zheng9934aba2017-06-03 17:10:14 +0800253 select SUNXI_DRAM_DW
Icenowy Zheng87098d72017-06-03 17:10:16 +0800254 select SUNXI_DRAM_DW_32BIT
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800255
Icenowy Zhengc1994892017-04-08 15:30:12 +0800256config MACH_SUN8I_V3S
257 bool "sun8i (Allwinner V3s)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530258 select CPU_V7A
Icenowy Zhengc1994892017-04-08 15:30:12 +0800259 select CPU_V7_HAS_NONSEC
260 select CPU_V7_HAS_VIRT
261 select ARCH_SUPPORT_PSCI
262 select SUNXI_GEN_SUN6I
Icenowy Zheng7d06e592017-06-03 17:10:22 +0800263 select SUNXI_DRAM_DW
264 select SUNXI_DRAM_DW_16BIT
265 select SUPPORT_SPL
Icenowy Zhengc1994892017-04-08 15:30:12 +0800266 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
267
Hans de Goede1871a8c2015-01-13 19:25:06 +0100268config MACH_SUN9I
269 bool "sun9i (Allwinner A80)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530270 select CPU_V7A
Jagan Teki7d0b1652018-03-17 00:18:01 +0530271 select DRAM_SUN9I
Jagan Teki63928fa2018-01-11 13:23:02 +0530272 select SUN6I_PRCM
Hans de Goede1871a8c2015-01-13 19:25:06 +0100273 select SUNXI_GEN_SUN6I
Jagan Teki6f6f8832018-01-11 13:23:52 +0530274 select SUN8I_RSB
Philipp Tomsicha98c2962016-10-28 18:21:32 +0800275 select SUPPORT_SPL
Hans de Goede1871a8c2015-01-13 19:25:06 +0100276
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800277config MACH_SUN50I
278 bool "sun50i (Allwinner A64)"
279 select ARM64
Jernej Skrabeca05a4542017-04-27 00:03:37 +0200280 select DM_I2C
Jagan Tekidd322812018-05-07 13:03:38 +0530281 select PHY_SUN4I_USB
Vasily Khoruzhick31a4ac42018-11-05 20:24:30 -0800282 select SUN6I_PRCM
Jernej Skrabec1ae5def2017-03-27 19:22:31 +0200283 select SUNXI_DE2
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800284 select SUNXI_GEN_SUN6I
Vasily Khoruzhick0e21a2f2018-11-09 20:41:46 -0800285 select MMC_SUNXI_HAS_NEW_MODE
Andre Przywaraeb77f5c2017-01-02 11:48:45 +0000286 select SUPPORT_SPL
Icenowy Zheng9934aba2017-06-03 17:10:14 +0800287 select SUNXI_DRAM_DW
Icenowy Zheng87098d72017-06-03 17:10:16 +0800288 select SUNXI_DRAM_DW_32BIT
Andre Przywarad29adf82017-04-26 01:32:48 +0100289 select FIT
290 select SPL_LOAD_FIT
Andre Przywarabe0d2172018-06-27 01:42:53 +0100291 select SUNXI_A64_TIMER_ERRATUM
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800292
Andre Przywara997bde62017-02-16 01:20:28 +0000293config MACH_SUN50I_H5
294 bool "sun50i (Allwinner H5)"
295 select ARM64
296 select MACH_SUNXI_H3_H5
Andre Przywarad29adf82017-04-26 01:32:48 +0100297 select FIT
298 select SPL_LOAD_FIT
Andre Przywara997bde62017-02-16 01:20:28 +0000299
Icenowy Zheng6f796a92018-07-21 16:20:31 +0800300config MACH_SUN50I_H6
301 bool "sun50i (Allwinner H6)"
302 select ARM64
303 select SUPPORT_SPL
304 select FIT
305 select SPL_LOAD_FIT
306 select DRAM_SUN50I_H6
307
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100308endchoice
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800309
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200310# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
311config MACH_SUN8I
312 bool
Jagan Teki6f6f8832018-01-11 13:23:52 +0530313 select SUN8I_RSB
Jagan Teki63928fa2018-01-11 13:23:02 +0530314 select SUN6I_PRCM
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800315 default y if MACH_SUN8I_A23
316 default y if MACH_SUN8I_A33
317 default y if MACH_SUN8I_A83T
318 default y if MACH_SUNXI_H3_H5
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800319 default y if MACH_SUN8I_R40
Icenowy Zhengc1994892017-04-08 15:30:12 +0800320 default y if MACH_SUN8I_V3S
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200321
Andre Przywarab5402d12017-01-02 11:48:35 +0000322config RESERVE_ALLWINNER_BOOT0_HEADER
323 bool "reserve space for Allwinner boot0 header"
324 select ENABLE_ARM_SOC_BOOT0_HOOK
325 ---help---
326 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
327 filled with magic values post build. The Allwinner provided boot0
328 blob relies on this information to load and execute U-Boot.
329 Only needed on 64-bit Allwinner boards so far when using boot0.
330
Andre Przywara83843c92017-01-02 11:48:36 +0000331config ARM_BOOT_HOOK_RMR
332 bool
333 depends on ARM64
334 default y
335 select ENABLE_ARM_SOC_BOOT0_HOOK
336 ---help---
337 Insert some ARM32 code at the very beginning of the U-Boot binary
338 which uses an RMR register write to bring the core into AArch64 mode.
339 The very first instruction acts as a switch, since it's carefully
340 chosen to be a NOP in one mode and a branch in the other, so the
341 code would only be executed if not already in AArch64.
342 This allows both the SPL and the U-Boot proper to be entered in
343 either mode and switch to AArch64 if needed.
344
Icenowy Zhengf6457ce2017-06-03 17:10:18 +0800345if SUNXI_DRAM_DW
346config SUNXI_DRAM_DDR3
347 bool
348
Icenowy Zheng67337e62017-06-03 17:10:20 +0800349config SUNXI_DRAM_DDR2
350 bool
351
Icenowy Zheng72cc9872017-06-03 17:10:23 +0800352config SUNXI_DRAM_LPDDR3
353 bool
354
Icenowy Zhengf6457ce2017-06-03 17:10:18 +0800355choice
356 prompt "DRAM Type and Timing"
Icenowy Zheng3ec06982017-06-03 17:10:21 +0800357 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
358 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
Icenowy Zhengf6457ce2017-06-03 17:10:18 +0800359
360config SUNXI_DRAM_DDR3_1333
361 bool "DDR3 1333"
362 select SUNXI_DRAM_DDR3
Icenowy Zheng3ec06982017-06-03 17:10:21 +0800363 depends on !MACH_SUN8I_V3S
Icenowy Zhengf6457ce2017-06-03 17:10:18 +0800364 ---help---
365 This option is the original only supported memory type, which suits
366 many H3/H5/A64 boards available now.
367
Icenowy Zhengec4670a2017-06-03 17:10:24 +0800368config SUNXI_DRAM_LPDDR3_STOCK
369 bool "LPDDR3 with Allwinner stock configuration"
370 select SUNXI_DRAM_LPDDR3
371 ---help---
372 This option is the LPDDR3 timing used by the stock boot0 by
373 Allwinner.
374
Icenowy Zheng67337e62017-06-03 17:10:20 +0800375config SUNXI_DRAM_DDR2_V3S
376 bool "DDR2 found in V3s chip"
377 select SUNXI_DRAM_DDR2
Icenowy Zheng3ec06982017-06-03 17:10:21 +0800378 depends on MACH_SUN8I_V3S
Icenowy Zheng67337e62017-06-03 17:10:20 +0800379 ---help---
380 This option is only for the DDR2 memory chip which is co-packaged in
381 Allwinner V3s SoC.
382
Icenowy Zhengf6457ce2017-06-03 17:10:18 +0800383endchoice
384endif
385
Vishnu Patekarf5fd8ca2016-01-12 01:20:58 +0800386config DRAM_TYPE
387 int "sunxi dram type"
388 depends on MACH_SUN8I_A83T
389 default 3
390 ---help---
391 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200392
Hans de Goede37781a12014-11-15 19:46:39 +0100393config DRAM_CLK
Hans de Goede8ffc4872015-01-17 14:24:55 +0100394 int "sunxi dram clock speed"
Philipp Tomsich297bb9e2016-10-28 18:21:28 +0800395 default 792 if MACH_SUN9I
Chen-Yu Tsaifab03e32016-11-30 16:58:35 +0800396 default 648 if MACH_SUN8I_R40
Hans de Goede8ffc4872015-01-17 14:24:55 +0100397 default 312 if MACH_SUN6I || MACH_SUN8I
Icenowy Zheng7d06e592017-06-03 17:10:22 +0800398 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
399 MACH_SUN8I_V3S
Andre Przywara52e31822017-01-02 11:48:37 +0000400 default 672 if MACH_SUN50I
Icenowy Zheng6f796a92018-07-21 16:20:31 +0800401 default 744 if MACH_SUN50I_H6
Hans de Goede37781a12014-11-15 19:46:39 +0100402 ---help---
Philipp Tomsich297bb9e2016-10-28 18:21:28 +0800403 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
404 must be a multiple of 24. For the sun9i (A80), the tested values
405 (for DDR3-1600) are 312 to 792.
Hans de Goede37781a12014-11-15 19:46:39 +0100406
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200407if MACH_SUN5I || MACH_SUN7I
408config DRAM_MBUS_CLK
409 int "sunxi mbus clock speed"
410 default 300
411 ---help---
412 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
413
414endif
415
Hans de Goede37781a12014-11-15 19:46:39 +0100416config DRAM_ZQ
Hans de Goede8ffc4872015-01-17 14:24:55 +0100417 int "sunxi dram zq value"
418 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
419 default 127 if MACH_SUN7I
Icenowy Zheng7d06e592017-06-03 17:10:22 +0800420 default 14779 if MACH_SUN8I_V3S
Icenowy Zheng6f796a92018-07-21 16:20:31 +0800421 default 3881979 if MACH_SUN8I_R40 || MACH_SUN50I_H6
Chen-Yu Tsai58b628e2016-10-28 18:21:36 +0800422 default 4145117 if MACH_SUN9I
Andre Przywara52e31822017-01-02 11:48:37 +0000423 default 3881915 if MACH_SUN50I
Hans de Goede37781a12014-11-15 19:46:39 +0100424 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100425 Set the dram zq value.
Hans de Goede37781a12014-11-15 19:46:39 +0100426
Hans de Goede8975cdf2015-05-13 15:00:46 +0200427config DRAM_ODT_EN
428 bool "sunxi dram odt enable"
Hans de Goede8975cdf2015-05-13 15:00:46 +0200429 default y if MACH_SUN8I_A23
Chen-Yu Tsaifab03e32016-11-30 16:58:35 +0800430 default y if MACH_SUN8I_R40
Andre Przywaraeb77f5c2017-01-02 11:48:45 +0000431 default y if MACH_SUN50I
Icenowy Zheng6f796a92018-07-21 16:20:31 +0800432 default y if MACH_SUN50I_H6
Hans de Goede8975cdf2015-05-13 15:00:46 +0200433 ---help---
434 Select this to enable dram odt (on die termination).
435
Hans de Goede8ffc4872015-01-17 14:24:55 +0100436if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
437config DRAM_EMR1
438 int "sunxi dram emr1 value"
439 default 0 if MACH_SUN4I
440 default 4 if MACH_SUN5I || MACH_SUN7I
441 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100442 Set the dram controller emr1 value.
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200443
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200444config DRAM_TPR3
445 hex "sunxi dram tpr3 value"
446 default 0
447 ---help---
448 Set the dram controller tpr3 parameter. This parameter configures
449 the delay on the command lane and also phase shifts, which are
450 applied for sampling incoming read data. The default value 0
451 means that no phase/delay adjustments are necessary. Properly
452 configuring this parameter increases reliability at high DRAM
453 clock speeds.
454
455config DRAM_DQS_GATING_DELAY
456 hex "sunxi dram dqs_gating_delay value"
457 default 0
458 ---help---
459 Set the dram controller dqs_gating_delay parmeter. Each byte
460 encodes the DQS gating delay for each byte lane. The delay
461 granularity is 1/4 cycle. For example, the value 0x05060606
462 means that the delay is 5 quarter-cycles for one lane (1.25
463 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
464 The default value 0 means autodetection. The results of hardware
465 autodetection are not very reliable and depend on the chip
466 temperature (sometimes producing different results on cold start
467 and warm reboot). But the accuracy of hardware autodetection
468 is usually good enough, unless running at really high DRAM
469 clocks speeds (up to 600MHz). If unsure, keep as 0.
470
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200471choice
472 prompt "sunxi dram timings"
473 default DRAM_TIMINGS_VENDOR_MAGIC
474 ---help---
475 Select the timings of the DDR3 chips.
476
477config DRAM_TIMINGS_VENDOR_MAGIC
478 bool "Magic vendor timings from Android"
479 ---help---
480 The same DRAM timings as in the Allwinner boot0 bootloader.
481
482config DRAM_TIMINGS_DDR3_1066F_1333H
483 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
484 ---help---
485 Use the timings of the standard JEDEC DDR3-1066F speed bin for
486 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
487 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
488 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
489 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
490 that down binning to DDR3-1066F is supported (because DDR3-1066F
491 uses a bit faster timings than DDR3-1333H).
492
493config DRAM_TIMINGS_DDR3_800E_1066G_1333J
494 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
495 ---help---
496 Use the timings of the slowest possible JEDEC speed bin for the
497 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
498 DDR3-800E, DDR3-1066G or DDR3-1333J.
499
500endchoice
501
Hans de Goede37781a12014-11-15 19:46:39 +0100502endif
503
Hans de Goede8975cdf2015-05-13 15:00:46 +0200504if MACH_SUN8I_A23
505config DRAM_ODT_CORRECTION
506 int "sunxi dram odt correction value"
507 default 0
508 ---help---
509 Set the dram odt correction value (range -255 - 255). In allwinner
510 fex files, this option is found in bits 8-15 of the u32 odt_en variable
511 in the [dram] section. When bit 31 of the odt_en variable is set
512 then the correction is negative. Usually the value for this is 0.
513endif
514
Iain Patone71b4222015-03-28 10:26:38 +0000515config SYS_CLK_FREQ
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800516 default 1008000000 if MACH_SUN4I
517 default 1008000000 if MACH_SUN5I
518 default 1008000000 if MACH_SUN6I
Iain Patone71b4222015-03-28 10:26:38 +0000519 default 912000000 if MACH_SUN7I
Icenowy Zheng3cfecee2017-10-31 07:36:28 +0800520 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800521 default 1008000000 if MACH_SUN8I
522 default 1008000000 if MACH_SUN9I
Icenowy Zheng6f796a92018-07-21 16:20:31 +0800523 default 888000000 if MACH_SUN50I_H6
Iain Patone71b4222015-03-28 10:26:38 +0000524
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800525config SYS_CONFIG_NAME
Ian Campbellc3be2792014-10-24 21:20:45 +0100526 default "sun4i" if MACH_SUN4I
527 default "sun5i" if MACH_SUN5I
528 default "sun6i" if MACH_SUN6I
529 default "sun7i" if MACH_SUN7I
530 default "sun8i" if MACH_SUN8I
Hans de Goede1871a8c2015-01-13 19:25:06 +0100531 default "sun9i" if MACH_SUN9I
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200532 default "sun50i" if MACH_SUN50I
Icenowy Zheng6f796a92018-07-21 16:20:31 +0800533 default "sun50i" if MACH_SUN50I_H6
Hans de Goede6ae66f22014-08-01 09:28:24 +0200534
Masahiro Yamadadd840582014-07-30 14:08:14 +0900535config SYS_BOARD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900536 default "sunxi"
537
538config SYS_SOC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900539 default "sunxi"
540
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200541config UART0_PORT_F
542 bool "UART0 on MicroSD breakout board"
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200543 default n
544 ---help---
545 Repurpose the SD card slot for getting access to the UART0 serial
546 console. Primarily useful only for low level u-boot debugging on
547 tablets, where normal UART0 is difficult to access and requires
548 device disassembly and/or soldering. As the SD card can't be used
549 at the same time, the system can be only booted in the FEL mode.
550 Only enable this if you really know what you are doing.
551
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200552config OLD_SUNXI_KERNEL_COMPAT
Masahiro Yamadaab650062016-08-12 10:26:50 +0900553 bool "Enable workarounds for booting old kernels"
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200554 default n
555 ---help---
556 Set this to enable various workarounds for old kernels, this results in
557 sub-optimal settings for newer kernels, only enable if needed.
558
Mylène Josserandf5fd7882017-04-02 12:59:10 +0200559config MACPWR
560 string "MAC power pin"
561 default ""
562 help
563 Set the pin used to power the MAC. This takes a string in the format
564 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
565
Hans de Goedecd821132014-10-02 20:29:26 +0200566config MMC0_CD_PIN
567 string "Card detect pin for mmc0"
Andre Przywara7b82a222017-02-16 01:20:27 +0000568 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
Hans de Goedecd821132014-10-02 20:29:26 +0200569 default ""
570 ---help---
571 Set the card detect pin for mmc0, leave empty to not use cd. This
572 takes a string in the format understood by sunxi_name_to_gpio, e.g.
573 PH1 for pin 1 of port H.
574
575config MMC1_CD_PIN
576 string "Card detect pin for mmc1"
577 default ""
578 ---help---
579 See MMC0_CD_PIN help text.
580
581config MMC2_CD_PIN
582 string "Card detect pin for mmc2"
583 default ""
584 ---help---
585 See MMC0_CD_PIN help text.
586
587config MMC3_CD_PIN
588 string "Card detect pin for mmc3"
589 default ""
590 ---help---
591 See MMC0_CD_PIN help text.
592
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100593config MMC1_PINS
594 string "Pins for mmc1"
595 default ""
596 ---help---
597 Set the pins used for mmc1, when applicable. This takes a string in the
598 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
599
600config MMC2_PINS
601 string "Pins for mmc2"
602 default ""
603 ---help---
604 See MMC1_PINS help text.
605
606config MMC3_PINS
607 string "Pins for mmc3"
608 default ""
609 ---help---
610 See MMC1_PINS help text.
611
Hans de Goede2ccfac02014-10-02 20:43:50 +0200612config MMC_SUNXI_SLOT_EXTRA
613 int "mmc extra slot number"
614 default -1
615 ---help---
616 sunxi builds always enable mmc0, some boards also have a second sdcard
617 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
618 support for this.
619
Hans de Goede2c3c3ec2016-04-01 22:39:26 +0200620config INITIAL_USB_SCAN_DELAY
621 int "delay initial usb scan by x ms to allow builtin devices to init"
622 default 0
623 ---help---
624 Some boards have on board usb devices which need longer than the
625 USB spec's 1 second to connect from board powerup. Set this config
626 option to a non 0 value to add an extra delay before the first usb
627 bus scan.
628
Hans de Goede4458b7a2015-01-07 15:26:06 +0100629config USB0_VBUS_PIN
630 string "Vbus enable pin for usb0 (otg)"
631 default ""
632 ---help---
633 Set the Vbus enable pin for usb0 (otg). This takes a string in the
634 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
635
Hans de Goede52defe82015-02-16 22:13:43 +0100636config USB0_VBUS_DET
637 string "Vbus detect pin for usb0 (otg)"
Hans de Goede52defe82015-02-16 22:13:43 +0100638 default ""
639 ---help---
640 Set the Vbus detect pin for usb0 (otg). This takes a string in the
641 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
642
Hans de Goede48c06c92015-06-14 17:29:53 +0200643config USB0_ID_DET
644 string "ID detect pin for usb0 (otg)"
645 default ""
646 ---help---
647 Set the ID detect pin for usb0 (otg). This takes a string in the
648 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
649
Hans de Goede115200c2014-11-07 16:09:00 +0100650config USB1_VBUS_PIN
651 string "Vbus enable pin for usb1 (ehci0)"
652 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100653 default "PH27" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100654 ---help---
655 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
656 a string in the format understood by sunxi_name_to_gpio, e.g.
657 PH1 for pin 1 of port H.
658
659config USB2_VBUS_PIN
660 string "Vbus enable pin for usb2 (ehci1)"
661 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100662 default "PH24" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100663 ---help---
664 See USB1_VBUS_PIN help text.
665
Hans de Goede60fa6302016-03-18 08:42:01 +0100666config USB3_VBUS_PIN
667 string "Vbus enable pin for usb3 (ehci2)"
668 default ""
669 ---help---
670 See USB1_VBUS_PIN help text.
671
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200672config I2C0_ENABLE
673 bool "Enable I2C/TWI controller 0"
Chen-Yu Tsai409677e2016-11-30 15:30:30 +0800674 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200675 default n if MACH_SUN6I || MACH_SUN8I
Hans de Goede0878a8a2016-05-15 13:51:58 +0200676 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200677 ---help---
678 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
679 its clock and setting up the bus. This is especially useful on devices
680 with slaves connected to the bus or with pins exposed through e.g. an
681 expansion port/header.
682
683config I2C1_ENABLE
684 bool "Enable I2C/TWI controller 1"
685 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200686 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200687 ---help---
688 See I2C0_ENABLE help text.
689
690config I2C2_ENABLE
691 bool "Enable I2C/TWI controller 2"
692 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200693 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200694 ---help---
695 See I2C0_ENABLE help text.
696
697if MACH_SUN6I || MACH_SUN7I
698config I2C3_ENABLE
699 bool "Enable I2C/TWI controller 3"
700 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200701 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200702 ---help---
703 See I2C0_ENABLE help text.
704endif
705
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100706if SUNXI_GEN_SUN6I
Jelle van der Waa9d082682016-01-14 14:06:26 +0100707config R_I2C_ENABLE
708 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100709 # This is used for the pmic on H3
710 default y if SY8106A_POWER
Hans de Goede0878a8a2016-05-15 13:51:58 +0200711 select CMD_I2C
Jelle van der Waa9d082682016-01-14 14:06:26 +0100712 ---help---
713 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100714endif
Jelle van der Waa9d082682016-01-14 14:06:26 +0100715
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200716if MACH_SUN7I
717config I2C4_ENABLE
718 bool "Enable I2C/TWI controller 4"
719 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200720 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200721 ---help---
722 See I2C0_ENABLE help text.
723endif
724
Hans de Goede2fcf0332015-04-25 17:25:14 +0200725config AXP_GPIO
Masahiro Yamadaab650062016-08-12 10:26:50 +0900726 bool "Enable support for gpio-s on axp PMICs"
Hans de Goede2fcf0332015-04-25 17:25:14 +0200727 default n
728 ---help---
729 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
730
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800731config VIDEO_SUNXI
Masahiro Yamadaab650062016-08-12 10:26:50 +0900732 bool "Enable graphical uboot console on HDMI, LCD or VGA"
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800733 depends on !MACH_SUN8I_A83T
734 depends on !MACH_SUNXI_H3_H5
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800735 depends on !MACH_SUN8I_R40
Icenowy Zhengc1994892017-04-08 15:30:12 +0800736 depends on !MACH_SUN8I_V3S
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800737 depends on !MACH_SUN9I
738 depends on !MACH_SUN50I
Icenowy Zheng6f796a92018-07-21 16:20:31 +0800739 depends on !MACH_SUN50I_H6
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800740 select VIDEO
Icenowy Zhengf6bdddc2017-10-26 11:14:46 +0800741 imply VIDEO_DT_SIMPLEFB
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200742 default y
743 ---help---
Hans de Goede2dae8002014-12-21 16:28:32 +0100744 Say Y here to add support for using a cfb console on the HDMI, LCD
745 or VGA output found on most sunxi devices. See doc/README.video for
746 info on how to select the video output and mode.
747
Hans de Goede2fbf0912014-12-23 23:04:35 +0100748config VIDEO_HDMI
Masahiro Yamadaab650062016-08-12 10:26:50 +0900749 bool "HDMI output support"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800750 depends on VIDEO_SUNXI && !MACH_SUN8I
Hans de Goede2fbf0912014-12-23 23:04:35 +0100751 default y
752 ---help---
753 Say Y here to add support for outputting video over HDMI.
754
Hans de Goeded9786d22014-12-25 13:58:06 +0100755config VIDEO_VGA
Masahiro Yamadaab650062016-08-12 10:26:50 +0900756 bool "VGA output support"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800757 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
Hans de Goeded9786d22014-12-25 13:58:06 +0100758 default n
759 ---help---
760 Say Y here to add support for outputting video over VGA.
761
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100762config VIDEO_VGA_VIA_LCD
Masahiro Yamadaab650062016-08-12 10:26:50 +0900763 bool "VGA via LCD controller support"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800764 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100765 default n
766 ---help---
767 Say Y here to add support for external DACs connected to the parallel
768 LCD interface driving a VGA connector, such as found on the
769 Olimex A13 boards.
770
Hans de Goedefb75d972015-01-25 15:33:07 +0100771config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
Masahiro Yamadaab650062016-08-12 10:26:50 +0900772 bool "Force sync active high for VGA via LCD controller support"
Hans de Goedefb75d972015-01-25 15:33:07 +0100773 depends on VIDEO_VGA_VIA_LCD
774 default n
775 ---help---
776 Say Y here if you've a board which uses opendrain drivers for the vga
777 hsync and vsync signals. Opendrain drivers cannot generate steep enough
778 positive edges for a stable video output, so on boards with opendrain
779 drivers the sync signals must always be active high.
780
Chen-Yu Tsai507e27d2015-01-12 18:02:11 +0800781config VIDEO_VGA_EXTERNAL_DAC_EN
782 string "LCD panel power enable pin"
783 depends on VIDEO_VGA_VIA_LCD
784 default ""
785 ---help---
786 Set the enable pin for the external VGA DAC. This takes a string in the
787 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
788
Hans de Goede39920c82015-08-03 19:20:26 +0200789config VIDEO_COMPOSITE
Masahiro Yamadaab650062016-08-12 10:26:50 +0900790 bool "Composite video output support"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800791 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
Hans de Goede39920c82015-08-03 19:20:26 +0200792 default n
793 ---help---
794 Say Y here to add support for outputting composite video.
795
Hans de Goede2dae8002014-12-21 16:28:32 +0100796config VIDEO_LCD_MODE
797 string "LCD panel timing details"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800798 depends on VIDEO_SUNXI
Hans de Goede2dae8002014-12-21 16:28:32 +0100799 default ""
800 ---help---
801 LCD panel timing details string, leave empty if there is no LCD panel.
802 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
803 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede8addd3e2015-08-16 11:23:42 +0200804 Also see: http://linux-sunxi.org/LCD
Hans de Goede2dae8002014-12-21 16:28:32 +0100805
Hans de Goede65150322015-01-13 13:21:46 +0100806config VIDEO_LCD_DCLK_PHASE
807 int "LCD panel display clock phase"
Vasily Khoruzhick1d7eef32017-10-26 21:51:52 -0700808 depends on VIDEO_SUNXI || DM_VIDEO
Hans de Goede65150322015-01-13 13:21:46 +0100809 default 1
810 ---help---
811 Select LCD panel display clock phase shift, range 0-3.
812
Hans de Goede2dae8002014-12-21 16:28:32 +0100813config VIDEO_LCD_POWER
814 string "LCD panel power enable pin"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800815 depends on VIDEO_SUNXI
Hans de Goede2dae8002014-12-21 16:28:32 +0100816 default ""
817 ---help---
818 Set the power enable pin for the LCD panel. This takes a string in the
819 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
820
Hans de Goede242e3d82015-02-16 17:26:41 +0100821config VIDEO_LCD_RESET
822 string "LCD panel reset pin"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800823 depends on VIDEO_SUNXI
Hans de Goede242e3d82015-02-16 17:26:41 +0100824 default ""
825 ---help---
826 Set the reset pin for the LCD panel. This takes a string in the format
827 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
828
Hans de Goede2dae8002014-12-21 16:28:32 +0100829config VIDEO_LCD_BL_EN
830 string "LCD panel backlight enable pin"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800831 depends on VIDEO_SUNXI
Hans de Goede2dae8002014-12-21 16:28:32 +0100832 default ""
833 ---help---
834 Set the backlight enable pin for the LCD panel. This takes a string in the
835 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
836 port H.
837
838config VIDEO_LCD_BL_PWM
839 string "LCD panel backlight pwm pin"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800840 depends on VIDEO_SUNXI
Hans de Goede2dae8002014-12-21 16:28:32 +0100841 default ""
842 ---help---
843 Set the backlight pwm pin for the LCD panel. This takes a string in the
844 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200845
Hans de Goedea7403ae2015-01-22 21:02:42 +0100846config VIDEO_LCD_BL_PWM_ACTIVE_LOW
847 bool "LCD panel backlight pwm is inverted"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800848 depends on VIDEO_SUNXI
Hans de Goedea7403ae2015-01-22 21:02:42 +0100849 default y
850 ---help---
851 Set this if the backlight pwm output is active low.
852
Hans de Goede55410082015-02-16 17:23:25 +0100853config VIDEO_LCD_PANEL_I2C
854 bool "LCD panel needs to be configured via i2c"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800855 depends on VIDEO_SUNXI
Hans de Goede1fc42012015-03-07 12:00:02 +0100856 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200857 select CMD_I2C
Hans de Goede55410082015-02-16 17:23:25 +0100858 ---help---
859 Say y here if the LCD panel needs to be configured via i2c. This
860 will add a bitbang i2c controller using gpios to talk to the LCD.
861
862config VIDEO_LCD_PANEL_I2C_SDA
863 string "LCD panel i2c interface SDA pin"
864 depends on VIDEO_LCD_PANEL_I2C
865 default "PG12"
866 ---help---
867 Set the SDA pin for the LCD i2c interface. This takes a string in the
868 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
869
870config VIDEO_LCD_PANEL_I2C_SCL
871 string "LCD panel i2c interface SCL pin"
872 depends on VIDEO_LCD_PANEL_I2C
873 default "PG10"
874 ---help---
875 Set the SCL pin for the LCD i2c interface. This takes a string in the
876 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
877
Hans de Goede213480e2015-01-01 22:04:34 +0100878
879# Note only one of these may be selected at a time! But hidden choices are
880# not supported by Kconfig
881config VIDEO_LCD_IF_PARALLEL
882 bool
883
884config VIDEO_LCD_IF_LVDS
885 bool
886
Jernej Skrabec1ae5def2017-03-27 19:22:31 +0200887config SUNXI_DE2
888 bool
889 default n
890
Jernej Skrabec56009452017-03-27 19:22:32 +0200891config VIDEO_DE2
892 bool "Display Engine 2 video driver"
893 depends on SUNXI_DE2
894 select DM_VIDEO
895 select DISPLAY
Icenowy Zhengbe5b96f2017-10-26 11:14:47 +0800896 imply VIDEO_DT_SIMPLEFB
Jernej Skrabec56009452017-03-27 19:22:32 +0200897 default y
898 ---help---
899 Say y here if you want to build DE2 video driver which is present on
900 newer SoCs. Currently only HDMI output is supported.
901
Hans de Goede213480e2015-01-01 22:04:34 +0100902
903choice
904 prompt "LCD panel support"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800905 depends on VIDEO_SUNXI
Hans de Goede213480e2015-01-01 22:04:34 +0100906 ---help---
907 Select which type of LCD panel to support.
908
909config VIDEO_LCD_PANEL_PARALLEL
910 bool "Generic parallel interface LCD panel"
911 select VIDEO_LCD_IF_PARALLEL
912
913config VIDEO_LCD_PANEL_LVDS
914 bool "Generic lvds interface LCD panel"
915 select VIDEO_LCD_IF_LVDS
916
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200917config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
918 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
919 select VIDEO_LCD_SSD2828
920 select VIDEO_LCD_IF_PARALLEL
921 ---help---
Hans de Goedec1cfd512015-08-08 16:13:53 +0200922 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
923
924config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
925 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
926 select VIDEO_LCD_ANX9804
927 select VIDEO_LCD_IF_PARALLEL
928 select VIDEO_LCD_PANEL_I2C
929 ---help---
930 Select this for eDP LCD panels with 4 lanes running at 1.62G,
931 connected via an ANX9804 bridge chip.
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200932
Hans de Goede27515b22015-01-20 09:23:36 +0100933config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
934 bool "Hitachi tx18d42vm LCD panel"
935 select VIDEO_LCD_HITACHI_TX18D42VM
936 select VIDEO_LCD_IF_LVDS
937 ---help---
938 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
939
Hans de Goedeaad2ac22015-02-16 17:49:47 +0100940config VIDEO_LCD_TL059WV5C0
941 bool "tl059wv5c0 LCD panel"
942 select VIDEO_LCD_PANEL_I2C
943 select VIDEO_LCD_IF_PARALLEL
944 ---help---
945 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
946 Aigo M60/M608/M606 tablets.
947
Hans de Goede213480e2015-01-01 22:04:34 +0100948endchoice
949
Mylène Josserandd7b560e2017-04-02 12:59:09 +0200950config SATAPWR
951 string "SATA power pin"
952 default ""
953 help
954 Set the pins used to power the SATA. This takes a string in the
955 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
956 port H.
Hans de Goede213480e2015-01-01 22:04:34 +0100957
Hans de Goedec13f60d2015-01-25 12:10:48 +0100958config GMAC_TX_DELAY
959 int "GMAC Transmit Clock Delay Chain"
960 default 0
961 ---help---
962 Set the GMAC Transmit Clock Delay Chain value.
963
Hans de Goedeff42d102015-09-13 13:02:48 +0200964config SPL_STACK_R_ADDR
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800965 default 0x4fe00000 if MACH_SUN4I
966 default 0x4fe00000 if MACH_SUN5I
967 default 0x4fe00000 if MACH_SUN6I
968 default 0x4fe00000 if MACH_SUN7I
969 default 0x4fe00000 if MACH_SUN8I
Hans de Goedeff42d102015-09-13 13:02:48 +0200970 default 0x2fe00000 if MACH_SUN9I
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800971 default 0x4fe00000 if MACH_SUN50I
Icenowy Zheng6f796a92018-07-21 16:20:31 +0800972 default 0x4fe00000 if MACH_SUN50I_H6
Hans de Goedeff42d102015-09-13 13:02:48 +0200973
Jagan Tekic2a7a7e2018-02-06 22:42:56 +0530974config SPL_SPI_SUNXI
975 bool "Support for SPI Flash on Allwinner SoCs in SPL"
976 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
977 help
978 Enable support for SPI Flash. This option allows SPL to read from
979 sunxi SPI Flash. It uses the same method as the boot ROM, so does
980 not need any extra configuration.
981
Icenowy Zhengc6c2c852018-10-25 17:23:02 +0800982config PINE64_DT_SELECTION
983 bool "Enable Pine64 device tree selection code"
984 depends on MACH_SUN50I
985 help
986 The original Pine A64 and Pine A64+ are similar but different
987 boards and can be differed by the DRAM size. Pine A64 has
988 512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
989 option, the device tree selection code specific to Pine64 which
990 utilizes the DRAM size will be enabled.
991
Masahiro Yamadadd840582014-07-30 14:08:14 +0900992endif