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Ian Campbell2c7e3b92014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Hans de Goede44d8ae52015-04-06 20:33:34 +02003# Note only one of these may be selected at a time! But hidden choices are
4# not supported by Kconfig
5config SUNXI_GEN_SUN4I
6 bool
7 ---help---
8 Select this for sunxi SoCs which have resets and clocks set up
9 as the original A10 (mach-sun4i).
10
11config SUNXI_GEN_SUN6I
12 bool
13 ---help---
14 Select this for sunxi SoCs which have sun6i like periphery, like
15 separate ahb reset control registers, custom pmic bus, new style
16 watchdog, etc.
17
18
Ian Campbell2c7e3b92014-10-24 21:20:44 +010019choice
20 prompt "Sunxi SoC Variant"
21
Ian Campbellc3be2792014-10-24 21:20:45 +010022config MACH_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010023 bool "sun4i (Allwinner A10)"
24 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020025 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010026 select SUPPORT_SPL
27
Ian Campbellc3be2792014-10-24 21:20:45 +010028config MACH_SUN5I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010029 bool "sun5i (Allwinner A13)"
30 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020031 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010032 select SUPPORT_SPL
33
Ian Campbellc3be2792014-10-24 21:20:45 +010034config MACH_SUN6I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010035 bool "sun6i (Allwinner A31)"
36 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020037 select SUNXI_GEN_SUN6I
Hans de Goede8c2c9cf2014-10-25 20:18:10 +020038 select SUPPORT_SPL
Ian Campbell2c7e3b92014-10-24 21:20:44 +010039
Ian Campbellc3be2792014-10-24 21:20:45 +010040config MACH_SUN7I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010041 bool "sun7i (Allwinner A20)"
42 select CPU_V7
Hans de Goedeea624e12014-11-14 09:34:30 +010043 select CPU_V7_HAS_NONSEC
44 select CPU_V7_HAS_VIRT
Hans de Goede44d8ae52015-04-06 20:33:34 +020045 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010046 select SUPPORT_SPL
Hans de Goedeb366fb92014-10-24 20:12:04 +020047 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010048
Hans de Goede5e6bacd2015-04-06 20:55:39 +020049config MACH_SUN8I_A23
Ian Campbell2c7e3b92014-10-24 21:20:44 +010050 bool "sun8i (Allwinner A23)"
51 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020052 select SUNXI_GEN_SUN6I
Hans de Goede08fd1472014-12-07 14:34:27 +010053 select SUPPORT_SPL
Ian Campbell2c7e3b92014-10-24 21:20:44 +010054
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053055config MACH_SUN8I_A33
56 bool "sun8i (Allwinner A33)"
57 select CPU_V7
58 select SUNXI_GEN_SUN6I
59 select SUPPORT_SPL
60
Ian Campbell2c7e3b92014-10-24 21:20:44 +010061endchoice
Maxime Ripard8a6564d2014-10-03 20:16:29 +080062
Hans de Goede5e6bacd2015-04-06 20:55:39 +020063# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
64config MACH_SUN8I
65 bool
66 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33
67
68
Hans de Goede37781a12014-11-15 19:46:39 +010069config DRAM_CLK
Hans de Goede8ffc4872015-01-17 14:24:55 +010070 int "sunxi dram clock speed"
71 default 312 if MACH_SUN6I || MACH_SUN8I
72 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +010073 ---help---
74 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goedee1a08882015-01-25 11:29:27 +010075 of 24.
Hans de Goede37781a12014-11-15 19:46:39 +010076
Siarhei Siamashka47e35012015-02-01 00:27:06 +020077if MACH_SUN5I || MACH_SUN7I
78config DRAM_MBUS_CLK
79 int "sunxi mbus clock speed"
80 default 300
81 ---help---
82 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
83
84endif
85
Hans de Goede37781a12014-11-15 19:46:39 +010086config DRAM_ZQ
Hans de Goede8ffc4872015-01-17 14:24:55 +010087 int "sunxi dram zq value"
88 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
89 default 127 if MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +010090 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +010091 Set the dram zq value.
Hans de Goede37781a12014-11-15 19:46:39 +010092
Hans de Goede8ffc4872015-01-17 14:24:55 +010093if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
94config DRAM_EMR1
95 int "sunxi dram emr1 value"
96 default 0 if MACH_SUN4I
97 default 4 if MACH_SUN5I || MACH_SUN7I
98 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +010099 Set the dram controller emr1 value.
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200100
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200101config DRAM_ODT_EN
102 int "sunxi dram odt_en value"
103 default 0
104 ---help---
105 Set the dram controller odt_en parameter. This can be used to
106 enable/disable the ODT feature.
107
108config DRAM_TPR3
109 hex "sunxi dram tpr3 value"
110 default 0
111 ---help---
112 Set the dram controller tpr3 parameter. This parameter configures
113 the delay on the command lane and also phase shifts, which are
114 applied for sampling incoming read data. The default value 0
115 means that no phase/delay adjustments are necessary. Properly
116 configuring this parameter increases reliability at high DRAM
117 clock speeds.
118
119config DRAM_DQS_GATING_DELAY
120 hex "sunxi dram dqs_gating_delay value"
121 default 0
122 ---help---
123 Set the dram controller dqs_gating_delay parmeter. Each byte
124 encodes the DQS gating delay for each byte lane. The delay
125 granularity is 1/4 cycle. For example, the value 0x05060606
126 means that the delay is 5 quarter-cycles for one lane (1.25
127 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
128 The default value 0 means autodetection. The results of hardware
129 autodetection are not very reliable and depend on the chip
130 temperature (sometimes producing different results on cold start
131 and warm reboot). But the accuracy of hardware autodetection
132 is usually good enough, unless running at really high DRAM
133 clocks speeds (up to 600MHz). If unsure, keep as 0.
134
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200135choice
136 prompt "sunxi dram timings"
137 default DRAM_TIMINGS_VENDOR_MAGIC
138 ---help---
139 Select the timings of the DDR3 chips.
140
141config DRAM_TIMINGS_VENDOR_MAGIC
142 bool "Magic vendor timings from Android"
143 ---help---
144 The same DRAM timings as in the Allwinner boot0 bootloader.
145
146config DRAM_TIMINGS_DDR3_1066F_1333H
147 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
148 ---help---
149 Use the timings of the standard JEDEC DDR3-1066F speed bin for
150 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
151 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
152 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
153 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
154 that down binning to DDR3-1066F is supported (because DDR3-1066F
155 uses a bit faster timings than DDR3-1333H).
156
157config DRAM_TIMINGS_DDR3_800E_1066G_1333J
158 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
159 ---help---
160 Use the timings of the slowest possible JEDEC speed bin for the
161 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
162 DDR3-800E, DDR3-1066G or DDR3-1333J.
163
164endchoice
165
Hans de Goede37781a12014-11-15 19:46:39 +0100166endif
167
Iain Patone71b4222015-03-28 10:26:38 +0000168config SYS_CLK_FREQ
169 default 912000000 if MACH_SUN7I
170 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
171
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800172config SYS_CONFIG_NAME
Ian Campbellc3be2792014-10-24 21:20:45 +0100173 default "sun4i" if MACH_SUN4I
174 default "sun5i" if MACH_SUN5I
175 default "sun6i" if MACH_SUN6I
176 default "sun7i" if MACH_SUN7I
177 default "sun8i" if MACH_SUN8I
Hans de Goede6ae66f22014-08-01 09:28:24 +0200178
Masahiro Yamadadd840582014-07-30 14:08:14 +0900179config SYS_BOARD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900180 default "sunxi"
181
182config SYS_SOC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900183 default "sunxi"
184
Ian Campbell4ce99412014-10-24 21:20:46 +0100185config SPL_FEL
186 bool "SPL/FEL mode support"
187 depends on SPL
188 default n
Simon Glass942cb0b2015-02-07 10:47:30 -0700189 help
190 This enables support for Fast Early Loader (FEL) mode. This
191 allows U-Boot to be loaded to the board over USB by the on-chip
192 boot rom. U-Boot should be sent in two parts: SPL first, with
193 'fel write 0x2000 u-boot-spl.bin; fel exe 0x2000' then U-Boot with
194 'fel write 0x4a000000 u-boot.bin; fel exe 0x4a000000'. This option
195 shrinks the amount of SRAM available to SPL, so only enable it if
196 you need FEL. Note that enabling this option only allows FEL to be
197 used; it is still possible to boot U-Boot from boot media. U-Boot
198 SPL detects when it is being loaded using FEL.
Ian Campbell4ce99412014-10-24 21:20:46 +0100199
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200200config UART0_PORT_F
201 bool "UART0 on MicroSD breakout board"
202 depends on SPL_FEL
203 default n
204 ---help---
205 Repurpose the SD card slot for getting access to the UART0 serial
206 console. Primarily useful only for low level u-boot debugging on
207 tablets, where normal UART0 is difficult to access and requires
208 device disassembly and/or soldering. As the SD card can't be used
209 at the same time, the system can be only booted in the FEL mode.
210 Only enable this if you really know what you are doing.
211
Ian Campbell98e214d2014-08-31 13:13:43 +0100212config FDTFILE
213 string "Default fdtfile env setting for this board"
Hans de Goede846e3252014-08-01 09:37:58 +0200214
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200215config OLD_SUNXI_KERNEL_COMPAT
216 boolean "Enable workarounds for booting old kernels"
217 default n
218 ---help---
219 Set this to enable various workarounds for old kernels, this results in
220 sub-optimal settings for newer kernels, only enable if needed.
221
Hans de Goedecd821132014-10-02 20:29:26 +0200222config MMC0_CD_PIN
223 string "Card detect pin for mmc0"
224 default ""
225 ---help---
226 Set the card detect pin for mmc0, leave empty to not use cd. This
227 takes a string in the format understood by sunxi_name_to_gpio, e.g.
228 PH1 for pin 1 of port H.
229
230config MMC1_CD_PIN
231 string "Card detect pin for mmc1"
232 default ""
233 ---help---
234 See MMC0_CD_PIN help text.
235
236config MMC2_CD_PIN
237 string "Card detect pin for mmc2"
238 default ""
239 ---help---
240 See MMC0_CD_PIN help text.
241
242config MMC3_CD_PIN
243 string "Card detect pin for mmc3"
244 default ""
245 ---help---
246 See MMC0_CD_PIN help text.
247
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100248config MMC1_PINS
249 string "Pins for mmc1"
250 default ""
251 ---help---
252 Set the pins used for mmc1, when applicable. This takes a string in the
253 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
254
255config MMC2_PINS
256 string "Pins for mmc2"
257 default ""
258 ---help---
259 See MMC1_PINS help text.
260
261config MMC3_PINS
262 string "Pins for mmc3"
263 default ""
264 ---help---
265 See MMC1_PINS help text.
266
Hans de Goede2ccfac02014-10-02 20:43:50 +0200267config MMC_SUNXI_SLOT_EXTRA
268 int "mmc extra slot number"
269 default -1
270 ---help---
271 sunxi builds always enable mmc0, some boards also have a second sdcard
272 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
273 support for this.
274
Hans de Goede4458b7a2015-01-07 15:26:06 +0100275config USB0_VBUS_PIN
276 string "Vbus enable pin for usb0 (otg)"
277 default ""
278 ---help---
279 Set the Vbus enable pin for usb0 (otg). This takes a string in the
280 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
281
Hans de Goede52defe82015-02-16 22:13:43 +0100282config USB0_VBUS_DET
283 string "Vbus detect pin for usb0 (otg)"
Hans de Goede52defe82015-02-16 22:13:43 +0100284 default ""
285 ---help---
286 Set the Vbus detect pin for usb0 (otg). This takes a string in the
287 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
288
Hans de Goede115200c2014-11-07 16:09:00 +0100289config USB1_VBUS_PIN
290 string "Vbus enable pin for usb1 (ehci0)"
291 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100292 default "PH27" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100293 ---help---
294 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
295 a string in the format understood by sunxi_name_to_gpio, e.g.
296 PH1 for pin 1 of port H.
297
298config USB2_VBUS_PIN
299 string "Vbus enable pin for usb2 (ehci1)"
300 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100301 default "PH24" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100302 ---help---
303 See USB1_VBUS_PIN help text.
304
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200305config I2C0_ENABLE
306 bool "Enable I2C/TWI controller 0"
307 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
308 default n if MACH_SUN6I || MACH_SUN8I
309 ---help---
310 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
311 its clock and setting up the bus. This is especially useful on devices
312 with slaves connected to the bus or with pins exposed through e.g. an
313 expansion port/header.
314
315config I2C1_ENABLE
316 bool "Enable I2C/TWI controller 1"
317 default n
318 ---help---
319 See I2C0_ENABLE help text.
320
321config I2C2_ENABLE
322 bool "Enable I2C/TWI controller 2"
323 default n
324 ---help---
325 See I2C0_ENABLE help text.
326
327if MACH_SUN6I || MACH_SUN7I
328config I2C3_ENABLE
329 bool "Enable I2C/TWI controller 3"
330 default n
331 ---help---
332 See I2C0_ENABLE help text.
333endif
334
335if MACH_SUN7I
336config I2C4_ENABLE
337 bool "Enable I2C/TWI controller 4"
338 default n
339 ---help---
340 See I2C0_ENABLE help text.
341endif
342
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200343config VIDEO
Hans de Goede2dae8002014-12-21 16:28:32 +0100344 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200345 default y
346 ---help---
Hans de Goede2dae8002014-12-21 16:28:32 +0100347 Say Y here to add support for using a cfb console on the HDMI, LCD
348 or VGA output found on most sunxi devices. See doc/README.video for
349 info on how to select the video output and mode.
350
Hans de Goede2fbf0912014-12-23 23:04:35 +0100351config VIDEO_HDMI
352 boolean "HDMI output support"
353 depends on VIDEO && !MACH_SUN8I
354 default y
355 ---help---
356 Say Y here to add support for outputting video over HDMI.
357
Hans de Goeded9786d22014-12-25 13:58:06 +0100358config VIDEO_VGA
359 boolean "VGA output support"
360 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
361 default n
362 ---help---
363 Say Y here to add support for outputting video over VGA.
364
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100365config VIDEO_VGA_VIA_LCD
366 boolean "VGA via LCD controller support"
Chen-Yu Tsai2583d5b2015-01-12 18:02:10 +0800367 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100368 default n
369 ---help---
370 Say Y here to add support for external DACs connected to the parallel
371 LCD interface driving a VGA connector, such as found on the
372 Olimex A13 boards.
373
Hans de Goedefb75d972015-01-25 15:33:07 +0100374config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
375 boolean "Force sync active high for VGA via LCD controller support"
376 depends on VIDEO_VGA_VIA_LCD
377 default n
378 ---help---
379 Say Y here if you've a board which uses opendrain drivers for the vga
380 hsync and vsync signals. Opendrain drivers cannot generate steep enough
381 positive edges for a stable video output, so on boards with opendrain
382 drivers the sync signals must always be active high.
383
Chen-Yu Tsai507e27d2015-01-12 18:02:11 +0800384config VIDEO_VGA_EXTERNAL_DAC_EN
385 string "LCD panel power enable pin"
386 depends on VIDEO_VGA_VIA_LCD
387 default ""
388 ---help---
389 Set the enable pin for the external VGA DAC. This takes a string in the
390 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
391
Hans de Goede2dae8002014-12-21 16:28:32 +0100392config VIDEO_LCD_MODE
393 string "LCD panel timing details"
394 depends on VIDEO
395 default ""
396 ---help---
397 LCD panel timing details string, leave empty if there is no LCD panel.
398 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
399 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
400
Hans de Goede65150322015-01-13 13:21:46 +0100401config VIDEO_LCD_DCLK_PHASE
402 int "LCD panel display clock phase"
403 depends on VIDEO
404 default 1
405 ---help---
406 Select LCD panel display clock phase shift, range 0-3.
407
Hans de Goede2dae8002014-12-21 16:28:32 +0100408config VIDEO_LCD_POWER
409 string "LCD panel power enable pin"
410 depends on VIDEO
411 default ""
412 ---help---
413 Set the power enable pin for the LCD panel. This takes a string in the
414 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
415
Hans de Goede242e3d82015-02-16 17:26:41 +0100416config VIDEO_LCD_RESET
417 string "LCD panel reset pin"
418 depends on VIDEO
419 default ""
420 ---help---
421 Set the reset pin for the LCD panel. This takes a string in the format
422 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
423
Hans de Goede2dae8002014-12-21 16:28:32 +0100424config VIDEO_LCD_BL_EN
425 string "LCD panel backlight enable pin"
426 depends on VIDEO
427 default ""
428 ---help---
429 Set the backlight enable pin for the LCD panel. This takes a string in the
430 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
431 port H.
432
433config VIDEO_LCD_BL_PWM
434 string "LCD panel backlight pwm pin"
435 depends on VIDEO
436 default ""
437 ---help---
438 Set the backlight pwm pin for the LCD panel. This takes a string in the
439 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200440
Hans de Goedea7403ae2015-01-22 21:02:42 +0100441config VIDEO_LCD_BL_PWM_ACTIVE_LOW
442 bool "LCD panel backlight pwm is inverted"
443 depends on VIDEO
444 default y
445 ---help---
446 Set this if the backlight pwm output is active low.
447
Hans de Goede55410082015-02-16 17:23:25 +0100448config VIDEO_LCD_PANEL_I2C
449 bool "LCD panel needs to be configured via i2c"
450 depends on VIDEO
Hans de Goede1fc42012015-03-07 12:00:02 +0100451 default n
Hans de Goede55410082015-02-16 17:23:25 +0100452 ---help---
453 Say y here if the LCD panel needs to be configured via i2c. This
454 will add a bitbang i2c controller using gpios to talk to the LCD.
455
456config VIDEO_LCD_PANEL_I2C_SDA
457 string "LCD panel i2c interface SDA pin"
458 depends on VIDEO_LCD_PANEL_I2C
459 default "PG12"
460 ---help---
461 Set the SDA pin for the LCD i2c interface. This takes a string in the
462 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
463
464config VIDEO_LCD_PANEL_I2C_SCL
465 string "LCD panel i2c interface SCL pin"
466 depends on VIDEO_LCD_PANEL_I2C
467 default "PG10"
468 ---help---
469 Set the SCL pin for the LCD i2c interface. This takes a string in the
470 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
471
Hans de Goede213480e2015-01-01 22:04:34 +0100472
473# Note only one of these may be selected at a time! But hidden choices are
474# not supported by Kconfig
475config VIDEO_LCD_IF_PARALLEL
476 bool
477
478config VIDEO_LCD_IF_LVDS
479 bool
480
481
482choice
483 prompt "LCD panel support"
484 depends on VIDEO
485 ---help---
486 Select which type of LCD panel to support.
487
488config VIDEO_LCD_PANEL_PARALLEL
489 bool "Generic parallel interface LCD panel"
490 select VIDEO_LCD_IF_PARALLEL
491
492config VIDEO_LCD_PANEL_LVDS
493 bool "Generic lvds interface LCD panel"
494 select VIDEO_LCD_IF_LVDS
495
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200496config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
497 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
498 select VIDEO_LCD_SSD2828
499 select VIDEO_LCD_IF_PARALLEL
500 ---help---
501 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
502
Hans de Goede27515b22015-01-20 09:23:36 +0100503config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
504 bool "Hitachi tx18d42vm LCD panel"
505 select VIDEO_LCD_HITACHI_TX18D42VM
506 select VIDEO_LCD_IF_LVDS
507 ---help---
508 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
509
Hans de Goedeaad2ac22015-02-16 17:49:47 +0100510config VIDEO_LCD_TL059WV5C0
511 bool "tl059wv5c0 LCD panel"
512 select VIDEO_LCD_PANEL_I2C
513 select VIDEO_LCD_IF_PARALLEL
514 ---help---
515 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
516 Aigo M60/M608/M606 tablets.
517
Hans de Goede213480e2015-01-01 22:04:34 +0100518endchoice
519
520
Hans de Goede1a800f72015-01-11 17:17:00 +0100521config USB_MUSB_SUNXI
522 bool "Enable sunxi OTG / DRC USB controller in host mode"
523 default n
524 ---help---
525 Say y here to enable support for the sunxi OTG / DRC USB controller
526 used on almost all sunxi boards. Note currently u-boot can only have
527 one usb host controller enabled at a time, so enabling this on boards
528 which also use the ehci host controller will result in build errors.
529
Hans de Goede86b49092014-09-18 21:03:34 +0200530config USB_KEYBOARD
531 boolean "Enable USB keyboard support"
532 default y
533 ---help---
534 Say Y here to add support for using a USB keyboard (typically used
Hans de Goede2dae8002014-12-21 16:28:32 +0100535 in combination with a graphical console).
Hans de Goede86b49092014-09-18 21:03:34 +0200536
Hans de Goedec13f60d2015-01-25 12:10:48 +0100537config GMAC_TX_DELAY
538 int "GMAC Transmit Clock Delay Chain"
539 default 0
540 ---help---
541 Set the GMAC Transmit Clock Delay Chain value.
542
Masahiro Yamadadd840582014-07-30 14:08:14 +0900543endif