blob: 3c29fc61f76c3549feeb27a10c90ef898eb91521 [file] [log] [blame]
Ian Campbell2c7e3b92014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Philipp Tomsichb5299932017-08-03 23:23:55 +02003config SPL_LDSCRIPT
4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
5
Siva Durga Prasad Paladugua4d88922016-07-29 15:31:47 +05306config IDENT_STRING
7 default " Allwinner Technology"
8
Andre Przywarabc613d82017-02-16 01:20:23 +00009config SUNXI_HIGH_SRAM
10 bool
11 default n
12 ---help---
13 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
14 with the first SRAM region being located at address 0.
15 Some newer SoCs map the boot ROM at address 0 instead and move the
16 SRAM to 64KB, just behind the mask ROM.
17 Chips using the latter setup are supposed to select this option to
18 adjust the addresses accordingly.
19
Hans de Goede44d8ae52015-04-06 20:33:34 +020020# Note only one of these may be selected at a time! But hidden choices are
21# not supported by Kconfig
22config SUNXI_GEN_SUN4I
23 bool
24 ---help---
25 Select this for sunxi SoCs which have resets and clocks set up
26 as the original A10 (mach-sun4i).
27
28config SUNXI_GEN_SUN6I
29 bool
30 ---help---
31 Select this for sunxi SoCs which have sun6i like periphery, like
32 separate ahb reset control registers, custom pmic bus, new style
33 watchdog, etc.
34
Icenowy Zheng9934aba2017-06-03 17:10:14 +080035config SUNXI_DRAM_DW
36 bool
37 ---help---
38 Select this for sunxi SoCs which uses a DRAM controller like the
39 DesignWare controller used in H3, mainly SoCs after H3, which do
40 not have official open-source DRAM initialization code, but can
41 use modified H3 DRAM initialization code.
Hans de Goede44d8ae52015-04-06 20:33:34 +020042
Icenowy Zheng87098d72017-06-03 17:10:16 +080043if SUNXI_DRAM_DW
44config SUNXI_DRAM_DW_16BIT
45 bool
46 ---help---
47 Select this for sunxi SoCs with DesignWare DRAM controller and
48 have only 16-bit memory buswidth.
49
50config SUNXI_DRAM_DW_32BIT
51 bool
52 ---help---
53 Select this for sunxi SoCs with DesignWare DRAM controller with
54 32-bit memory buswidth.
55endif
56
Andre Przywara7b82a222017-02-16 01:20:27 +000057config MACH_SUNXI_H3_H5
58 bool
Jernej Skrabeca05a4542017-04-27 00:03:37 +020059 select DM_I2C
Jernej Skrabec1ae5def2017-03-27 19:22:31 +020060 select SUNXI_DE2
Icenowy Zheng9934aba2017-06-03 17:10:14 +080061 select SUNXI_DRAM_DW
Icenowy Zheng87098d72017-06-03 17:10:16 +080062 select SUNXI_DRAM_DW_32BIT
Andre Przywara7b82a222017-02-16 01:20:27 +000063 select SUNXI_GEN_SUN6I
64 select SUPPORT_SPL
65
Ian Campbell2c7e3b92014-10-24 21:20:44 +010066choice
67 prompt "Sunxi SoC Variant"
Hans de Goede3da95362016-06-12 11:57:07 +020068 optional
Ian Campbell2c7e3b92014-10-24 21:20:44 +010069
Ian Campbellc3be2792014-10-24 21:20:45 +010070config MACH_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010071 bool "sun4i (Allwinner A10)"
72 select CPU_V7
Andre Przywara85db5832017-02-16 01:20:21 +000073 select ARM_CORTEX_CPU_IS_UP
Hans de Goede44d8ae52015-04-06 20:33:34 +020074 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010075 select SUPPORT_SPL
76
Ian Campbellc3be2792014-10-24 21:20:45 +010077config MACH_SUN5I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010078 bool "sun5i (Allwinner A13)"
79 select CPU_V7
Andre Przywara85db5832017-02-16 01:20:21 +000080 select ARM_CORTEX_CPU_IS_UP
Hans de Goede44d8ae52015-04-06 20:33:34 +020081 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010082 select SUPPORT_SPL
83
Ian Campbellc3be2792014-10-24 21:20:45 +010084config MACH_SUN6I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010085 bool "sun6i (Allwinner A31)"
86 select CPU_V7
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080087 select CPU_V7_HAS_NONSEC
88 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090089 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020090 select SUNXI_GEN_SUN6I
Hans de Goede8c2c9cf2014-10-25 20:18:10 +020091 select SUPPORT_SPL
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080092 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010093
Ian Campbellc3be2792014-10-24 21:20:45 +010094config MACH_SUN7I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010095 bool "sun7i (Allwinner A20)"
96 select CPU_V7
Hans de Goedeea624e12014-11-14 09:34:30 +010097 select CPU_V7_HAS_NONSEC
98 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090099 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +0200100 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100101 select SUPPORT_SPL
Hans de Goedeb366fb92014-10-24 20:12:04 +0200102 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100103
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200104config MACH_SUN8I_A23
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100105 bool "sun8i (Allwinner A23)"
106 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +0800107 select CPU_V7_HAS_NONSEC
108 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +0900109 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +0200110 select SUNXI_GEN_SUN6I
Hans de Goede08fd1472014-12-07 14:34:27 +0100111 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +0800112 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100113
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +0530114config MACH_SUN8I_A33
115 bool "sun8i (Allwinner A33)"
116 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +0800117 select CPU_V7_HAS_NONSEC
118 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +0900119 select ARCH_SUPPORT_PSCI
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +0530120 select SUNXI_GEN_SUN6I
121 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +0800122 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +0530123
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800124config MACH_SUN8I_A83T
125 bool "sun8i (Allwinner A83T)"
126 select CPU_V7
127 select SUNXI_GEN_SUN6I
Maxime Ripard343ff162017-08-23 12:03:42 +0200128 select MMC_SUNXI_HAS_NEW_MODE
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800129 select SUPPORT_SPL
130
Jens Kuske1c27b7d2015-11-17 15:12:58 +0100131config MACH_SUN8I_H3
132 bool "sun8i (Allwinner H3)"
133 select CPU_V7
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +0800134 select CPU_V7_HAS_NONSEC
135 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +0900136 select ARCH_SUPPORT_PSCI
Andre Przywara7b82a222017-02-16 01:20:27 +0000137 select MACH_SUNXI_H3_H5
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +0800138 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuske1c27b7d2015-11-17 15:12:58 +0100139
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800140config MACH_SUN8I_R40
141 bool "sun8i (Allwinner R40)"
142 select CPU_V7
Chen-Yu Tsai09186482017-03-01 11:03:15 +0800143 select CPU_V7_HAS_NONSEC
144 select CPU_V7_HAS_VIRT
145 select ARCH_SUPPORT_PSCI
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800146 select SUNXI_GEN_SUN6I
Chen-Yu Tsai50ae7ae2016-12-02 16:09:49 +0800147 select SUPPORT_SPL
Icenowy Zheng9934aba2017-06-03 17:10:14 +0800148 select SUNXI_DRAM_DW
Icenowy Zheng87098d72017-06-03 17:10:16 +0800149 select SUNXI_DRAM_DW_32BIT
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800150
Icenowy Zhengc1994892017-04-08 15:30:12 +0800151config MACH_SUN8I_V3S
152 bool "sun8i (Allwinner V3s)"
153 select CPU_V7
154 select CPU_V7_HAS_NONSEC
155 select CPU_V7_HAS_VIRT
156 select ARCH_SUPPORT_PSCI
157 select SUNXI_GEN_SUN6I
Icenowy Zheng7d06e592017-06-03 17:10:22 +0800158 select SUNXI_DRAM_DW
159 select SUNXI_DRAM_DW_16BIT
160 select SUPPORT_SPL
Icenowy Zhengc1994892017-04-08 15:30:12 +0800161 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
162
Hans de Goede1871a8c2015-01-13 19:25:06 +0100163config MACH_SUN9I
164 bool "sun9i (Allwinner A80)"
165 select CPU_V7
Andre Przywarabc613d82017-02-16 01:20:23 +0000166 select SUNXI_HIGH_SRAM
Hans de Goede1871a8c2015-01-13 19:25:06 +0100167 select SUNXI_GEN_SUN6I
Philipp Tomsicha98c2962016-10-28 18:21:32 +0800168 select SUPPORT_SPL
Hans de Goede1871a8c2015-01-13 19:25:06 +0100169
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800170config MACH_SUN50I
171 bool "sun50i (Allwinner A64)"
172 select ARM64
Jernej Skrabeca05a4542017-04-27 00:03:37 +0200173 select DM_I2C
Jernej Skrabec1ae5def2017-03-27 19:22:31 +0200174 select SUNXI_DE2
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800175 select SUNXI_GEN_SUN6I
Andre Przywarabc613d82017-02-16 01:20:23 +0000176 select SUNXI_HIGH_SRAM
Andre Przywaraeb77f5c2017-01-02 11:48:45 +0000177 select SUPPORT_SPL
Icenowy Zheng9934aba2017-06-03 17:10:14 +0800178 select SUNXI_DRAM_DW
Icenowy Zheng87098d72017-06-03 17:10:16 +0800179 select SUNXI_DRAM_DW_32BIT
Andre Przywarad29adf82017-04-26 01:32:48 +0100180 select FIT
181 select SPL_LOAD_FIT
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800182
Andre Przywara997bde62017-02-16 01:20:28 +0000183config MACH_SUN50I_H5
184 bool "sun50i (Allwinner H5)"
185 select ARM64
186 select MACH_SUNXI_H3_H5
187 select SUNXI_HIGH_SRAM
Andre Przywarad29adf82017-04-26 01:32:48 +0100188 select FIT
189 select SPL_LOAD_FIT
Andre Przywara997bde62017-02-16 01:20:28 +0000190
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100191endchoice
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800192
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200193# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
194config MACH_SUN8I
195 bool
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800196 default y if MACH_SUN8I_A23
197 default y if MACH_SUN8I_A33
198 default y if MACH_SUN8I_A83T
199 default y if MACH_SUNXI_H3_H5
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800200 default y if MACH_SUN8I_R40
Icenowy Zhengc1994892017-04-08 15:30:12 +0800201 default y if MACH_SUN8I_V3S
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200202
Andre Przywarab5402d12017-01-02 11:48:35 +0000203config RESERVE_ALLWINNER_BOOT0_HEADER
204 bool "reserve space for Allwinner boot0 header"
205 select ENABLE_ARM_SOC_BOOT0_HOOK
206 ---help---
207 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
208 filled with magic values post build. The Allwinner provided boot0
209 blob relies on this information to load and execute U-Boot.
210 Only needed on 64-bit Allwinner boards so far when using boot0.
211
Andre Przywara83843c92017-01-02 11:48:36 +0000212config ARM_BOOT_HOOK_RMR
213 bool
214 depends on ARM64
215 default y
216 select ENABLE_ARM_SOC_BOOT0_HOOK
217 ---help---
218 Insert some ARM32 code at the very beginning of the U-Boot binary
219 which uses an RMR register write to bring the core into AArch64 mode.
220 The very first instruction acts as a switch, since it's carefully
221 chosen to be a NOP in one mode and a branch in the other, so the
222 code would only be executed if not already in AArch64.
223 This allows both the SPL and the U-Boot proper to be entered in
224 either mode and switch to AArch64 if needed.
225
Icenowy Zhengf6457ce2017-06-03 17:10:18 +0800226if SUNXI_DRAM_DW
227config SUNXI_DRAM_DDR3
228 bool
229
Icenowy Zheng67337e62017-06-03 17:10:20 +0800230config SUNXI_DRAM_DDR2
231 bool
232
Icenowy Zheng72cc9872017-06-03 17:10:23 +0800233config SUNXI_DRAM_LPDDR3
234 bool
235
Icenowy Zhengf6457ce2017-06-03 17:10:18 +0800236choice
237 prompt "DRAM Type and Timing"
Icenowy Zheng3ec06982017-06-03 17:10:21 +0800238 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
239 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
Icenowy Zhengf6457ce2017-06-03 17:10:18 +0800240
241config SUNXI_DRAM_DDR3_1333
242 bool "DDR3 1333"
243 select SUNXI_DRAM_DDR3
Icenowy Zheng3ec06982017-06-03 17:10:21 +0800244 depends on !MACH_SUN8I_V3S
Icenowy Zhengf6457ce2017-06-03 17:10:18 +0800245 ---help---
246 This option is the original only supported memory type, which suits
247 many H3/H5/A64 boards available now.
248
Icenowy Zhengec4670a2017-06-03 17:10:24 +0800249config SUNXI_DRAM_LPDDR3_STOCK
250 bool "LPDDR3 with Allwinner stock configuration"
251 select SUNXI_DRAM_LPDDR3
252 ---help---
253 This option is the LPDDR3 timing used by the stock boot0 by
254 Allwinner.
255
Icenowy Zheng67337e62017-06-03 17:10:20 +0800256config SUNXI_DRAM_DDR2_V3S
257 bool "DDR2 found in V3s chip"
258 select SUNXI_DRAM_DDR2
Icenowy Zheng3ec06982017-06-03 17:10:21 +0800259 depends on MACH_SUN8I_V3S
Icenowy Zheng67337e62017-06-03 17:10:20 +0800260 ---help---
261 This option is only for the DDR2 memory chip which is co-packaged in
262 Allwinner V3s SoC.
263
Icenowy Zhengf6457ce2017-06-03 17:10:18 +0800264endchoice
265endif
266
Vishnu Patekarf5fd8ca2016-01-12 01:20:58 +0800267config DRAM_TYPE
268 int "sunxi dram type"
269 depends on MACH_SUN8I_A83T
270 default 3
271 ---help---
272 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200273
Hans de Goede37781a12014-11-15 19:46:39 +0100274config DRAM_CLK
Hans de Goede8ffc4872015-01-17 14:24:55 +0100275 int "sunxi dram clock speed"
Philipp Tomsich297bb9e2016-10-28 18:21:28 +0800276 default 792 if MACH_SUN9I
Chen-Yu Tsaifab03e32016-11-30 16:58:35 +0800277 default 648 if MACH_SUN8I_R40
Hans de Goede8ffc4872015-01-17 14:24:55 +0100278 default 312 if MACH_SUN6I || MACH_SUN8I
Icenowy Zheng7d06e592017-06-03 17:10:22 +0800279 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
280 MACH_SUN8I_V3S
Andre Przywara52e31822017-01-02 11:48:37 +0000281 default 672 if MACH_SUN50I
Hans de Goede37781a12014-11-15 19:46:39 +0100282 ---help---
Philipp Tomsich297bb9e2016-10-28 18:21:28 +0800283 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
284 must be a multiple of 24. For the sun9i (A80), the tested values
285 (for DDR3-1600) are 312 to 792.
Hans de Goede37781a12014-11-15 19:46:39 +0100286
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200287if MACH_SUN5I || MACH_SUN7I
288config DRAM_MBUS_CLK
289 int "sunxi mbus clock speed"
290 default 300
291 ---help---
292 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
293
294endif
295
Hans de Goede37781a12014-11-15 19:46:39 +0100296config DRAM_ZQ
Hans de Goede8ffc4872015-01-17 14:24:55 +0100297 int "sunxi dram zq value"
298 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
299 default 127 if MACH_SUN7I
Icenowy Zheng7d06e592017-06-03 17:10:22 +0800300 default 14779 if MACH_SUN8I_V3S
Chen-Yu Tsaifab03e32016-11-30 16:58:35 +0800301 default 3881979 if MACH_SUN8I_R40
Chen-Yu Tsai58b628e2016-10-28 18:21:36 +0800302 default 4145117 if MACH_SUN9I
Andre Przywara52e31822017-01-02 11:48:37 +0000303 default 3881915 if MACH_SUN50I
Hans de Goede37781a12014-11-15 19:46:39 +0100304 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100305 Set the dram zq value.
Hans de Goede37781a12014-11-15 19:46:39 +0100306
Hans de Goede8975cdf2015-05-13 15:00:46 +0200307config DRAM_ODT_EN
308 bool "sunxi dram odt enable"
309 default n if !MACH_SUN8I_A23
310 default y if MACH_SUN8I_A23
Chen-Yu Tsaifab03e32016-11-30 16:58:35 +0800311 default y if MACH_SUN8I_R40
Andre Przywaraeb77f5c2017-01-02 11:48:45 +0000312 default y if MACH_SUN50I
Hans de Goede8975cdf2015-05-13 15:00:46 +0200313 ---help---
314 Select this to enable dram odt (on die termination).
315
Hans de Goede8ffc4872015-01-17 14:24:55 +0100316if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
317config DRAM_EMR1
318 int "sunxi dram emr1 value"
319 default 0 if MACH_SUN4I
320 default 4 if MACH_SUN5I || MACH_SUN7I
321 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100322 Set the dram controller emr1 value.
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200323
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200324config DRAM_TPR3
325 hex "sunxi dram tpr3 value"
326 default 0
327 ---help---
328 Set the dram controller tpr3 parameter. This parameter configures
329 the delay on the command lane and also phase shifts, which are
330 applied for sampling incoming read data. The default value 0
331 means that no phase/delay adjustments are necessary. Properly
332 configuring this parameter increases reliability at high DRAM
333 clock speeds.
334
335config DRAM_DQS_GATING_DELAY
336 hex "sunxi dram dqs_gating_delay value"
337 default 0
338 ---help---
339 Set the dram controller dqs_gating_delay parmeter. Each byte
340 encodes the DQS gating delay for each byte lane. The delay
341 granularity is 1/4 cycle. For example, the value 0x05060606
342 means that the delay is 5 quarter-cycles for one lane (1.25
343 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
344 The default value 0 means autodetection. The results of hardware
345 autodetection are not very reliable and depend on the chip
346 temperature (sometimes producing different results on cold start
347 and warm reboot). But the accuracy of hardware autodetection
348 is usually good enough, unless running at really high DRAM
349 clocks speeds (up to 600MHz). If unsure, keep as 0.
350
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200351choice
352 prompt "sunxi dram timings"
353 default DRAM_TIMINGS_VENDOR_MAGIC
354 ---help---
355 Select the timings of the DDR3 chips.
356
357config DRAM_TIMINGS_VENDOR_MAGIC
358 bool "Magic vendor timings from Android"
359 ---help---
360 The same DRAM timings as in the Allwinner boot0 bootloader.
361
362config DRAM_TIMINGS_DDR3_1066F_1333H
363 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
364 ---help---
365 Use the timings of the standard JEDEC DDR3-1066F speed bin for
366 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
367 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
368 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
369 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
370 that down binning to DDR3-1066F is supported (because DDR3-1066F
371 uses a bit faster timings than DDR3-1333H).
372
373config DRAM_TIMINGS_DDR3_800E_1066G_1333J
374 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
375 ---help---
376 Use the timings of the slowest possible JEDEC speed bin for the
377 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
378 DDR3-800E, DDR3-1066G or DDR3-1333J.
379
380endchoice
381
Hans de Goede37781a12014-11-15 19:46:39 +0100382endif
383
Hans de Goede8975cdf2015-05-13 15:00:46 +0200384if MACH_SUN8I_A23
385config DRAM_ODT_CORRECTION
386 int "sunxi dram odt correction value"
387 default 0
388 ---help---
389 Set the dram odt correction value (range -255 - 255). In allwinner
390 fex files, this option is found in bits 8-15 of the u32 odt_en variable
391 in the [dram] section. When bit 31 of the odt_en variable is set
392 then the correction is negative. Usually the value for this is 0.
393endif
394
Iain Patone71b4222015-03-28 10:26:38 +0000395config SYS_CLK_FREQ
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800396 default 1008000000 if MACH_SUN4I
397 default 1008000000 if MACH_SUN5I
398 default 1008000000 if MACH_SUN6I
Iain Patone71b4222015-03-28 10:26:38 +0000399 default 912000000 if MACH_SUN7I
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800400 default 1008000000 if MACH_SUN8I
401 default 1008000000 if MACH_SUN9I
402 default 816000000 if MACH_SUN50I
Iain Patone71b4222015-03-28 10:26:38 +0000403
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800404config SYS_CONFIG_NAME
Ian Campbellc3be2792014-10-24 21:20:45 +0100405 default "sun4i" if MACH_SUN4I
406 default "sun5i" if MACH_SUN5I
407 default "sun6i" if MACH_SUN6I
408 default "sun7i" if MACH_SUN7I
409 default "sun8i" if MACH_SUN8I
Hans de Goede1871a8c2015-01-13 19:25:06 +0100410 default "sun9i" if MACH_SUN9I
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200411 default "sun50i" if MACH_SUN50I
Hans de Goede6ae66f22014-08-01 09:28:24 +0200412
Masahiro Yamadadd840582014-07-30 14:08:14 +0900413config SYS_BOARD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900414 default "sunxi"
415
416config SYS_SOC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900417 default "sunxi"
418
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200419config UART0_PORT_F
420 bool "UART0 on MicroSD breakout board"
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200421 default n
422 ---help---
423 Repurpose the SD card slot for getting access to the UART0 serial
424 console. Primarily useful only for low level u-boot debugging on
425 tablets, where normal UART0 is difficult to access and requires
426 device disassembly and/or soldering. As the SD card can't be used
427 at the same time, the system can be only booted in the FEL mode.
428 Only enable this if you really know what you are doing.
429
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200430config OLD_SUNXI_KERNEL_COMPAT
Masahiro Yamadaab650062016-08-12 10:26:50 +0900431 bool "Enable workarounds for booting old kernels"
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200432 default n
433 ---help---
434 Set this to enable various workarounds for old kernels, this results in
435 sub-optimal settings for newer kernels, only enable if needed.
436
Mylène Josserandf5fd7882017-04-02 12:59:10 +0200437config MACPWR
438 string "MAC power pin"
439 default ""
440 help
441 Set the pin used to power the MAC. This takes a string in the format
442 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
443
Hans de Goedecd821132014-10-02 20:29:26 +0200444config MMC0_CD_PIN
445 string "Card detect pin for mmc0"
Andre Przywara7b82a222017-02-16 01:20:27 +0000446 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
Hans de Goedecd821132014-10-02 20:29:26 +0200447 default ""
448 ---help---
449 Set the card detect pin for mmc0, leave empty to not use cd. This
450 takes a string in the format understood by sunxi_name_to_gpio, e.g.
451 PH1 for pin 1 of port H.
452
453config MMC1_CD_PIN
454 string "Card detect pin for mmc1"
455 default ""
456 ---help---
457 See MMC0_CD_PIN help text.
458
459config MMC2_CD_PIN
460 string "Card detect pin for mmc2"
461 default ""
462 ---help---
463 See MMC0_CD_PIN help text.
464
465config MMC3_CD_PIN
466 string "Card detect pin for mmc3"
467 default ""
468 ---help---
469 See MMC0_CD_PIN help text.
470
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100471config MMC1_PINS
472 string "Pins for mmc1"
473 default ""
474 ---help---
475 Set the pins used for mmc1, when applicable. This takes a string in the
476 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
477
478config MMC2_PINS
479 string "Pins for mmc2"
480 default ""
481 ---help---
482 See MMC1_PINS help text.
483
484config MMC3_PINS
485 string "Pins for mmc3"
486 default ""
487 ---help---
488 See MMC1_PINS help text.
489
Hans de Goede2ccfac02014-10-02 20:43:50 +0200490config MMC_SUNXI_SLOT_EXTRA
491 int "mmc extra slot number"
492 default -1
493 ---help---
494 sunxi builds always enable mmc0, some boards also have a second sdcard
495 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
496 support for this.
497
Hans de Goede2c3c3ec2016-04-01 22:39:26 +0200498config INITIAL_USB_SCAN_DELAY
499 int "delay initial usb scan by x ms to allow builtin devices to init"
500 default 0
501 ---help---
502 Some boards have on board usb devices which need longer than the
503 USB spec's 1 second to connect from board powerup. Set this config
504 option to a non 0 value to add an extra delay before the first usb
505 bus scan.
506
Hans de Goede4458b7a2015-01-07 15:26:06 +0100507config USB0_VBUS_PIN
508 string "Vbus enable pin for usb0 (otg)"
509 default ""
510 ---help---
511 Set the Vbus enable pin for usb0 (otg). This takes a string in the
512 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
513
Hans de Goede52defe82015-02-16 22:13:43 +0100514config USB0_VBUS_DET
515 string "Vbus detect pin for usb0 (otg)"
Hans de Goede52defe82015-02-16 22:13:43 +0100516 default ""
517 ---help---
518 Set the Vbus detect pin for usb0 (otg). This takes a string in the
519 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
520
Hans de Goede48c06c92015-06-14 17:29:53 +0200521config USB0_ID_DET
522 string "ID detect pin for usb0 (otg)"
523 default ""
524 ---help---
525 Set the ID detect pin for usb0 (otg). This takes a string in the
526 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
527
Hans de Goede115200c2014-11-07 16:09:00 +0100528config USB1_VBUS_PIN
529 string "Vbus enable pin for usb1 (ehci0)"
530 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100531 default "PH27" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100532 ---help---
533 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
534 a string in the format understood by sunxi_name_to_gpio, e.g.
535 PH1 for pin 1 of port H.
536
537config USB2_VBUS_PIN
538 string "Vbus enable pin for usb2 (ehci1)"
539 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100540 default "PH24" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100541 ---help---
542 See USB1_VBUS_PIN help text.
543
Hans de Goede60fa6302016-03-18 08:42:01 +0100544config USB3_VBUS_PIN
545 string "Vbus enable pin for usb3 (ehci2)"
546 default ""
547 ---help---
548 See USB1_VBUS_PIN help text.
549
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200550config I2C0_ENABLE
551 bool "Enable I2C/TWI controller 0"
Chen-Yu Tsai409677e2016-11-30 15:30:30 +0800552 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200553 default n if MACH_SUN6I || MACH_SUN8I
Hans de Goede0878a8a2016-05-15 13:51:58 +0200554 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200555 ---help---
556 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
557 its clock and setting up the bus. This is especially useful on devices
558 with slaves connected to the bus or with pins exposed through e.g. an
559 expansion port/header.
560
561config I2C1_ENABLE
562 bool "Enable I2C/TWI controller 1"
563 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200564 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200565 ---help---
566 See I2C0_ENABLE help text.
567
568config I2C2_ENABLE
569 bool "Enable I2C/TWI controller 2"
570 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200571 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200572 ---help---
573 See I2C0_ENABLE help text.
574
575if MACH_SUN6I || MACH_SUN7I
576config I2C3_ENABLE
577 bool "Enable I2C/TWI controller 3"
578 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200579 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200580 ---help---
581 See I2C0_ENABLE help text.
582endif
583
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100584if SUNXI_GEN_SUN6I
Jelle van der Waa9d082682016-01-14 14:06:26 +0100585config R_I2C_ENABLE
586 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100587 # This is used for the pmic on H3
588 default y if SY8106A_POWER
Hans de Goede0878a8a2016-05-15 13:51:58 +0200589 select CMD_I2C
Jelle van der Waa9d082682016-01-14 14:06:26 +0100590 ---help---
591 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100592endif
Jelle van der Waa9d082682016-01-14 14:06:26 +0100593
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200594if MACH_SUN7I
595config I2C4_ENABLE
596 bool "Enable I2C/TWI controller 4"
597 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200598 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200599 ---help---
600 See I2C0_ENABLE help text.
601endif
602
Hans de Goede2fcf0332015-04-25 17:25:14 +0200603config AXP_GPIO
Masahiro Yamadaab650062016-08-12 10:26:50 +0900604 bool "Enable support for gpio-s on axp PMICs"
Hans de Goede2fcf0332015-04-25 17:25:14 +0200605 default n
606 ---help---
607 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
608
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800609config VIDEO_SUNXI
Masahiro Yamadaab650062016-08-12 10:26:50 +0900610 bool "Enable graphical uboot console on HDMI, LCD or VGA"
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800611 depends on !MACH_SUN8I_A83T
612 depends on !MACH_SUNXI_H3_H5
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800613 depends on !MACH_SUN8I_R40
Icenowy Zhengc1994892017-04-08 15:30:12 +0800614 depends on !MACH_SUN8I_V3S
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800615 depends on !MACH_SUN9I
616 depends on !MACH_SUN50I
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800617 select VIDEO
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200618 default y
619 ---help---
Hans de Goede2dae8002014-12-21 16:28:32 +0100620 Say Y here to add support for using a cfb console on the HDMI, LCD
621 or VGA output found on most sunxi devices. See doc/README.video for
622 info on how to select the video output and mode.
623
Hans de Goede2fbf0912014-12-23 23:04:35 +0100624config VIDEO_HDMI
Masahiro Yamadaab650062016-08-12 10:26:50 +0900625 bool "HDMI output support"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800626 depends on VIDEO_SUNXI && !MACH_SUN8I
Hans de Goede2fbf0912014-12-23 23:04:35 +0100627 default y
628 ---help---
629 Say Y here to add support for outputting video over HDMI.
630
Hans de Goeded9786d22014-12-25 13:58:06 +0100631config VIDEO_VGA
Masahiro Yamadaab650062016-08-12 10:26:50 +0900632 bool "VGA output support"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800633 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
Hans de Goeded9786d22014-12-25 13:58:06 +0100634 default n
635 ---help---
636 Say Y here to add support for outputting video over VGA.
637
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100638config VIDEO_VGA_VIA_LCD
Masahiro Yamadaab650062016-08-12 10:26:50 +0900639 bool "VGA via LCD controller support"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800640 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100641 default n
642 ---help---
643 Say Y here to add support for external DACs connected to the parallel
644 LCD interface driving a VGA connector, such as found on the
645 Olimex A13 boards.
646
Hans de Goedefb75d972015-01-25 15:33:07 +0100647config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
Masahiro Yamadaab650062016-08-12 10:26:50 +0900648 bool "Force sync active high for VGA via LCD controller support"
Hans de Goedefb75d972015-01-25 15:33:07 +0100649 depends on VIDEO_VGA_VIA_LCD
650 default n
651 ---help---
652 Say Y here if you've a board which uses opendrain drivers for the vga
653 hsync and vsync signals. Opendrain drivers cannot generate steep enough
654 positive edges for a stable video output, so on boards with opendrain
655 drivers the sync signals must always be active high.
656
Chen-Yu Tsai507e27d2015-01-12 18:02:11 +0800657config VIDEO_VGA_EXTERNAL_DAC_EN
658 string "LCD panel power enable pin"
659 depends on VIDEO_VGA_VIA_LCD
660 default ""
661 ---help---
662 Set the enable pin for the external VGA DAC. This takes a string in the
663 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
664
Hans de Goede39920c82015-08-03 19:20:26 +0200665config VIDEO_COMPOSITE
Masahiro Yamadaab650062016-08-12 10:26:50 +0900666 bool "Composite video output support"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800667 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
Hans de Goede39920c82015-08-03 19:20:26 +0200668 default n
669 ---help---
670 Say Y here to add support for outputting composite video.
671
Hans de Goede2dae8002014-12-21 16:28:32 +0100672config VIDEO_LCD_MODE
673 string "LCD panel timing details"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800674 depends on VIDEO_SUNXI
Hans de Goede2dae8002014-12-21 16:28:32 +0100675 default ""
676 ---help---
677 LCD panel timing details string, leave empty if there is no LCD panel.
678 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
679 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede8addd3e2015-08-16 11:23:42 +0200680 Also see: http://linux-sunxi.org/LCD
Hans de Goede2dae8002014-12-21 16:28:32 +0100681
Hans de Goede65150322015-01-13 13:21:46 +0100682config VIDEO_LCD_DCLK_PHASE
683 int "LCD panel display clock phase"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800684 depends on VIDEO_SUNXI
Hans de Goede65150322015-01-13 13:21:46 +0100685 default 1
686 ---help---
687 Select LCD panel display clock phase shift, range 0-3.
688
Hans de Goede2dae8002014-12-21 16:28:32 +0100689config VIDEO_LCD_POWER
690 string "LCD panel power enable pin"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800691 depends on VIDEO_SUNXI
Hans de Goede2dae8002014-12-21 16:28:32 +0100692 default ""
693 ---help---
694 Set the power enable pin for the LCD panel. This takes a string in the
695 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
696
Hans de Goede242e3d82015-02-16 17:26:41 +0100697config VIDEO_LCD_RESET
698 string "LCD panel reset pin"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800699 depends on VIDEO_SUNXI
Hans de Goede242e3d82015-02-16 17:26:41 +0100700 default ""
701 ---help---
702 Set the reset pin for the LCD panel. This takes a string in the format
703 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
704
Hans de Goede2dae8002014-12-21 16:28:32 +0100705config VIDEO_LCD_BL_EN
706 string "LCD panel backlight enable pin"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800707 depends on VIDEO_SUNXI
Hans de Goede2dae8002014-12-21 16:28:32 +0100708 default ""
709 ---help---
710 Set the backlight enable pin for the LCD panel. This takes a string in the
711 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
712 port H.
713
714config VIDEO_LCD_BL_PWM
715 string "LCD panel backlight pwm pin"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800716 depends on VIDEO_SUNXI
Hans de Goede2dae8002014-12-21 16:28:32 +0100717 default ""
718 ---help---
719 Set the backlight pwm pin for the LCD panel. This takes a string in the
720 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200721
Hans de Goedea7403ae2015-01-22 21:02:42 +0100722config VIDEO_LCD_BL_PWM_ACTIVE_LOW
723 bool "LCD panel backlight pwm is inverted"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800724 depends on VIDEO_SUNXI
Hans de Goedea7403ae2015-01-22 21:02:42 +0100725 default y
726 ---help---
727 Set this if the backlight pwm output is active low.
728
Hans de Goede55410082015-02-16 17:23:25 +0100729config VIDEO_LCD_PANEL_I2C
730 bool "LCD panel needs to be configured via i2c"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800731 depends on VIDEO_SUNXI
Hans de Goede1fc42012015-03-07 12:00:02 +0100732 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200733 select CMD_I2C
Hans de Goede55410082015-02-16 17:23:25 +0100734 ---help---
735 Say y here if the LCD panel needs to be configured via i2c. This
736 will add a bitbang i2c controller using gpios to talk to the LCD.
737
738config VIDEO_LCD_PANEL_I2C_SDA
739 string "LCD panel i2c interface SDA pin"
740 depends on VIDEO_LCD_PANEL_I2C
741 default "PG12"
742 ---help---
743 Set the SDA pin for the LCD i2c interface. This takes a string in the
744 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
745
746config VIDEO_LCD_PANEL_I2C_SCL
747 string "LCD panel i2c interface SCL pin"
748 depends on VIDEO_LCD_PANEL_I2C
749 default "PG10"
750 ---help---
751 Set the SCL pin for the LCD i2c interface. This takes a string in the
752 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
753
Hans de Goede213480e2015-01-01 22:04:34 +0100754
755# Note only one of these may be selected at a time! But hidden choices are
756# not supported by Kconfig
757config VIDEO_LCD_IF_PARALLEL
758 bool
759
760config VIDEO_LCD_IF_LVDS
761 bool
762
Jernej Skrabec1ae5def2017-03-27 19:22:31 +0200763config SUNXI_DE2
764 bool
765 default n
766
Jernej Skrabec56009452017-03-27 19:22:32 +0200767config VIDEO_DE2
768 bool "Display Engine 2 video driver"
769 depends on SUNXI_DE2
770 select DM_VIDEO
771 select DISPLAY
772 default y
773 ---help---
774 Say y here if you want to build DE2 video driver which is present on
775 newer SoCs. Currently only HDMI output is supported.
776
Hans de Goede213480e2015-01-01 22:04:34 +0100777
778choice
779 prompt "LCD panel support"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800780 depends on VIDEO_SUNXI
Hans de Goede213480e2015-01-01 22:04:34 +0100781 ---help---
782 Select which type of LCD panel to support.
783
784config VIDEO_LCD_PANEL_PARALLEL
785 bool "Generic parallel interface LCD panel"
786 select VIDEO_LCD_IF_PARALLEL
787
788config VIDEO_LCD_PANEL_LVDS
789 bool "Generic lvds interface LCD panel"
790 select VIDEO_LCD_IF_LVDS
791
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200792config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
793 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
794 select VIDEO_LCD_SSD2828
795 select VIDEO_LCD_IF_PARALLEL
796 ---help---
Hans de Goedec1cfd512015-08-08 16:13:53 +0200797 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
798
799config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
800 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
801 select VIDEO_LCD_ANX9804
802 select VIDEO_LCD_IF_PARALLEL
803 select VIDEO_LCD_PANEL_I2C
804 ---help---
805 Select this for eDP LCD panels with 4 lanes running at 1.62G,
806 connected via an ANX9804 bridge chip.
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200807
Hans de Goede27515b22015-01-20 09:23:36 +0100808config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
809 bool "Hitachi tx18d42vm LCD panel"
810 select VIDEO_LCD_HITACHI_TX18D42VM
811 select VIDEO_LCD_IF_LVDS
812 ---help---
813 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
814
Hans de Goedeaad2ac22015-02-16 17:49:47 +0100815config VIDEO_LCD_TL059WV5C0
816 bool "tl059wv5c0 LCD panel"
817 select VIDEO_LCD_PANEL_I2C
818 select VIDEO_LCD_IF_PARALLEL
819 ---help---
820 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
821 Aigo M60/M608/M606 tablets.
822
Hans de Goede213480e2015-01-01 22:04:34 +0100823endchoice
824
Mylène Josserandd7b560e2017-04-02 12:59:09 +0200825config SATAPWR
826 string "SATA power pin"
827 default ""
828 help
829 Set the pins used to power the SATA. This takes a string in the
830 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
831 port H.
Hans de Goede213480e2015-01-01 22:04:34 +0100832
Hans de Goedec13f60d2015-01-25 12:10:48 +0100833config GMAC_TX_DELAY
834 int "GMAC Transmit Clock Delay Chain"
835 default 0
836 ---help---
837 Set the GMAC Transmit Clock Delay Chain value.
838
Hans de Goedeff42d102015-09-13 13:02:48 +0200839config SPL_STACK_R_ADDR
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800840 default 0x4fe00000 if MACH_SUN4I
841 default 0x4fe00000 if MACH_SUN5I
842 default 0x4fe00000 if MACH_SUN6I
843 default 0x4fe00000 if MACH_SUN7I
844 default 0x4fe00000 if MACH_SUN8I
Hans de Goedeff42d102015-09-13 13:02:48 +0200845 default 0x2fe00000 if MACH_SUN9I
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800846 default 0x4fe00000 if MACH_SUN50I
Hans de Goedeff42d102015-09-13 13:02:48 +0200847
Masahiro Yamadadd840582014-07-30 14:08:14 +0900848endif