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gerrit.cesnet.cz / github / trini / u-boot / 8176a874233eb5180701e2811b38c199369975b2 / . / arch / powerpc / include / asm / config_mpc85xx.h
blob: 01b09058cc3fb8765622e17379765f6d71031435 [file] [log] [blame]
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]1/*
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000[diff] [blame]2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]5 */
6
7#ifndef _ASM_MPC85xx_CONFIG_H_
8#define _ASM_MPC85xx_CONFIG_H_
9
10/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
11
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]12#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
13#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
14#endif
15
York Sun2a5fcb82012-10-28 08:12:54 +0000[diff] [blame]16/*
17 * This macro should be removed when we no longer care about backwards
18 * compatibility with older operating systems.
19 */
20#define CONFIG_PPC_SPINTABLE_COMPATIBLE
21
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]22#include <fsl_ddrc_version.h>
23#define CONFIG_SYS_FSL_DDR_BE
York Sun57495e42012-10-08 07:44:22 +0000[diff] [blame]24
Prabhakar Kushwaha1b4175d2014-01-18 12:28:30 +0530[diff] [blame]25/* IP endianness */
26#define CONFIG_SYS_FSL_IFC_BE
Ruchika Gupta028dbb82014-09-09 11:50:31 +0530[diff] [blame]27#define CONFIG_SYS_FSL_SEC_BE
Prabhakar Kushwaha1b4175d2014-01-18 12:28:30 +0530[diff] [blame]28
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]29/* Number of TLB CAM entries we have on FSL Book-E chips */
30#if defined(CONFIG_E500MC)
31#define CONFIG_SYS_NUM_TLBCAMS 64
32#elif defined(CONFIG_E500)
33#define CONFIG_SYS_NUM_TLBCAMS 16
34#endif
35
36#if defined(CONFIG_MPC8536)
37#define CONFIG_MAX_CPUS 1
38#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +0000[diff] [blame]39#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]40#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]41#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun9855b3b2014-05-23 13:15:00 -0700[diff] [blame]42#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]43#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]44
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100[diff] [blame]45#elif defined(CONFIG_MPC8540)
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]46#define CONFIG_MAX_CPUS 1
47#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]48#define CONFIG_SYS_FSL_DDRC_GEN1
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]49#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]50
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100[diff] [blame]51#elif defined(CONFIG_MPC8541)
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]52#define CONFIG_MAX_CPUS 1
53#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]54#define CONFIG_SYS_FSL_DDRC_GEN1
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]55#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]56#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]57
58#elif defined(CONFIG_MPC8544)
59#define CONFIG_MAX_CPUS 1
60#define CONFIG_SYS_FSL_NUM_LAWS 10
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]61#define CONFIG_SYS_FSL_DDRC_GEN2
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +0000[diff] [blame]62#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]63#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]64#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]65#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]66
67#elif defined(CONFIG_MPC8548)
68#define CONFIG_MAX_CPUS 1
69#define CONFIG_SYS_FSL_NUM_LAWS 10
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]70#define CONFIG_SYS_FSL_DDRC_GEN2
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +0000[diff] [blame]71#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]72#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]73#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala5ace2992011-09-16 09:54:30 -0500[diff] [blame]74#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
Kumar Gala2b3a1cd2011-10-03 08:37:57 -0500[diff] [blame]75#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
chenhui zhaoaada81d2011-10-03 08:38:50 -0500[diff] [blame]76#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]77#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
78#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
79#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
80#define CONFIG_SYS_FSL_RMU
81#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]82#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800[diff] [blame]83#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
84#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]85
86#elif defined(CONFIG_MPC8555)
87#define CONFIG_MAX_CPUS 1
88#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]89#define CONFIG_SYS_FSL_DDRC_GEN1
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]90#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]91#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]92
93#elif defined(CONFIG_MPC8560)
94#define CONFIG_MAX_CPUS 1
95#define CONFIG_SYS_FSL_NUM_LAWS 8
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]96#define CONFIG_SYS_FSL_DDRC_GEN1
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]97#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]98
99#elif defined(CONFIG_MPC8568)
100#define CONFIG_MAX_CPUS 1
101#define CONFIG_SYS_FSL_NUM_LAWS 10
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]102#define CONFIG_SYS_FSL_DDRC_GEN2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]103#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galafdb4dad2011-01-31 23:09:25 -0600[diff] [blame]104#define QE_MURAM_SIZE 0x10000UL
105#define MAX_QE_RISC 2
106#define QE_NUM_OF_SNUM 28
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]107#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]108#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
109#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
110#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
111#define CONFIG_SYS_FSL_RMU
112#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]113
114#elif defined(CONFIG_MPC8569)
115#define CONFIG_MAX_CPUS 1
116#define CONFIG_SYS_FSL_NUM_LAWS 10
117#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galafdb4dad2011-01-31 23:09:25 -0600[diff] [blame]118#define QE_MURAM_SIZE 0x20000UL
119#define MAX_QE_RISC 4
120#define QE_NUM_OF_SNUM 46
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]121#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]122#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
123#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
124#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
125#define CONFIG_SYS_FSL_RMU
126#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun9855b3b2014-05-23 13:15:00 -0700[diff] [blame]127#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]128#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]129
130#elif defined(CONFIG_MPC8572)
131#define CONFIG_MAX_CPUS 2
132#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahae4879af2012-08-15 04:12:43 +0000[diff] [blame]133#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]134#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]135#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Suneb0aff72011-01-25 21:51:27 -0800[diff] [blame]136#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sun91671912011-01-25 22:05:49 -0800[diff] [blame]137#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
York Sun9855b3b2014-05-23 13:15:00 -0700[diff] [blame]138#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]139#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]140
141#elif defined(CONFIG_P1010)
142#define CONFIG_MAX_CPUS 1
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530[diff] [blame]143#define CONFIG_FSL_SDHC_V2_3
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]144#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]145#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]146#define CONFIG_TSECV2
147#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530[diff] [blame]148#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
149#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]150#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Mingkai Hu362ee042013-05-16 10:18:13 +0800[diff] [blame]151#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530[diff] [blame]152#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]153#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530[diff] [blame]154#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal42aee642011-06-30 03:00:28 -0500[diff] [blame]155#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalfb855f42011-06-29 16:32:52 +0530[diff] [blame]156#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Shengzhou Liu424bf942013-08-15 09:31:47 +0800[diff] [blame]157#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
Poonam Aggrwalbc6bbd62011-07-07 20:36:47 +0530[diff] [blame]158#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]159#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800[diff] [blame]160#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
York Sun9855b3b2014-05-23 13:15:00 -0700[diff] [blame]161#define CONFIG_SYS_FSL_ERRATUM_A004508
Nikhil Badola11856912014-02-26 17:43:15 +0530[diff] [blame]162#define CONFIG_SYS_FSL_ERRATUM_A007075
Suresh Gupta9c641a82014-02-26 14:29:12 +0530[diff] [blame]163#define CONFIG_SYS_FSL_ERRATUM_A006261
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800[diff] [blame]164#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
Haijun.Zhangf28bea02014-01-10 13:52:19 +0800[diff] [blame]165#define CONFIG_ESDHC_HC_BLK_ADDR
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]166
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]167/* P1011 is single core version of P1020 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]168#elif defined(CONFIG_P1011)
169#define CONFIG_MAX_CPUS 1
170#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]171#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]172#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000[diff] [blame]173#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]174#define CONFIG_SYS_FSL_SEC_COMPAT 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]175#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]176#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]177#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
178#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun9855b3b2014-05-23 13:15:00 -0700[diff] [blame]179#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]180#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]181
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]182/* P1012 is single core version of P1021 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]183#elif defined(CONFIG_P1012)
184#define CONFIG_MAX_CPUS 1
185#define CONFIG_SYS_FSL_NUM_LAWS 12
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]186#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]187#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]188#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000[diff] [blame]189#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]190#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]191#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]192#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
193#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600[diff] [blame]194#define QE_MURAM_SIZE 0x6000UL
195#define MAX_QE_RISC 1
196#define QE_NUM_OF_SNUM 28
York Sun9855b3b2014-05-23 13:15:00 -0700[diff] [blame]197#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]198#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]199
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]200/* P1013 is single core version of P1022 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]201#elif defined(CONFIG_P1013)
202#define CONFIG_MAX_CPUS 1
203#define CONFIG_SYS_FSL_NUM_LAWS 12
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]204#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]205#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]206#define CONFIG_TSECV2
207#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]208#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang2d7534a2011-01-30 17:06:20 -0600[diff] [blame]209#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
210#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
211#define CONFIG_FSL_SATA_ERRATUM_A001
York Sun9855b3b2014-05-23 13:15:00 -0700[diff] [blame]212#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]213#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]214
215#elif defined(CONFIG_P1014)
216#define CONFIG_MAX_CPUS 1
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530[diff] [blame]217#define CONFIG_FSL_SDHC_V2_3
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]218#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]219#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]220#define CONFIG_TSECV2
221#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530[diff] [blame]222#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
223#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]224#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Poonam Aggrwal1fbf3482011-02-06 11:31:44 +0530[diff] [blame]225#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Ramneek Mehresh1b719e62011-03-23 15:20:43 +0530[diff] [blame]226#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal42aee642011-06-30 03:00:28 -0500[diff] [blame]227#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalfb855f42011-06-29 16:32:52 +0530[diff] [blame]228#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwalbc6bbd62011-07-07 20:36:47 +0530[diff] [blame]229#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
York Sun9855b3b2014-05-23 13:15:00 -0700[diff] [blame]230#define CONFIG_SYS_FSL_ERRATUM_A004508
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]231
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]232/* P1017 is single core version of P1023 */
Roy Zang67a719d2011-02-03 22:14:19 -0600[diff] [blame]233#elif defined(CONFIG_P1017)
234#define CONFIG_MAX_CPUS 1
235#define CONFIG_SYS_FSL_NUM_LAWS 12
236#define CONFIG_SYS_FSL_SEC_COMPAT 4
237#define CONFIG_SYS_NUM_FMAN 1
238#define CONFIG_SYS_NUM_FM1_DTSEC 2
239#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]240#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Roy Zang67a719d2011-02-03 22:14:19 -0600[diff] [blame]241#define CONFIG_SYS_QMAN_NUM_PORTALS 3
242#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]243#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]244#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]245#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
York Sun9855b3b2014-05-23 13:15:00 -0700[diff] [blame]246#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]247#define CONFIG_SYS_FSL_ERRATUM_A005125
Roy Zang67a719d2011-02-03 22:14:19 -0600[diff] [blame]248
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]249#elif defined(CONFIG_P1020)
250#define CONFIG_MAX_CPUS 2
251#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]252#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]253#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000[diff] [blame]254#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]255#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]256#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]257#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
258#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun9855b3b2014-05-23 13:15:00 -0700[diff] [blame]259#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]260#define CONFIG_SYS_FSL_ERRATUM_A005125
ramneek mehresh80ba6a62014-05-13 15:36:07 +0530[diff] [blame]261#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]262#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
ramneek mehresh80ba6a62014-05-13 15:36:07 +0530[diff] [blame]263#endif
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]264
265#elif defined(CONFIG_P1021)
266#define CONFIG_MAX_CPUS 2
267#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]268#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]269#define CONFIG_TSECV2
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000[diff] [blame]270#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]271#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]272#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]273#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
274#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600[diff] [blame]275#define QE_MURAM_SIZE 0x6000UL
276#define MAX_QE_RISC 1
277#define QE_NUM_OF_SNUM 28
York Sun9855b3b2014-05-23 13:15:00 -0700[diff] [blame]278#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]279#define CONFIG_SYS_FSL_ERRATUM_A005125
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]280#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]281
282#elif defined(CONFIG_P1022)
283#define CONFIG_MAX_CPUS 2
284#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]285#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]286#define CONFIG_TSECV2
287#define CONFIG_SYS_FSL_SEC_COMPAT 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]288#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]289#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang2d7534a2011-01-30 17:06:20 -0600[diff] [blame]290#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
291#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
292#define CONFIG_FSL_SATA_ERRATUM_A001
York Sun9855b3b2014-05-23 13:15:00 -0700[diff] [blame]293#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]294#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]295
Roy Zang67a719d2011-02-03 22:14:19 -0600[diff] [blame]296#elif defined(CONFIG_P1023)
297#define CONFIG_MAX_CPUS 2
298#define CONFIG_SYS_FSL_NUM_LAWS 12
299#define CONFIG_SYS_FSL_SEC_COMPAT 4
300#define CONFIG_SYS_NUM_FMAN 1
301#define CONFIG_SYS_NUM_FM1_DTSEC 2
302#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]303#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Roy Zang67a719d2011-02-03 22:14:19 -0600[diff] [blame]304#define CONFIG_SYS_QMAN_NUM_PORTALS 3
305#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]306#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]307#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]308#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
York Sun9855b3b2014-05-23 13:15:00 -0700[diff] [blame]309#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]310#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800[diff] [blame]311#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
312#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Roy Zang67a719d2011-02-03 22:14:19 -0600[diff] [blame]313
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]314/* P1024 is lower end variant of P1020 */
315#elif defined(CONFIG_P1024)
316#define CONFIG_MAX_CPUS 2
317#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]318#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]319#define CONFIG_TSECV2
320#define CONFIG_FSL_PCIE_DISABLE_ASPM
321#define CONFIG_SYS_FSL_SEC_COMPAT 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]322#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]323#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]324#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
325#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun9855b3b2014-05-23 13:15:00 -0700[diff] [blame]326#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]327#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]328
329/* P1025 is lower end variant of P1021 */
330#elif defined(CONFIG_P1025)
331#define CONFIG_MAX_CPUS 2
332#define CONFIG_SYS_FSL_NUM_LAWS 12
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]333#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]334#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]335#define CONFIG_TSECV2
336#define CONFIG_FSL_PCIE_DISABLE_ASPM
337#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]338#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]339#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
340#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wanga52d2f82011-02-11 01:25:30 -0600[diff] [blame]341#define QE_MURAM_SIZE 0x6000UL
342#define MAX_QE_RISC 1
343#define QE_NUM_OF_SNUM 28
York Sun9855b3b2014-05-23 13:15:00 -0700[diff] [blame]344#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]345#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala093cffb2011-02-05 13:45:07 -0600[diff] [blame]346
347/* P2010 is single core version of P2020 */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]348#elif defined(CONFIG_P2010)
349#define CONFIG_MAX_CPUS 1
350#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]351#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]352#define CONFIG_SYS_FSL_SEC_COMPAT 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]353#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]354#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala6e7f0bc02011-01-26 01:43:15 -0600[diff] [blame]355#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala5103a032011-01-29 15:36:10 -0600[diff] [blame]356#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
York Sun9855b3b2014-05-23 13:15:00 -0700[diff] [blame]357#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]358#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]359
360#elif defined(CONFIG_P2020)
361#define CONFIG_MAX_CPUS 2
362#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwahaad75d442012-04-29 23:57:12 +0000[diff] [blame]363#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]364#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]365#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala6e7f0bc02011-01-26 01:43:15 -0600[diff] [blame]366#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala5103a032011-01-29 15:36:10 -0600[diff] [blame]367#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]368#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
369#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
370#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
371#define CONFIG_SYS_FSL_RMU
372#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun9855b3b2014-05-23 13:15:00 -0700[diff] [blame]373#define CONFIG_SYS_FSL_ERRATUM_A004508
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]374#define CONFIG_SYS_FSL_ERRATUM_A005125
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]375#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
York Sun9855b3b2014-05-23 13:15:00 -0700[diff] [blame]376
Scott Wood3e978f52012-08-14 10:14:51 +0000[diff] [blame]377#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]378#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700[diff] [blame]379#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala1f979872011-05-13 01:16:07 -0500[diff] [blame]380#define CONFIG_MAX_CPUS 4
381#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
382#define CONFIG_SYS_FSL_NUM_LAWS 32
383#define CONFIG_SYS_FSL_SEC_COMPAT 4
384#define CONFIG_SYS_NUM_FMAN 1
385#define CONFIG_SYS_NUM_FM1_DTSEC 5
386#define CONFIG_SYS_NUM_FM1_10GEC 1
387#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]388#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Kumar Gala1f979872011-05-13 01:16:07 -0500[diff] [blame]389#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
390#define CONFIG_SYS_FSL_TBCLK_DIV 32
391#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]392#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala1f979872011-05-13 01:16:07 -0500[diff] [blame]393#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
394#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500[diff] [blame]395#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala1f979872011-05-13 01:16:07 -0500[diff] [blame]396#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun5e23ab02012-05-07 07:26:47 +0000[diff] [blame]397#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei99d7b0a2013-03-11 17:56:34 +0000[diff] [blame]398#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala43f082b2011-11-22 06:51:15 -0600[diff] [blame]399#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sune22be772013-03-25 07:30:11 +0000[diff] [blame]400#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun41085082011-11-20 10:01:35 -0800[diff] [blame]401#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]402#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
403#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
404#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000[diff] [blame]405#define CONFIG_SYS_FSL_ERRATUM_A004510
406#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
407#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
408#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000[diff] [blame]409#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi01180332012-10-25 12:40:00 +0000[diff] [blame]410#define CONFIG_SYS_FSL_ERRATUM_A004849
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800[diff] [blame]411#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Suresh Gupta9c641a82014-02-26 14:29:12 +0530[diff] [blame]412#define CONFIG_SYS_FSL_ERRATUM_A006261
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800[diff] [blame]413#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Kumar Gala1f979872011-05-13 01:16:07 -0500[diff] [blame]414
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]415#elif defined(CONFIG_PPC_P3041)
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]416#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700[diff] [blame]417#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]418#define CONFIG_MAX_CPUS 4
Kumar Galab5c87532011-02-16 02:03:29 -0600[diff] [blame]419#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]420#define CONFIG_SYS_FSL_NUM_LAWS 32
421#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galafbee0f72011-01-25 12:42:32 -0600[diff] [blame]422#define CONFIG_SYS_NUM_FMAN 1
423#define CONFIG_SYS_NUM_FM1_DTSEC 5
424#define CONFIG_SYS_NUM_FM1_10GEC 1
425#define CONFIG_NUM_DDR_CONTROLLERS 1
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]426#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]427#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600[diff] [blame]428#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]429#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]430#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang86221f02011-04-13 00:08:51 -0500[diff] [blame]431#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
432#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500[diff] [blame]433#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]434#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Lei Xu30009762011-04-19 15:28:41 +0800[diff] [blame]435#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun57125f22012-08-08 18:04:53 +0000[diff] [blame]436#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei99d7b0a2013-03-11 17:56:34 +0000[diff] [blame]437#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala43f082b2011-11-22 06:51:15 -0600[diff] [blame]438#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sune22be772013-03-25 07:30:11 +0000[diff] [blame]439#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun41085082011-11-20 10:01:35 -0800[diff] [blame]440#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]441#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
442#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
443#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000[diff] [blame]444#define CONFIG_SYS_FSL_ERRATUM_A004510
445#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
446#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
447#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000[diff] [blame]448#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi01180332012-10-25 12:40:00 +0000[diff] [blame]449#define CONFIG_SYS_FSL_ERRATUM_A004849
York Sund217a9a2013-06-25 11:37:49 -0700[diff] [blame]450#define CONFIG_SYS_FSL_ERRATUM_A005812
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800[diff] [blame]451#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Suresh Gupta9c641a82014-02-26 14:29:12 +0530[diff] [blame]452#define CONFIG_SYS_FSL_ERRATUM_A006261
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800[diff] [blame]453#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]454
Scott Wood3e978f52012-08-14 10:14:51 +0000[diff] [blame]455#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]456#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700[diff] [blame]457#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]458#define CONFIG_MAX_CPUS 8
Kumar Galab5c87532011-02-16 02:03:29 -0600[diff] [blame]459#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]460#define CONFIG_SYS_FSL_NUM_LAWS 32
461#define CONFIG_SYS_FSL_SEC_COMPAT 4
462#define CONFIG_SYS_NUM_FMAN 2
463#define CONFIG_SYS_NUM_FM1_DTSEC 4
464#define CONFIG_SYS_NUM_FM2_DTSEC 4
465#define CONFIG_SYS_NUM_FM1_10GEC 1
466#define CONFIG_SYS_NUM_FM2_10GEC 1
467#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]468#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]469#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]470#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600[diff] [blame]471#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]472#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]473#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]474#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
475#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sunfa8d23c2011-01-10 12:03:01 +0000[diff] [blame]476#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]477#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
478#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
479#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
Zang Roy-R619114e0be342012-09-18 09:50:08 +0000[diff] [blame]480#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]481#define CONFIG_SYS_P4080_ERRATUM_CPU22
York Sun5e23ab02012-05-07 07:26:47 +0000[diff] [blame]482#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]483#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medvedf8af0b2010-08-31 22:57:38 -0500[diff] [blame]484#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabid90fdba2011-04-18 17:16:00 -0500[diff] [blame]485#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabida30b9f2011-04-01 13:19:36 -0500[diff] [blame]486#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Gala43f082b2011-11-22 06:51:15 -0600[diff] [blame]487#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun41085082011-11-20 10:01:35 -0800[diff] [blame]488#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]489#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
490#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
491#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
492#define CONFIG_SYS_FSL_RMU
493#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Scott Wood33eee332012-08-14 10:14:53 +0000[diff] [blame]494#define CONFIG_SYS_FSL_ERRATUM_A004510
495#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
496#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
Liu Gangd59c5572012-09-28 21:26:19 +0000[diff] [blame]497#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi01180332012-10-25 12:40:00 +0000[diff] [blame]498#define CONFIG_SYS_FSL_ERRATUM_A004849
Timur Tabid607b962012-11-01 08:20:23 +0000[diff] [blame]499#define CONFIG_SYS_FSL_ERRATUM_A004580
Yuanquan Chenc0a4e6b2012-11-26 23:49:45 +0000[diff] [blame]500#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
York Sund217a9a2013-06-25 11:37:49 -0700[diff] [blame]501#define CONFIG_SYS_FSL_ERRATUM_A005812
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800[diff] [blame]502#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Nikhil Badola11856912014-02-26 17:43:15 +0530[diff] [blame]503#define CONFIG_SYS_FSL_ERRATUM_A007075
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800[diff] [blame]504#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]505
Scott Wood3e978f52012-08-14 10:14:51 +0000[diff] [blame]506#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
York Sunffd06e02012-10-08 07:44:30 +0000[diff] [blame]507#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]508#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700[diff] [blame]509#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]510#define CONFIG_MAX_CPUS 2
Kumar Galab5c87532011-02-16 02:03:29 -0600[diff] [blame]511#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]512#define CONFIG_SYS_FSL_NUM_LAWS 32
513#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galafbee0f72011-01-25 12:42:32 -0600[diff] [blame]514#define CONFIG_SYS_NUM_FMAN 1
515#define CONFIG_SYS_NUM_FM1_DTSEC 5
516#define CONFIG_SYS_NUM_FM1_10GEC 1
517#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]518#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]519#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Kumar Galac657d892011-02-04 00:43:34 -0600[diff] [blame]520#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala66412c62011-02-18 05:40:54 -0600[diff] [blame]521#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala8f290842011-05-20 00:39:21 -0500[diff] [blame]522#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]523#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang86221f02011-04-13 00:08:51 -0500[diff] [blame]524#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
525#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galab6c37222011-04-13 00:19:10 -0500[diff] [blame]526#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu30009762011-04-19 15:28:41 +0800[diff] [blame]527#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei99d7b0a2013-03-11 17:56:34 +0000[diff] [blame]528#define CONFIG_SYS_FSL_ERRATUM_USB14
York Sune22be772013-03-25 07:30:11 +0000[diff] [blame]529#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun41085082011-11-20 10:01:35 -0800[diff] [blame]530#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang7d67ed52012-03-08 00:33:14 +0000[diff] [blame]531#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
532#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
533#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood33eee332012-08-14 10:14:53 +0000[diff] [blame]534#define CONFIG_SYS_FSL_ERRATUM_A004510
535#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
536#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
Liu Gangd59c5572012-09-28 21:26:19 +0000[diff] [blame]537#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800[diff] [blame]538#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
Suresh Gupta9c641a82014-02-26 14:29:12 +0530[diff] [blame]539#define CONFIG_SYS_FSL_ERRATUM_A006261
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800[diff] [blame]540#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]541
Timur Tabi49054432012-10-05 11:09:19 +0000[diff] [blame]542#elif defined(CONFIG_PPC_P5040)
Timur Tabi1956e432012-10-23 10:48:09 +0000[diff] [blame]543#define CONFIG_SYS_PPC64
Timur Tabi49054432012-10-05 11:09:19 +0000[diff] [blame]544#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sund2ab4bb2013-06-25 11:37:39 -0700[diff] [blame]545#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Timur Tabi49054432012-10-05 11:09:19 +0000[diff] [blame]546#define CONFIG_MAX_CPUS 4
547#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
548#define CONFIG_SYS_FSL_NUM_LAWS 32
549#define CONFIG_SYS_FSL_SEC_COMPAT 4
550#define CONFIG_SYS_NUM_FMAN 2
551#define CONFIG_SYS_NUM_FM1_DTSEC 5
552#define CONFIG_SYS_NUM_FM1_10GEC 1
553#define CONFIG_SYS_NUM_FM2_DTSEC 5
554#define CONFIG_SYS_NUM_FM2_10GEC 1
555#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]556#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]557#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Timur Tabi49054432012-10-05 11:09:19 +0000[diff] [blame]558#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
559#define CONFIG_SYS_FSL_TBCLK_DIV 16
560#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
561#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
562#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
563#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
564#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
565#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei99d7b0a2013-03-11 17:56:34 +0000[diff] [blame]566#define CONFIG_SYS_FSL_ERRATUM_USB14
Timur Tabi49054432012-10-05 11:09:19 +0000[diff] [blame]567#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
568#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
569#define CONFIG_SYS_FSL_ERRATUM_A004699
Timur Tabi49054432012-10-05 11:09:19 +0000[diff] [blame]570#define CONFIG_SYS_FSL_ERRATUM_A004510
571#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
Suresh Gupta9c641a82014-02-26 14:29:12 +0530[diff] [blame]572#define CONFIG_SYS_FSL_ERRATUM_A006261
Timur Tabi49054432012-10-05 11:09:19 +0000[diff] [blame]573#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
York Sund217a9a2013-06-25 11:37:49 -0700[diff] [blame]574#define CONFIG_SYS_FSL_ERRATUM_A005812
Timur Tabi49054432012-10-05 11:09:19 +0000[diff] [blame]575
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000[diff] [blame]576#elif defined(CONFIG_BSC9131)
577#define CONFIG_MAX_CPUS 1
578#define CONFIG_FSL_SDHC_V2_3
579#define CONFIG_SYS_FSL_NUM_LAWS 12
580#define CONFIG_TSECV2
581#define CONFIG_SYS_FSL_SEC_COMPAT 4
582#define CONFIG_NUM_DDR_CONTROLLERS 1
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]583#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]584#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Priyanka Jain765b0bd2013-04-04 09:31:54 +0530[diff] [blame]585#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
586#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
Mingkai Hu362ee042013-05-16 10:18:13 +0800[diff] [blame]587#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000[diff] [blame]588#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
589#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000[diff] [blame]590#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]591#define CONFIG_SYS_FSL_ERRATUM_A005125
Haijun.Zhangf28bea02014-01-10 13:52:19 +0800[diff] [blame]592#define CONFIG_ESDHC_HC_BLK_ADDR
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +0000[diff] [blame]593
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000[diff] [blame]594#elif defined(CONFIG_BSC9132)
595#define CONFIG_MAX_CPUS 2
596#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
597#define CONFIG_FSL_SDHC_V2_3
598#define CONFIG_SYS_FSL_NUM_LAWS 12
599#define CONFIG_TSECV2
600#define CONFIG_SYS_FSL_SEC_COMPAT 4
601#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]602#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]603#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Priyanka Jain64501c62013-07-02 09:21:04 +0530[diff] [blame]604#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
605#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
606#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
607#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
York Sun061ffed2013-04-18 19:31:01 -0700[diff] [blame]608#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000[diff] [blame]609#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
610#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000[diff] [blame]611#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
612#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
613#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]614#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lanf1a96ec2014-05-07 10:50:20 +0800[diff] [blame]615#define CONFIG_SYS_FSL_ERRATUM_A005434
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800[diff] [blame]616#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
617#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Haijun.Zhangf28bea02014-01-10 13:52:19 +0800[diff] [blame]618#define CONFIG_ESDHC_HC_BLK_ADDR
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +0000[diff] [blame]619
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800[diff] [blame]620#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
621 defined(CONFIG_PPC_T4080)
York Sun3d2972f2013-03-25 07:40:05 +0000[diff] [blame]622#define CONFIG_E6500
York Sunffd06e02012-10-08 07:44:30 +0000[diff] [blame]623#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun9e758752012-10-08 07:44:19 +0000[diff] [blame]624#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
625#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
York Sunf6981432013-03-25 07:40:07 +0000[diff] [blame]626#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
York Sun9e758752012-10-08 07:44:19 +0000[diff] [blame]627#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
York Sun3d2972f2013-03-25 07:40:05 +0000[diff] [blame]628#ifdef CONFIG_PPC_T4240
York Sun9e758752012-10-08 07:44:19 +0000[diff] [blame]629#define CONFIG_MAX_CPUS 12
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530[diff] [blame]630#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
York Sun9e758752012-10-08 07:44:19 +0000[diff] [blame]631#define CONFIG_SYS_NUM_FM1_DTSEC 8
632#define CONFIG_SYS_NUM_FM1_10GEC 2
633#define CONFIG_SYS_NUM_FM2_DTSEC 8
634#define CONFIG_SYS_NUM_FM2_10GEC 2
635#define CONFIG_NUM_DDR_CONTROLLERS 3
York Sun3d2972f2013-03-25 07:40:05 +0000[diff] [blame]636#else
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800[diff] [blame]637#define CONFIG_SYS_NUM_FM1_DTSEC 6
York Sun3d2972f2013-03-25 07:40:05 +0000[diff] [blame]638#define CONFIG_SYS_NUM_FM1_10GEC 1
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800[diff] [blame]639#define CONFIG_SYS_NUM_FM2_DTSEC 8
York Sun3d2972f2013-03-25 07:40:05 +0000[diff] [blame]640#define CONFIG_SYS_NUM_FM2_10GEC 1
641#define CONFIG_NUM_DDR_CONTROLLERS 2
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800[diff] [blame]642#if defined(CONFIG_PPC_T4160)
643#define CONFIG_MAX_CPUS 8
644#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
645#elif defined(CONFIG_PPC_T4080)
646#define CONFIG_MAX_CPUS 4
647#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 }
648#endif
York Sun3d2972f2013-03-25 07:40:05 +0000[diff] [blame]649#endif
York Sunb6240842013-03-25 07:33:29 +0000[diff] [blame]650#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
651#define CONFIG_SYS_FSL_NUM_LAWS 32
Prabhakar Kushwahaa4c955b2013-07-31 16:56:41 +0530[diff] [blame]652#define CONFIG_SYS_FSL_SRDS_1
653#define CONFIG_SYS_FSL_SRDS_2
York Sunb6240842013-03-25 07:33:29 +0000[diff] [blame]654#define CONFIG_SYS_FSL_SRDS_3
655#define CONFIG_SYS_FSL_SRDS_4
656#define CONFIG_SYS_FSL_SEC_COMPAT 4
657#define CONFIG_SYS_NUM_FMAN 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]658#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530[diff] [blame]659#define CONFIG_SYS_PME_CLK 0
York Sunb6240842013-03-25 07:33:29 +0000[diff] [blame]660#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Mingkai Hu362ee042013-05-16 10:18:13 +0800[diff] [blame]661#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
York Sunb6240842013-03-25 07:33:29 +0000[diff] [blame]662#define CONFIG_SYS_FMAN_V3
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530[diff] [blame]663#define CONFIG_SYS_FM1_CLK 3
664#define CONFIG_SYS_FM2_CLK 3
York Sunb6240842013-03-25 07:33:29 +0000[diff] [blame]665#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
666#define CONFIG_SYS_FSL_TBCLK_DIV 16
667#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
668#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
669#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
670#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Liu Gang08047932013-06-25 18:12:14 +0800[diff] [blame]671#define CONFIG_SYS_FSL_SRIO_LIODN
York Sunb6240842013-03-25 07:33:29 +0000[diff] [blame]672#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
673#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
674#define CONFIG_SYS_FSL_ERRATUM_A004468
675#define CONFIG_SYS_FSL_ERRATUM_A_004934
676#define CONFIG_SYS_FSL_ERRATUM_A005871
Suresh Gupta9c641a82014-02-26 14:29:12 +0530[diff] [blame]677#define CONFIG_SYS_FSL_ERRATUM_A006261
York Sun133fbfa2013-09-16 12:49:31 -0700[diff] [blame]678#define CONFIG_SYS_FSL_ERRATUM_A006379
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530[diff] [blame]679#define CONFIG_SYS_FSL_ERRATUM_A007186
Scott Wood82125192013-05-15 17:50:13 -0500[diff] [blame]680#define CONFIG_SYS_FSL_ERRATUM_A006593
Nikhil Badolaf3dff692014-10-17 09:12:07 +0530[diff] [blame]681#define CONFIG_SYS_FSL_ERRATUM_A007798
York Sunb6240842013-03-25 07:33:29 +0000[diff] [blame]682#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530[diff] [blame]683#define CONFIG_SYS_FSL_SFP_VER_3_0
York Sunb6240842013-03-25 07:33:29 +0000[diff] [blame]684#define CONFIG_SYS_FSL_PCI_VER_3_X
685
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000[diff] [blame]686#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
687#define CONFIG_E6500
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000[diff] [blame]688#define CONFIG_SYS_PPC64 /* 64-bit core */
689#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
690#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
691#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000[diff] [blame]692#define CONFIG_SYS_FSL_NUM_LAWS 32
Prabhakar Kushwahaa4c955b2013-07-31 16:56:41 +0530[diff] [blame]693#define CONFIG_SYS_FSL_SRDS_1
694#define CONFIG_SYS_FSL_SRDS_2
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000[diff] [blame]695#define CONFIG_SYS_FSL_SEC_COMPAT 4
696#define CONFIG_SYS_NUM_FMAN 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]697#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530[diff] [blame]698#define CONFIG_SYS_FM1_CLK 0
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000[diff] [blame]699#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Mingkai Hu362ee042013-05-16 10:18:13 +0800[diff] [blame]700#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000[diff] [blame]701#define CONFIG_SYS_FMAN_V3
702#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
703#define CONFIG_SYS_FSL_TBCLK_DIV 16
704#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
705#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
706#define CONFIG_SYS_FSL_ERRATUM_A_004934
Shengzhou Liu04feb572013-02-27 21:56:54 +0000[diff] [blame]707#define CONFIG_SYS_FSL_ERRATUM_A005871
York Sun133fbfa2013-09-16 12:49:31 -0700[diff] [blame]708#define CONFIG_SYS_FSL_ERRATUM_A006379
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530[diff] [blame]709#define CONFIG_SYS_FSL_ERRATUM_A007186
Scott Wood82125192013-05-15 17:50:13 -0500[diff] [blame]710#define CONFIG_SYS_FSL_ERRATUM_A006593
Nikhil Badola11856912014-02-26 17:43:15 +0530[diff] [blame]711#define CONFIG_SYS_FSL_ERRATUM_A007075
Shaveta Leekha7af9a072014-02-26 16:08:22 +0530[diff] [blame]712#define CONFIG_SYS_FSL_ERRATUM_A006475
713#define CONFIG_SYS_FSL_ERRATUM_A006384
York Sunc3678b02014-03-28 15:07:27 -0700[diff] [blame]714#define CONFIG_SYS_FSL_ERRATUM_A007212
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000[diff] [blame]715#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530[diff] [blame]716#define CONFIG_SYS_FSL_SFP_VER_3_0
Poonam Aggrwale1dbdd82012-12-23 19:24:16 +0000[diff] [blame]717
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000[diff] [blame]718#ifdef CONFIG_PPC_B4860
York Sunf6981432013-03-25 07:40:07 +0000[diff] [blame]719#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
York Sund2404142012-10-08 07:44:20 +0000[diff] [blame]720#define CONFIG_MAX_CPUS 4
Shaveta Leekha6df82e32014-02-26 16:07:37 +0530[diff] [blame]721#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
York Sund2404142012-10-08 07:44:20 +0000[diff] [blame]722#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530[diff] [blame]723#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
York Sund2404142012-10-08 07:44:20 +0000[diff] [blame]724#define CONFIG_SYS_NUM_FM1_DTSEC 6
725#define CONFIG_SYS_NUM_FM1_10GEC 2
Poonam Aggrwale394ceb2012-12-23 19:22:33 +0000[diff] [blame]726#define CONFIG_NUM_DDR_CONTROLLERS 2
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]727#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
York Sund2404142012-10-08 07:44:20 +0000[diff] [blame]728#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
729#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
730#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Liu Gang32f38ee2013-06-25 18:12:13 +0800[diff] [blame]731#define CONFIG_SYS_FSL_SRIO_LIODN
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000[diff] [blame]732#else
733#define CONFIG_MAX_CPUS 2
Shaveta Leekha6df82e32014-02-26 16:07:37 +0530[diff] [blame]734#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000[diff] [blame]735#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
736#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530[diff] [blame]737#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
Poonam Aggrwal8fa01022013-03-25 07:40:20 +0000[diff] [blame]738#define CONFIG_SYS_NUM_FM1_DTSEC 4
739#define CONFIG_SYS_NUM_FM1_10GEC 0
740#define CONFIG_NUM_DDR_CONTROLLERS 1
741#endif
York Sund2404142012-10-08 07:44:20 +0000[diff] [blame]742
Priyanka Jain2967af62013-10-18 12:30:21 +0530[diff] [blame]743#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
744defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]745#define CONFIG_E5500
746#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
747#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
York Sunf6981432013-03-25 07:40:07 +0000[diff] [blame]748#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]749#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]750#ifdef CONFIG_SYS_FSL_DDR4
751#define CONFIG_SYS_FSL_DDRC_GEN4
752#endif
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530[diff] [blame]753#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]754#define CONFIG_MAX_CPUS 4
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530[diff] [blame]755#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
756#define CONFIG_MAX_CPUS 2
757#endif
758#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530[diff] [blame]759#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
760#define CONFIG_SYS_SDHC_CLOCK 0
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]761#define CONFIG_SYS_FSL_NUM_LAWS 16
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530[diff] [blame]762#define CONFIG_SYS_FSL_SRDS_1
763#define CONFIG_SYS_FSL_SEC_COMPAT 5
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]764#define CONFIG_SYS_NUM_FMAN 1
765#define CONFIG_SYS_NUM_FM1_DTSEC 5
766#define CONFIG_NUM_DDR_CONTROLLERS 1
ramneek mehreshf1810d82013-10-18 17:40:17 +0530[diff] [blame]767#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530[diff] [blame]768#define CONFIG_PME_PLAT_CLK_DIV 2
769#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530[diff] [blame]770#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
771#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
Prabhakar Kushwaha9f074e62014-10-29 22:33:09 +0530[diff] [blame]772#define CONFIG_SYS_FSL_ERRATUM_A008044
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]773#define CONFIG_SYS_FMAN_V3
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530[diff] [blame]774#define CONFIG_FM_PLAT_CLK_DIV 1
775#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
Prabhakar Kushwaha1d384ec2013-09-03 11:19:54 +0530[diff] [blame]776#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
Priyanka Jainb1359912013-12-17 14:25:52 +0530[diff] [blame]777#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
Prabhakar Kushwahae03c76c2013-12-11 12:49:13 +0530[diff] [blame]778#define CONFIG_SYS_FSL_TBCLK_DIV 16
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]779#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
Nikhil Badolaa4f7cba2014-01-27 15:21:58 +0530[diff] [blame]780#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]781#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Suresh Gupta9c641a82014-02-26 14:29:12 +0530[diff] [blame]782#define CONFIG_SYS_FSL_ERRATUM_A006261
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]783#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Haijun.Zhang1336e2d2014-03-18 17:04:23 +0800[diff] [blame]784#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
785#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
Zhao Qiang2a44efe2014-03-21 16:21:45 +0800[diff] [blame]786#define QE_MURAM_SIZE 0x6000UL
787#define MAX_QE_RISC 1
788#define QE_NUM_OF_SNUM 28
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]789
Shengzhou Liuf6050792014-11-24 17:11:54 +0800[diff] [blame]790#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
791defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
792#define CONFIG_E5500
793#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
794#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
795#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
796#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
797#define CONFIG_SYS_FMAN_V3
798#ifdef CONFIG_SYS_FSL_DDR4
799#define CONFIG_SYS_FSL_DDRC_GEN4
800#endif
801#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
802#define CONFIG_MAX_CPUS 2
803#elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
804#define CONFIG_MAX_CPUS 1
805#endif
806#define CONFIG_SYS_FSL_NUM_CC_PLL 2
807#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
808#define CONFIG_SYS_SDHC_CLOCK 0
809#define CONFIG_SYS_FSL_NUM_LAWS 16
810#define CONFIG_SYS_FSL_SRDS_1
811#define CONFIG_SYS_FSL_SEC_COMPAT 5
812#define CONFIG_SYS_NUM_FMAN 1
813#define CONFIG_SYS_NUM_FM1_DTSEC 4
814#define CONFIG_SYS_NUM_FM1_10GEC 1
Shengzhou Liucc19c252014-11-24 17:11:57 +0800[diff] [blame]815#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
Shengzhou Liuf6050792014-11-24 17:11:54 +0800[diff] [blame]816#define CONFIG_NUM_DDR_CONTROLLERS 1
817#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
818#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
819#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
820#define CONFIG_SYS_FM1_CLK 0
821#define CONFIG_QBMAN_CLK_DIV 1
822#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
823#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
824#define CONFIG_SYS_FSL_TBCLK_DIV 16
825#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
826#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
827#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
828#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
829#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
830#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
831#define QE_MURAM_SIZE 0x6000UL
832#define MAX_QE_RISC 1
833#define QE_NUM_OF_SNUM 28
834#define CONFIG_SYS_FSL_SFP_VER_3_0
835
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800[diff] [blame]836#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
837#define CONFIG_E6500
838#define CONFIG_SYS_PPC64 /* 64-bit core */
839#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
840#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
841#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
842#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
843#define CONFIG_SYS_FSL_QMAN_V3
844#define CONFIG_MAX_CPUS 4
845#define CONFIG_SYS_FSL_NUM_LAWS 32
846#define CONFIG_SYS_FSL_SEC_COMPAT 4
847#define CONFIG_SYS_NUM_FMAN 1
848#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
849#define CONFIG_SYS_FSL_SRDS_1
850#define CONFIG_SYS_FSL_PCI_VER_3_X
851#if defined(CONFIG_PPC_T2080)
852#define CONFIG_SYS_NUM_FM1_DTSEC 8
853#define CONFIG_SYS_NUM_FM1_10GEC 4
854#define CONFIG_SYS_FSL_SRDS_2
855#define CONFIG_SYS_FSL_SRIO_LIODN
856#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
857#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
858#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
859#elif defined(CONFIG_PPC_T2081)
860#define CONFIG_SYS_NUM_FM1_DTSEC 6
861#define CONFIG_SYS_NUM_FM1_10GEC 2
862#endif
Shengzhou Liu2ffa96d2013-12-18 10:27:55 +0800[diff] [blame]863#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800[diff] [blame]864#define CONFIG_NUM_DDR_CONTROLLERS 1
865#define CONFIG_PME_PLAT_CLK_DIV 1
866#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
867#define CONFIG_SYS_FM1_CLK 0
868#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
869#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
870#define CONFIG_SYS_FMAN_V3
871#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
872#define CONFIG_SYS_FSL_TBCLK_DIV 16
873#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
874#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
875#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
York Sunc3678b02014-03-28 15:07:27 -0700[diff] [blame]876#define CONFIG_SYS_FSL_ERRATUM_A007212
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800[diff] [blame]877#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
878#define CONFIG_SYS_FSL_SFP_VER_3_0
879#define CONFIG_SYS_FSL_ISBC_VER 2
Haijun.Zhang1336e2d2014-03-18 17:04:23 +0800[diff] [blame]880#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Shengzhou Liuc665c472014-04-24 11:10:09 +0800[diff] [blame]881#define CONFIG_SYS_FSL_ERRATUM_A006261
882#define CONFIG_SYS_FSL_ERRATUM_A006593
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530[diff] [blame]883#define CONFIG_SYS_FSL_ERRATUM_A007186
Shengzhou Liuc665c472014-04-24 11:10:09 +0800[diff] [blame]884#define CONFIG_SYS_FSL_ERRATUM_A006379
Haijun.Zhang1336e2d2014-03-18 17:04:23 +0800[diff] [blame]885#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
Shaveta Leekhab6808cd2014-05-28 14:18:55 +0530[diff] [blame]886#define CONFIG_SYS_FSL_SFP_VER_3_0
Haijun.Zhang1336e2d2014-03-18 17:04:23 +0800[diff] [blame]887
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800[diff] [blame]888
Mingkai Hu3b75e982013-07-04 17:30:36 +0800[diff] [blame]889#elif defined(CONFIG_PPC_C29X)
890#define CONFIG_MAX_CPUS 1
891#define CONFIG_FSL_SDHC_V2_3
892#define CONFIG_SYS_FSL_NUM_LAWS 12
893#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
894#define CONFIG_TSECV2_1
895#define CONFIG_SYS_FSL_SEC_COMPAT 6
896#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
897#define CONFIG_NUM_DDR_CONTROLLERS 1
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]898#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
Mingkai Hu3b75e982013-07-04 17:30:36 +0800[diff] [blame]899#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
900#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun954a1a42013-08-20 15:09:43 -0700[diff] [blame]901#define CONFIG_SYS_FSL_ERRATUM_A005125
Mingkai Hu3b75e982013-07-04 17:30:36 +0800[diff] [blame]902
Alexander Graffa08d392014-04-11 17:09:45 +0200[diff] [blame]903#elif defined(CONFIG_QEMU_E500)
904#define CONFIG_MAX_CPUS 1
905#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
906
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]907#else
908#error Processor type not defined for this platform
909#endif
910
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]911#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
912#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
913#endif
914
York Sunf6981432013-03-25 07:40:07 +0000[diff] [blame]915#ifdef CONFIG_E6500
916#define CONFIG_SYS_FSL_THREADS_PER_CORE 2
917#else
918#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
919#endif
920
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]921#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
922 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
York Sun34e026f2014-03-27 17:54:47 -0700[diff] [blame]923 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
924 !defined(CONFIG_SYS_FSL_DDRC_GEN4)
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]925#define CONFIG_SYS_FSL_DDRC_GEN3
926#endif
927
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]928#endif /* _ASM_MPC85xx_CONFIG_H_ */