Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 1 | /* |
Kumar Gala | 4c2e3da | 2009-07-28 21:49:52 -0500 | [diff] [blame] | 2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 3 | * Author: Jason Jin<Jason.jin@freescale.com> |
| 4 | * Zhang Wei<wei.zhang@freescale.com> |
| 5 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 7 | * |
| 8 | * with the reference on libata and ahci drvier in kernel |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 9 | */ |
| 10 | #include <common.h> |
| 11 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 12 | #include <command.h> |
| 13 | #include <pci.h> |
| 14 | #include <asm/processor.h> |
| 15 | #include <asm/errno.h> |
| 16 | #include <asm/io.h> |
| 17 | #include <malloc.h> |
| 18 | #include <scsi.h> |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 19 | #include <libata.h> |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 20 | #include <linux/ctype.h> |
| 21 | #include <ahci.h> |
| 22 | |
Marc Jones | 766b16f | 2012-10-29 05:24:02 +0000 | [diff] [blame] | 23 | static int ata_io_flush(u8 port); |
| 24 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 25 | struct ahci_probe_ent *probe_ent = NULL; |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 26 | u16 *ataid[AHCI_MAX_PORTS]; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 27 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 28 | #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) |
| 29 | |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 30 | /* |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 31 | * Some controllers limit number of blocks they can read/write at once. |
| 32 | * Contemporary SSD devices work much faster if the read/write size is aligned |
| 33 | * to a power of 2. Let's set default to 128 and allowing to be overwritten if |
| 34 | * needed. |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 35 | */ |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 36 | #ifndef MAX_SATA_BLOCKS_READ_WRITE |
| 37 | #define MAX_SATA_BLOCKS_READ_WRITE 0x80 |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 38 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 39 | |
Walter Murphy | 5784766 | 2012-10-29 05:24:00 +0000 | [diff] [blame] | 40 | /* Maximum timeouts for each event */ |
Rob Herring | 7610b41 | 2013-08-24 10:10:53 -0500 | [diff] [blame] | 41 | #define WAIT_MS_SPINUP 20000 |
Walter Murphy | 5784766 | 2012-10-29 05:24:00 +0000 | [diff] [blame] | 42 | #define WAIT_MS_DATAIO 5000 |
Marc Jones | 766b16f | 2012-10-29 05:24:02 +0000 | [diff] [blame] | 43 | #define WAIT_MS_FLUSH 5000 |
Ian Campbell | e0ddcf9 | 2014-07-18 20:38:39 +0100 | [diff] [blame] | 44 | #define WAIT_MS_LINKUP 200 |
Walter Murphy | 5784766 | 2012-10-29 05:24:00 +0000 | [diff] [blame] | 45 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 46 | static inline u32 ahci_port_base(u32 base, u32 port) |
| 47 | { |
| 48 | return base + 0x100 + (port * 0x80); |
| 49 | } |
| 50 | |
| 51 | |
| 52 | static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, |
| 53 | unsigned int port_idx) |
| 54 | { |
| 55 | base = ahci_port_base(base, port_idx); |
| 56 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 57 | port->cmd_addr = base; |
| 58 | port->scr_addr = base + PORT_SCR; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 59 | } |
| 60 | |
| 61 | |
| 62 | #define msleep(a) udelay(a * 1000) |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 63 | |
Taylor Hutt | 90b276f | 2012-10-29 05:23:59 +0000 | [diff] [blame] | 64 | static void ahci_dcache_flush_range(unsigned begin, unsigned len) |
| 65 | { |
| 66 | const unsigned long start = begin; |
| 67 | const unsigned long end = start + len; |
| 68 | |
| 69 | debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end); |
| 70 | flush_dcache_range(start, end); |
| 71 | } |
| 72 | |
| 73 | /* |
| 74 | * SATA controller DMAs to physical RAM. Ensure data from the |
| 75 | * controller is invalidated from dcache; next access comes from |
| 76 | * physical RAM. |
| 77 | */ |
| 78 | static void ahci_dcache_invalidate_range(unsigned begin, unsigned len) |
| 79 | { |
| 80 | const unsigned long start = begin; |
| 81 | const unsigned long end = start + len; |
| 82 | |
| 83 | debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end); |
| 84 | invalidate_dcache_range(start, end); |
| 85 | } |
| 86 | |
| 87 | /* |
| 88 | * Ensure data for SATA controller is flushed out of dcache and |
| 89 | * written to physical memory. |
| 90 | */ |
| 91 | static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp) |
| 92 | { |
| 93 | ahci_dcache_flush_range((unsigned long)pp->cmd_slot, |
| 94 | AHCI_PORT_PRIV_DMA_SZ); |
| 95 | } |
| 96 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 97 | static int waiting_for_cmd_completed(volatile u8 *offset, |
| 98 | int timeout_msec, |
| 99 | u32 sign) |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 100 | { |
| 101 | int i; |
| 102 | u32 status; |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 103 | |
| 104 | for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 105 | msleep(1); |
| 106 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 107 | return (i < timeout_msec) ? 0 : -1; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 108 | } |
| 109 | |
Rob Herring | 124e9fa | 2013-08-24 10:10:51 -0500 | [diff] [blame] | 110 | int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port) |
| 111 | { |
| 112 | u32 tmp; |
| 113 | int j = 0; |
| 114 | u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio; |
| 115 | |
Wolfgang Denk | 3765b3e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 116 | /* |
Rob Herring | 124e9fa | 2013-08-24 10:10:51 -0500 | [diff] [blame] | 117 | * Bring up SATA link. |
| 118 | * SATA link bringup time is usually less than 1 ms; only very |
| 119 | * rarely has it taken between 1-2 ms. Never seen it above 2 ms. |
| 120 | */ |
| 121 | while (j < WAIT_MS_LINKUP) { |
| 122 | tmp = readl(port_mmio + PORT_SCR_STAT); |
| 123 | tmp &= PORT_SCR_STAT_DET_MASK; |
| 124 | if (tmp == PORT_SCR_STAT_DET_PHYRDY) |
| 125 | return 0; |
| 126 | udelay(1000); |
| 127 | j++; |
| 128 | } |
| 129 | return 1; |
| 130 | } |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 131 | |
Ian Campbell | a6e50a8 | 2014-07-18 20:38:41 +0100 | [diff] [blame] | 132 | #ifdef CONFIG_SUNXI_AHCI |
| 133 | /* The sunxi AHCI controller requires this undocumented setup */ |
| 134 | static void sunxi_dma_init(volatile u8 *port_mmio) |
| 135 | { |
| 136 | clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400); |
| 137 | } |
| 138 | #endif |
| 139 | |
Scott Wood | 9efaca3 | 2015-04-17 09:19:01 -0500 | [diff] [blame] | 140 | int ahci_reset(void __iomem *base) |
Dmitry Lifshitz | 6b68888 | 2014-12-15 16:02:55 +0200 | [diff] [blame] | 141 | { |
| 142 | int i = 1000; |
Scott Wood | 9efaca3 | 2015-04-17 09:19:01 -0500 | [diff] [blame] | 143 | u32 __iomem *host_ctl_reg = base + HOST_CTL; |
Dmitry Lifshitz | 6b68888 | 2014-12-15 16:02:55 +0200 | [diff] [blame] | 144 | u32 tmp = readl(host_ctl_reg); /* global controller reset */ |
| 145 | |
| 146 | if ((tmp & HOST_RESET) == 0) |
| 147 | writel_with_flush(tmp | HOST_RESET, host_ctl_reg); |
| 148 | |
| 149 | /* |
| 150 | * reset must complete within 1 second, or |
| 151 | * the hardware should be considered fried. |
| 152 | */ |
| 153 | do { |
| 154 | udelay(1000); |
| 155 | tmp = readl(host_ctl_reg); |
| 156 | i--; |
| 157 | } while ((i > 0) && (tmp & HOST_RESET)); |
| 158 | |
| 159 | if (i == 0) { |
| 160 | printf("controller reset failed (0x%x)\n", tmp); |
| 161 | return -1; |
| 162 | } |
| 163 | |
| 164 | return 0; |
| 165 | } |
| 166 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 167 | static int ahci_host_init(struct ahci_probe_ent *probe_ent) |
| 168 | { |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 169 | #ifndef CONFIG_SCSI_AHCI_PLAT |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 170 | pci_dev_t pdev = probe_ent->dev; |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 171 | u16 tmp16; |
| 172 | unsigned short vendor; |
| 173 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 174 | volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; |
Marc Jones | 2a0c61d | 2012-10-29 05:24:01 +0000 | [diff] [blame] | 175 | u32 tmp, cap_save, cmd; |
Rob Herring | 124e9fa | 2013-08-24 10:10:51 -0500 | [diff] [blame] | 176 | int i, j, ret; |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 177 | volatile u8 *port_mmio; |
Richard Gibbs | 2915a02 | 2013-08-24 10:10:47 -0500 | [diff] [blame] | 178 | u32 port_map; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 179 | |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 180 | debug("ahci_host_init: start\n"); |
| 181 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 182 | cap_save = readl(mmio + HOST_CAP); |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 183 | cap_save &= ((1 << 28) | (1 << 17)); |
Marc Jones | 2a0c61d | 2012-10-29 05:24:01 +0000 | [diff] [blame] | 184 | cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 185 | |
Dmitry Lifshitz | 6b68888 | 2014-12-15 16:02:55 +0200 | [diff] [blame] | 186 | ret = ahci_reset(probe_ent->mmio_base); |
| 187 | if (ret) |
| 188 | return ret; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 189 | |
| 190 | writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); |
| 191 | writel(cap_save, mmio + HOST_CAP); |
| 192 | writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); |
| 193 | |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 194 | #ifndef CONFIG_SCSI_AHCI_PLAT |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 195 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); |
| 196 | |
| 197 | if (vendor == PCI_VENDOR_ID_INTEL) { |
| 198 | u16 tmp16; |
| 199 | pci_read_config_word(pdev, 0x92, &tmp16); |
| 200 | tmp16 |= 0xf; |
| 201 | pci_write_config_word(pdev, 0x92, tmp16); |
| 202 | } |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 203 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 204 | probe_ent->cap = readl(mmio + HOST_CAP); |
| 205 | probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); |
Richard Gibbs | 2915a02 | 2013-08-24 10:10:47 -0500 | [diff] [blame] | 206 | port_map = probe_ent->port_map; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 207 | probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; |
| 208 | |
| 209 | debug("cap 0x%x port_map 0x%x n_ports %d\n", |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 210 | probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 211 | |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 212 | if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID) |
| 213 | probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID; |
| 214 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 215 | for (i = 0; i < probe_ent->n_ports; i++) { |
Richard Gibbs | 2915a02 | 2013-08-24 10:10:47 -0500 | [diff] [blame] | 216 | if (!(port_map & (1 << i))) |
| 217 | continue; |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 218 | probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); |
| 219 | port_mmio = (u8 *) probe_ent->port[i].port_mmio; |
| 220 | ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 221 | |
| 222 | /* make sure port is not active */ |
| 223 | tmp = readl(port_mmio + PORT_CMD); |
| 224 | if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | |
| 225 | PORT_CMD_FIS_RX | PORT_CMD_START)) { |
Stefan Reinauer | 7ba7917 | 2012-10-29 05:23:50 +0000 | [diff] [blame] | 226 | debug("Port %d is active. Deactivating.\n", i); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 227 | tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | |
| 228 | PORT_CMD_FIS_RX | PORT_CMD_START); |
| 229 | writel_with_flush(tmp, port_mmio + PORT_CMD); |
| 230 | |
| 231 | /* spec says 500 msecs for each bit, so |
| 232 | * this is slightly incorrect. |
| 233 | */ |
| 234 | msleep(500); |
| 235 | } |
| 236 | |
Ian Campbell | a6e50a8 | 2014-07-18 20:38:41 +0100 | [diff] [blame] | 237 | #ifdef CONFIG_SUNXI_AHCI |
| 238 | sunxi_dma_init(port_mmio); |
| 239 | #endif |
| 240 | |
Marc Jones | 2a0c61d | 2012-10-29 05:24:01 +0000 | [diff] [blame] | 241 | /* Add the spinup command to whatever mode bits may |
| 242 | * already be on in the command register. |
| 243 | */ |
| 244 | cmd = readl(port_mmio + PORT_CMD); |
Marc Jones | 2a0c61d | 2012-10-29 05:24:01 +0000 | [diff] [blame] | 245 | cmd |= PORT_CMD_SPIN_UP; |
| 246 | writel_with_flush(cmd, port_mmio + PORT_CMD); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 247 | |
Rob Herring | 124e9fa | 2013-08-24 10:10:51 -0500 | [diff] [blame] | 248 | /* Bring up SATA link. */ |
| 249 | ret = ahci_link_up(probe_ent, i); |
| 250 | if (ret) { |
Marc Jones | 2a0c61d | 2012-10-29 05:24:01 +0000 | [diff] [blame] | 251 | printf("SATA link %d timeout.\n", i); |
| 252 | continue; |
| 253 | } else { |
| 254 | debug("SATA link ok.\n"); |
| 255 | } |
| 256 | |
| 257 | /* Clear error status */ |
| 258 | tmp = readl(port_mmio + PORT_SCR_ERR); |
| 259 | if (tmp) |
| 260 | writel(tmp, port_mmio + PORT_SCR_ERR); |
| 261 | |
| 262 | debug("Spinning up device on SATA port %d... ", i); |
| 263 | |
| 264 | j = 0; |
| 265 | while (j < WAIT_MS_SPINUP) { |
| 266 | tmp = readl(port_mmio + PORT_TFDATA); |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 267 | if (!(tmp & (ATA_BUSY | ATA_DRQ))) |
Marc Jones | 2a0c61d | 2012-10-29 05:24:01 +0000 | [diff] [blame] | 268 | break; |
| 269 | udelay(1000); |
Rob Herring | 1782108 | 2013-08-24 10:10:52 -0500 | [diff] [blame] | 270 | tmp = readl(port_mmio + PORT_SCR_STAT); |
| 271 | tmp &= PORT_SCR_STAT_DET_MASK; |
| 272 | if (tmp == PORT_SCR_STAT_DET_PHYRDY) |
| 273 | break; |
Marc Jones | 2a0c61d | 2012-10-29 05:24:01 +0000 | [diff] [blame] | 274 | j++; |
| 275 | } |
Rob Herring | 1782108 | 2013-08-24 10:10:52 -0500 | [diff] [blame] | 276 | |
| 277 | tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK; |
| 278 | if (tmp == PORT_SCR_STAT_DET_COMINIT) { |
| 279 | debug("SATA link %d down (COMINIT received), retrying...\n", i); |
| 280 | i--; |
| 281 | continue; |
| 282 | } |
| 283 | |
Marc Jones | 2a0c61d | 2012-10-29 05:24:01 +0000 | [diff] [blame] | 284 | printf("Target spinup took %d ms.\n", j); |
| 285 | if (j == WAIT_MS_SPINUP) |
Stefan Reinauer | 9a65b87 | 2012-10-29 05:23:49 +0000 | [diff] [blame] | 286 | debug("timeout.\n"); |
| 287 | else |
| 288 | debug("ok.\n"); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 289 | |
| 290 | tmp = readl(port_mmio + PORT_SCR_ERR); |
| 291 | debug("PORT_SCR_ERR 0x%x\n", tmp); |
| 292 | writel(tmp, port_mmio + PORT_SCR_ERR); |
| 293 | |
| 294 | /* ack any pending irq events for this port */ |
| 295 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 296 | debug("PORT_IRQ_STAT 0x%x\n", tmp); |
| 297 | if (tmp) |
| 298 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
| 299 | |
| 300 | writel(1 << i, mmio + HOST_IRQ_STAT); |
| 301 | |
| 302 | /* set irq mask (enables interrupts) */ |
| 303 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); |
| 304 | |
Stefan Reinauer | 4e422bc | 2012-10-29 05:23:51 +0000 | [diff] [blame] | 305 | /* register linkup ports */ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 306 | tmp = readl(port_mmio + PORT_SCR_STAT); |
Marc Jones | 766b16f | 2012-10-29 05:24:02 +0000 | [diff] [blame] | 307 | debug("SATA port %d status: 0x%x\n", i, tmp); |
Rob Herring | 2bdb10d | 2013-08-24 10:10:50 -0500 | [diff] [blame] | 308 | if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY) |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 309 | probe_ent->link_port_map |= (0x01 << i); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 310 | } |
| 311 | |
| 312 | tmp = readl(mmio + HOST_CTL); |
| 313 | debug("HOST_CTL 0x%x\n", tmp); |
| 314 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); |
| 315 | tmp = readl(mmio + HOST_CTL); |
| 316 | debug("HOST_CTL 0x%x\n", tmp); |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 317 | #ifndef CONFIG_SCSI_AHCI_PLAT |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 318 | pci_read_config_word(pdev, PCI_COMMAND, &tmp16); |
| 319 | tmp |= PCI_COMMAND_MASTER; |
| 320 | pci_write_config_word(pdev, PCI_COMMAND, tmp16); |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 321 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 322 | return 0; |
| 323 | } |
| 324 | |
| 325 | |
| 326 | static void ahci_print_info(struct ahci_probe_ent *probe_ent) |
| 327 | { |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 328 | #ifndef CONFIG_SCSI_AHCI_PLAT |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 329 | pci_dev_t pdev = probe_ent->dev; |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 330 | u16 cc; |
| 331 | #endif |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 332 | volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; |
Stefan Reinauer | 4e422bc | 2012-10-29 05:23:51 +0000 | [diff] [blame] | 333 | u32 vers, cap, cap2, impl, speed; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 334 | const char *speed_s; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 335 | const char *scc_s; |
| 336 | |
| 337 | vers = readl(mmio + HOST_VERSION); |
| 338 | cap = probe_ent->cap; |
Stefan Reinauer | 4e422bc | 2012-10-29 05:23:51 +0000 | [diff] [blame] | 339 | cap2 = readl(mmio + HOST_CAP2); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 340 | impl = probe_ent->port_map; |
| 341 | |
| 342 | speed = (cap >> 20) & 0xf; |
| 343 | if (speed == 1) |
| 344 | speed_s = "1.5"; |
| 345 | else if (speed == 2) |
| 346 | speed_s = "3"; |
Stefan Reinauer | 4e422bc | 2012-10-29 05:23:51 +0000 | [diff] [blame] | 347 | else if (speed == 3) |
| 348 | speed_s = "6"; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 349 | else |
| 350 | speed_s = "?"; |
| 351 | |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 352 | #ifdef CONFIG_SCSI_AHCI_PLAT |
| 353 | scc_s = "SATA"; |
| 354 | #else |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 355 | pci_read_config_word(pdev, 0x0a, &cc); |
| 356 | if (cc == 0x0101) |
| 357 | scc_s = "IDE"; |
| 358 | else if (cc == 0x0106) |
| 359 | scc_s = "SATA"; |
| 360 | else if (cc == 0x0104) |
| 361 | scc_s = "RAID"; |
| 362 | else |
| 363 | scc_s = "unknown"; |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 364 | #endif |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 365 | printf("AHCI %02x%02x.%02x%02x " |
| 366 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n", |
| 367 | (vers >> 24) & 0xff, |
| 368 | (vers >> 16) & 0xff, |
| 369 | (vers >> 8) & 0xff, |
| 370 | vers & 0xff, |
| 371 | ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 372 | |
| 373 | printf("flags: " |
Stefan Reinauer | 4e422bc | 2012-10-29 05:23:51 +0000 | [diff] [blame] | 374 | "%s%s%s%s%s%s%s" |
| 375 | "%s%s%s%s%s%s%s" |
| 376 | "%s%s%s%s%s%s\n", |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 377 | cap & (1 << 31) ? "64bit " : "", |
| 378 | cap & (1 << 30) ? "ncq " : "", |
| 379 | cap & (1 << 28) ? "ilck " : "", |
| 380 | cap & (1 << 27) ? "stag " : "", |
| 381 | cap & (1 << 26) ? "pm " : "", |
| 382 | cap & (1 << 25) ? "led " : "", |
| 383 | cap & (1 << 24) ? "clo " : "", |
| 384 | cap & (1 << 19) ? "nz " : "", |
| 385 | cap & (1 << 18) ? "only " : "", |
| 386 | cap & (1 << 17) ? "pmp " : "", |
Stefan Reinauer | 4e422bc | 2012-10-29 05:23:51 +0000 | [diff] [blame] | 387 | cap & (1 << 16) ? "fbss " : "", |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 388 | cap & (1 << 15) ? "pio " : "", |
| 389 | cap & (1 << 14) ? "slum " : "", |
Stefan Reinauer | 4e422bc | 2012-10-29 05:23:51 +0000 | [diff] [blame] | 390 | cap & (1 << 13) ? "part " : "", |
| 391 | cap & (1 << 7) ? "ccc " : "", |
| 392 | cap & (1 << 6) ? "ems " : "", |
| 393 | cap & (1 << 5) ? "sxs " : "", |
| 394 | cap2 & (1 << 2) ? "apst " : "", |
| 395 | cap2 & (1 << 1) ? "nvmp " : "", |
| 396 | cap2 & (1 << 0) ? "boh " : ""); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 397 | } |
| 398 | |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 399 | #ifndef CONFIG_SCSI_AHCI_PLAT |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 400 | static int ahci_init_one(pci_dev_t pdev) |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 401 | { |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 402 | u16 vendor; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 403 | int rc; |
| 404 | |
Ed Swarthout | 594e798 | 2007-08-14 14:06:45 -0500 | [diff] [blame] | 405 | probe_ent = malloc(sizeof(struct ahci_probe_ent)); |
Roger Quadros | d73763a | 2013-11-11 16:56:37 +0200 | [diff] [blame] | 406 | if (!probe_ent) { |
| 407 | printf("%s: No memory for probe_ent\n", __func__); |
| 408 | return -ENOMEM; |
| 409 | } |
| 410 | |
Ed Swarthout | 594e798 | 2007-08-14 14:06:45 -0500 | [diff] [blame] | 411 | memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 412 | probe_ent->dev = pdev; |
| 413 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 414 | probe_ent->host_flags = ATA_FLAG_SATA |
| 415 | | ATA_FLAG_NO_LEGACY |
| 416 | | ATA_FLAG_MMIO |
| 417 | | ATA_FLAG_PIO_DMA |
| 418 | | ATA_FLAG_NO_ATAPI; |
| 419 | probe_ent->pio_mask = 0x1f; |
| 420 | probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 421 | |
Scott Wood | 9efaca3 | 2015-04-17 09:19:01 -0500 | [diff] [blame] | 422 | probe_ent->mmio_base = pci_map_bar(pdev, PCI_BASE_ADDRESS_5, |
| 423 | PCI_REGION_MEM); |
| 424 | debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 425 | |
| 426 | /* Take from kernel: |
| 427 | * JMicron-specific fixup: |
| 428 | * make sure we're in AHCI mode |
| 429 | */ |
| 430 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 431 | if (vendor == 0x197b) |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 432 | pci_write_config_byte(pdev, 0x41, 0xa1); |
| 433 | |
| 434 | /* initialize adapter */ |
| 435 | rc = ahci_host_init(probe_ent); |
| 436 | if (rc) |
| 437 | goto err_out; |
| 438 | |
| 439 | ahci_print_info(probe_ent); |
| 440 | |
| 441 | return 0; |
| 442 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 443 | err_out: |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 444 | return rc; |
| 445 | } |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 446 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 447 | |
| 448 | #define MAX_DATA_BYTE_COUNT (4*1024*1024) |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 449 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 450 | static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) |
| 451 | { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 452 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
| 453 | struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; |
| 454 | u32 sg_count; |
| 455 | int i; |
| 456 | |
| 457 | sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 458 | if (sg_count > AHCI_MAX_SG) { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 459 | printf("Error:Too much sg!\n"); |
| 460 | return -1; |
| 461 | } |
| 462 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 463 | for (i = 0; i < sg_count; i++) { |
| 464 | ahci_sg->addr = |
| 465 | cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 466 | ahci_sg->addr_hi = 0; |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 467 | ahci_sg->flags_size = cpu_to_le32(0x3fffff & |
| 468 | (buf_len < MAX_DATA_BYTE_COUNT |
| 469 | ? (buf_len - 1) |
| 470 | : (MAX_DATA_BYTE_COUNT - 1))); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 471 | ahci_sg++; |
| 472 | buf_len -= MAX_DATA_BYTE_COUNT; |
| 473 | } |
| 474 | |
| 475 | return sg_count; |
| 476 | } |
| 477 | |
| 478 | |
| 479 | static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) |
| 480 | { |
| 481 | pp->cmd_slot->opts = cpu_to_le32(opts); |
| 482 | pp->cmd_slot->status = 0; |
| 483 | pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); |
| 484 | pp->cmd_slot->tbl_addr_hi = 0; |
| 485 | } |
| 486 | |
| 487 | |
Gabe Black | e81058c | 2012-10-29 05:23:52 +0000 | [diff] [blame] | 488 | #ifdef CONFIG_AHCI_SETFEATURES_XFER |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 489 | static void ahci_set_feature(u8 port) |
| 490 | { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 491 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 492 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
| 493 | u32 cmd_fis_len = 5; /* five dwords */ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 494 | u8 fis[20]; |
| 495 | |
Stefan Reinauer | 4e422bc | 2012-10-29 05:23:51 +0000 | [diff] [blame] | 496 | /* set feature */ |
Taylor Hutt | c873111 | 2012-10-29 05:23:55 +0000 | [diff] [blame] | 497 | memset(fis, 0, sizeof(fis)); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 498 | fis[0] = 0x27; |
| 499 | fis[1] = 1 << 7; |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 500 | fis[2] = ATA_CMD_SET_FEATURES; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 501 | fis[3] = SETFEATURES_XFER; |
| 502 | fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; |
| 503 | |
Taylor Hutt | c873111 | 2012-10-29 05:23:55 +0000 | [diff] [blame] | 504 | memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis)); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 505 | ahci_fill_cmd_slot(pp, cmd_fis_len); |
Taylor Hutt | 90b276f | 2012-10-29 05:23:59 +0000 | [diff] [blame] | 506 | ahci_dcache_flush_sata_cmd(pp); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 507 | writel(1, port_mmio + PORT_CMD_ISSUE); |
| 508 | readl(port_mmio + PORT_CMD_ISSUE); |
| 509 | |
Walter Murphy | 5784766 | 2012-10-29 05:24:00 +0000 | [diff] [blame] | 510 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, |
| 511 | WAIT_MS_DATAIO, 0x1)) { |
Stefan Reinauer | 4e422bc | 2012-10-29 05:23:51 +0000 | [diff] [blame] | 512 | printf("set feature error on port %d!\n", port); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 513 | } |
| 514 | } |
Gabe Black | e81058c | 2012-10-29 05:23:52 +0000 | [diff] [blame] | 515 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 516 | |
Bin Meng | 4df2b48 | 2014-12-31 17:18:39 +0800 | [diff] [blame] | 517 | static int wait_spinup(volatile u8 *port_mmio) |
| 518 | { |
| 519 | ulong start; |
| 520 | u32 tf_data; |
| 521 | |
| 522 | start = get_timer(0); |
| 523 | do { |
| 524 | tf_data = readl(port_mmio + PORT_TFDATA); |
| 525 | if (!(tf_data & ATA_BUSY)) |
| 526 | return 0; |
| 527 | } while (get_timer(start) < WAIT_MS_SPINUP); |
| 528 | |
| 529 | return -ETIMEDOUT; |
| 530 | } |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 531 | |
| 532 | static int ahci_port_start(u8 port) |
| 533 | { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 534 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 535 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 536 | u32 port_status; |
| 537 | u32 mem; |
| 538 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 539 | debug("Enter start port: %d\n", port); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 540 | port_status = readl(port_mmio + PORT_SCR_STAT); |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 541 | debug("Port %d status: %x\n", port, port_status); |
| 542 | if ((port_status & 0xf) != 0x03) { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 543 | printf("No Link on this port!\n"); |
| 544 | return -1; |
| 545 | } |
| 546 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 547 | mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 548 | if (!mem) { |
| 549 | free(pp); |
Roger Quadros | d73763a | 2013-11-11 16:56:37 +0200 | [diff] [blame] | 550 | printf("%s: No mem for table!\n", __func__); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 551 | return -ENOMEM; |
| 552 | } |
| 553 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 554 | mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ |
| 555 | memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 556 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 557 | /* |
| 558 | * First item in chunk of DMA memory: 32-slot command table, |
| 559 | * 32 bytes each in size |
| 560 | */ |
Taylor Hutt | 64738e8 | 2012-10-29 05:23:58 +0000 | [diff] [blame] | 561 | pp->cmd_slot = |
| 562 | (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem); |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 563 | debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 564 | mem += (AHCI_CMD_SLOT_SZ + 224); |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 565 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 566 | /* |
| 567 | * Second item: Received-FIS area |
| 568 | */ |
Taylor Hutt | 64738e8 | 2012-10-29 05:23:58 +0000 | [diff] [blame] | 569 | pp->rx_fis = virt_to_phys((void *)mem); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 570 | mem += AHCI_RX_FIS_SZ; |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 571 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 572 | /* |
| 573 | * Third item: data area for storing a single command |
| 574 | * and its scatter-gather table |
| 575 | */ |
Taylor Hutt | 64738e8 | 2012-10-29 05:23:58 +0000 | [diff] [blame] | 576 | pp->cmd_tbl = virt_to_phys((void *)mem); |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 577 | debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 578 | |
| 579 | mem += AHCI_CMD_TBL_HDR; |
Taylor Hutt | 64738e8 | 2012-10-29 05:23:58 +0000 | [diff] [blame] | 580 | pp->cmd_tbl_sg = |
| 581 | (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 582 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 583 | writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 584 | |
| 585 | writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); |
| 586 | |
Ian Campbell | a6e50a8 | 2014-07-18 20:38:41 +0100 | [diff] [blame] | 587 | #ifdef CONFIG_SUNXI_AHCI |
| 588 | sunxi_dma_init(port_mmio); |
| 589 | #endif |
| 590 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 591 | writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 592 | PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | |
| 593 | PORT_CMD_START, port_mmio + PORT_CMD); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 594 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 595 | debug("Exit start port %d\n", port); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 596 | |
Bin Meng | 4df2b48 | 2014-12-31 17:18:39 +0800 | [diff] [blame] | 597 | /* |
| 598 | * Make sure interface is not busy based on error and status |
| 599 | * information from task file data register before proceeding |
| 600 | */ |
| 601 | return wait_spinup(port_mmio); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 602 | } |
| 603 | |
| 604 | |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 605 | static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, |
| 606 | int buf_len, u8 is_write) |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 607 | { |
| 608 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 609 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
| 610 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 611 | u32 opts; |
| 612 | u32 port_status; |
| 613 | int sg_count; |
| 614 | |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 615 | debug("Enter %s: for port %d\n", __func__, port); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 616 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 617 | if (port > probe_ent->n_ports) { |
Taylor Hutt | 5a2b77f | 2012-10-29 05:23:56 +0000 | [diff] [blame] | 618 | printf("Invalid port number %d\n", port); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 619 | return -1; |
| 620 | } |
| 621 | |
| 622 | port_status = readl(port_mmio + PORT_SCR_STAT); |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 623 | if ((port_status & 0xf) != 0x03) { |
| 624 | debug("No Link on port %d!\n", port); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 625 | return -1; |
| 626 | } |
| 627 | |
| 628 | memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); |
| 629 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 630 | sg_count = ahci_fill_sg(port, buf, buf_len); |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 631 | opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 632 | ahci_fill_cmd_slot(pp, opts); |
| 633 | |
Taylor Hutt | 90b276f | 2012-10-29 05:23:59 +0000 | [diff] [blame] | 634 | ahci_dcache_flush_sata_cmd(pp); |
| 635 | ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len); |
| 636 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 637 | writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); |
| 638 | |
Walter Murphy | 5784766 | 2012-10-29 05:24:00 +0000 | [diff] [blame] | 639 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, |
| 640 | WAIT_MS_DATAIO, 0x1)) { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 641 | printf("timeout exit!\n"); |
| 642 | return -1; |
| 643 | } |
Taylor Hutt | 90b276f | 2012-10-29 05:23:59 +0000 | [diff] [blame] | 644 | |
| 645 | ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len); |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 646 | debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 647 | |
| 648 | return 0; |
| 649 | } |
| 650 | |
| 651 | |
| 652 | static char *ata_id_strcpy(u16 *target, u16 *src, int len) |
| 653 | { |
| 654 | int i; |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 655 | for (i = 0; i < len / 2; i++) |
Rob Herring | e5a6c79 | 2011-06-01 09:10:26 +0000 | [diff] [blame] | 656 | target[i] = swab16(src[i]); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 657 | return (char *)target; |
| 658 | } |
| 659 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 660 | /* |
| 661 | * SCSI INQUIRY command operation. |
| 662 | */ |
| 663 | static int ata_scsiop_inquiry(ccb *pccb) |
| 664 | { |
Rob Herring | 48c3a87 | 2013-08-24 10:10:48 -0500 | [diff] [blame] | 665 | static const u8 hdr[] = { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 666 | 0, |
| 667 | 0, |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 668 | 0x5, /* claim SPC-3 version compatibility */ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 669 | 2, |
| 670 | 95 - 4, |
| 671 | }; |
| 672 | u8 fis[20]; |
Roger Quadros | 3f62971 | 2014-04-01 17:26:40 +0300 | [diff] [blame] | 673 | u16 *idbuf; |
Roger Quadros | 2faf5fb | 2013-11-11 16:56:38 +0200 | [diff] [blame] | 674 | ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 675 | u8 port; |
| 676 | |
| 677 | /* Clean ccb data buffer */ |
| 678 | memset(pccb->pdata, 0, pccb->datalen); |
| 679 | |
| 680 | memcpy(pccb->pdata, hdr, sizeof(hdr)); |
| 681 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 682 | if (pccb->datalen <= 35) |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 683 | return 0; |
| 684 | |
Taylor Hutt | c873111 | 2012-10-29 05:23:55 +0000 | [diff] [blame] | 685 | memset(fis, 0, sizeof(fis)); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 686 | /* Construct the FIS */ |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 687 | fis[0] = 0x27; /* Host to device FIS. */ |
| 688 | fis[1] = 1 << 7; /* Command FIS. */ |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 689 | fis[2] = ATA_CMD_ID_ATA; /* Command byte. */ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 690 | |
| 691 | /* Read id from sata */ |
| 692 | port = pccb->target; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 693 | |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 694 | if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid, |
| 695 | ATA_ID_WORDS * 2, 0)) { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 696 | debug("scsi_ahci: SCSI inquiry command failure.\n"); |
| 697 | return -EIO; |
| 698 | } |
| 699 | |
Roger Quadros | 3f62971 | 2014-04-01 17:26:40 +0300 | [diff] [blame] | 700 | if (!ataid[port]) { |
| 701 | ataid[port] = malloc(ATA_ID_WORDS * 2); |
| 702 | if (!ataid[port]) { |
| 703 | printf("%s: No memory for ataid[port]\n", __func__); |
| 704 | return -ENOMEM; |
| 705 | } |
| 706 | } |
| 707 | |
| 708 | idbuf = ataid[port]; |
| 709 | |
| 710 | memcpy(idbuf, tmpid, ATA_ID_WORDS * 2); |
| 711 | ata_swap_buf_le16(idbuf, ATA_ID_WORDS); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 712 | |
| 713 | memcpy(&pccb->pdata[8], "ATA ", 8); |
Roger Quadros | 3f62971 | 2014-04-01 17:26:40 +0300 | [diff] [blame] | 714 | ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16); |
| 715 | ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 716 | |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 717 | #ifdef DEBUG |
Roger Quadros | 3f62971 | 2014-04-01 17:26:40 +0300 | [diff] [blame] | 718 | ata_dump_id(idbuf); |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 719 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 720 | return 0; |
| 721 | } |
| 722 | |
| 723 | |
| 724 | /* |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 725 | * SCSI READ10/WRITE10 command operation. |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 726 | */ |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 727 | static int ata_scsiop_read_write(ccb *pccb, u8 is_write) |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 728 | { |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 729 | u32 lba = 0; |
| 730 | u16 blocks = 0; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 731 | u8 fis[20]; |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 732 | u8 *user_buffer = pccb->pdata; |
| 733 | u32 user_buffer_size = pccb->datalen; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 734 | |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 735 | /* Retrieve the base LBA number from the ccb structure. */ |
| 736 | memcpy(&lba, pccb->cmd + 2, sizeof(lba)); |
| 737 | lba = be32_to_cpu(lba); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 738 | |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 739 | /* |
| 740 | * And the number of blocks. |
| 741 | * |
| 742 | * For 10-byte and 16-byte SCSI R/W commands, transfer |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 743 | * length 0 means transfer 0 block of data. |
| 744 | * However, for ATA R/W commands, sector count 0 means |
| 745 | * 256 or 65536 sectors, not 0 sectors as in SCSI. |
| 746 | * |
| 747 | * WARNING: one or two older ATA drives treat 0 as 0... |
| 748 | */ |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 749 | blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]); |
| 750 | |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 751 | debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n", |
| 752 | is_write ? "write" : "read", (unsigned)lba, blocks); |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 753 | |
| 754 | /* Preset the FIS */ |
Taylor Hutt | c873111 | 2012-10-29 05:23:55 +0000 | [diff] [blame] | 755 | memset(fis, 0, sizeof(fis)); |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 756 | fis[0] = 0x27; /* Host to device FIS. */ |
| 757 | fis[1] = 1 << 7; /* Command FIS. */ |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 758 | /* Command byte (read/write). */ |
Walter Murphy | fe1f808 | 2012-10-29 05:24:03 +0000 | [diff] [blame] | 759 | fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 760 | |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 761 | while (blocks) { |
| 762 | u16 now_blocks; /* number of blocks per iteration */ |
| 763 | u32 transfer_size; /* number of bytes per iteration */ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 764 | |
Masahiro Yamada | b414119 | 2014-11-07 03:03:31 +0900 | [diff] [blame] | 765 | now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 766 | |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 767 | transfer_size = ATA_SECT_SIZE * now_blocks; |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 768 | if (transfer_size > user_buffer_size) { |
| 769 | printf("scsi_ahci: Error: buffer too small.\n"); |
| 770 | return -EIO; |
| 771 | } |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 772 | |
Walter Murphy | fe1f808 | 2012-10-29 05:24:03 +0000 | [diff] [blame] | 773 | /* LBA48 SATA command but only use 32bit address range within |
| 774 | * that. The next smaller command range (28bit) is too small. |
| 775 | */ |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 776 | fis[4] = (lba >> 0) & 0xff; |
| 777 | fis[5] = (lba >> 8) & 0xff; |
| 778 | fis[6] = (lba >> 16) & 0xff; |
Walter Murphy | fe1f808 | 2012-10-29 05:24:03 +0000 | [diff] [blame] | 779 | fis[7] = 1 << 6; /* device reg: set LBA mode */ |
| 780 | fis[8] = ((lba >> 24) & 0xff); |
| 781 | fis[3] = 0xe0; /* features */ |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 782 | |
| 783 | /* Block (sector) count */ |
| 784 | fis[12] = (now_blocks >> 0) & 0xff; |
| 785 | fis[13] = (now_blocks >> 8) & 0xff; |
| 786 | |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 787 | /* Read/Write from ahci */ |
| 788 | if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis), |
Tang Yuantian | 8f6e183 | 2015-03-31 15:02:43 +0800 | [diff] [blame] | 789 | user_buffer, transfer_size, |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 790 | is_write)) { |
| 791 | debug("scsi_ahci: SCSI %s10 command failure.\n", |
| 792 | is_write ? "WRITE" : "READ"); |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 793 | return -EIO; |
| 794 | } |
Marc Jones | 766b16f | 2012-10-29 05:24:02 +0000 | [diff] [blame] | 795 | |
| 796 | /* If this transaction is a write, do a following flush. |
| 797 | * Writes in u-boot are so rare, and the logic to know when is |
| 798 | * the last write and do a flush only there is sufficiently |
| 799 | * difficult. Just do a flush after every write. This incurs, |
| 800 | * usually, one extra flush when the rare writes do happen. |
| 801 | */ |
| 802 | if (is_write) { |
| 803 | if (-EIO == ata_io_flush(pccb->target)) |
| 804 | return -EIO; |
| 805 | } |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 806 | user_buffer += transfer_size; |
| 807 | user_buffer_size -= transfer_size; |
| 808 | blocks -= now_blocks; |
| 809 | lba += now_blocks; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 810 | } |
| 811 | |
| 812 | return 0; |
| 813 | } |
| 814 | |
| 815 | |
| 816 | /* |
| 817 | * SCSI READ CAPACITY10 command operation. |
| 818 | */ |
| 819 | static int ata_scsiop_read_capacity10(ccb *pccb) |
| 820 | { |
Kumar Gala | cb6d0b7 | 2009-07-13 09:24:00 -0500 | [diff] [blame] | 821 | u32 cap; |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 822 | u64 cap64; |
Gabe Black | 19d1d41 | 2012-10-29 05:23:54 +0000 | [diff] [blame] | 823 | u32 block_size; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 824 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 825 | if (!ataid[pccb->target]) { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 826 | printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 827 | "\tNo ATA info!\n" |
| 828 | "\tPlease run SCSI commmand INQUIRY firstly!\n"); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 829 | return -EPERM; |
| 830 | } |
| 831 | |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 832 | cap64 = ata_id_n_sectors(ataid[pccb->target]); |
| 833 | if (cap64 > 0x100000000ULL) |
| 834 | cap64 = 0xffffffff; |
Gabe Black | 19d1d41 | 2012-10-29 05:23:54 +0000 | [diff] [blame] | 835 | |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 836 | cap = cpu_to_be32(cap64); |
Kumar Gala | cb6d0b7 | 2009-07-13 09:24:00 -0500 | [diff] [blame] | 837 | memcpy(pccb->pdata, &cap, sizeof(cap)); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 838 | |
Gabe Black | 19d1d41 | 2012-10-29 05:23:54 +0000 | [diff] [blame] | 839 | block_size = cpu_to_be32((u32)512); |
| 840 | memcpy(&pccb->pdata[4], &block_size, 4); |
| 841 | |
| 842 | return 0; |
| 843 | } |
| 844 | |
| 845 | |
| 846 | /* |
| 847 | * SCSI READ CAPACITY16 command operation. |
| 848 | */ |
| 849 | static int ata_scsiop_read_capacity16(ccb *pccb) |
| 850 | { |
| 851 | u64 cap; |
| 852 | u64 block_size; |
| 853 | |
| 854 | if (!ataid[pccb->target]) { |
| 855 | printf("scsi_ahci: SCSI READ CAPACITY16 command failure. " |
| 856 | "\tNo ATA info!\n" |
| 857 | "\tPlease run SCSI commmand INQUIRY firstly!\n"); |
| 858 | return -EPERM; |
| 859 | } |
| 860 | |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 861 | cap = ata_id_n_sectors(ataid[pccb->target]); |
Gabe Black | 19d1d41 | 2012-10-29 05:23:54 +0000 | [diff] [blame] | 862 | cap = cpu_to_be64(cap); |
| 863 | memcpy(pccb->pdata, &cap, sizeof(cap)); |
| 864 | |
| 865 | block_size = cpu_to_be64((u64)512); |
| 866 | memcpy(&pccb->pdata[8], &block_size, 8); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 867 | |
| 868 | return 0; |
| 869 | } |
| 870 | |
| 871 | |
| 872 | /* |
| 873 | * SCSI TEST UNIT READY command operation. |
| 874 | */ |
| 875 | static int ata_scsiop_test_unit_ready(ccb *pccb) |
| 876 | { |
| 877 | return (ataid[pccb->target]) ? 0 : -EPERM; |
| 878 | } |
| 879 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 880 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 881 | int scsi_exec(ccb *pccb) |
| 882 | { |
| 883 | int ret; |
| 884 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 885 | switch (pccb->cmd[0]) { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 886 | case SCSI_READ10: |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 887 | ret = ata_scsiop_read_write(pccb, 0); |
| 888 | break; |
| 889 | case SCSI_WRITE10: |
| 890 | ret = ata_scsiop_read_write(pccb, 1); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 891 | break; |
Gabe Black | 19d1d41 | 2012-10-29 05:23:54 +0000 | [diff] [blame] | 892 | case SCSI_RD_CAPAC10: |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 893 | ret = ata_scsiop_read_capacity10(pccb); |
| 894 | break; |
Gabe Black | 19d1d41 | 2012-10-29 05:23:54 +0000 | [diff] [blame] | 895 | case SCSI_RD_CAPAC16: |
| 896 | ret = ata_scsiop_read_capacity16(pccb); |
| 897 | break; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 898 | case SCSI_TST_U_RDY: |
| 899 | ret = ata_scsiop_test_unit_ready(pccb); |
| 900 | break; |
| 901 | case SCSI_INQUIRY: |
| 902 | ret = ata_scsiop_inquiry(pccb); |
| 903 | break; |
| 904 | default: |
| 905 | printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); |
York Sun | 472d546 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 906 | return false; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 907 | } |
| 908 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 909 | if (ret) { |
| 910 | debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); |
York Sun | 472d546 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 911 | return false; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 912 | } |
York Sun | 472d546 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 913 | return true; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 914 | |
| 915 | } |
| 916 | |
| 917 | |
| 918 | void scsi_low_level_init(int busdevfunc) |
| 919 | { |
| 920 | int i; |
| 921 | u32 linkmap; |
| 922 | |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 923 | #ifndef CONFIG_SCSI_AHCI_PLAT |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 924 | ahci_init_one(busdevfunc); |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 925 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 926 | |
| 927 | linkmap = probe_ent->link_port_map; |
| 928 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 929 | for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 930 | if (((linkmap >> i) & 0x01)) { |
| 931 | if (ahci_port_start((u8) i)) { |
| 932 | printf("Can not start port %d\n", i); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 933 | continue; |
| 934 | } |
Gabe Black | e81058c | 2012-10-29 05:23:52 +0000 | [diff] [blame] | 935 | #ifdef CONFIG_AHCI_SETFEATURES_XFER |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 936 | ahci_set_feature((u8) i); |
Gabe Black | e81058c | 2012-10-29 05:23:52 +0000 | [diff] [blame] | 937 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 938 | } |
| 939 | } |
| 940 | } |
| 941 | |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 942 | #ifdef CONFIG_SCSI_AHCI_PLAT |
Scott Wood | 9efaca3 | 2015-04-17 09:19:01 -0500 | [diff] [blame] | 943 | int ahci_init(void __iomem *base) |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 944 | { |
| 945 | int i, rc = 0; |
| 946 | u32 linkmap; |
| 947 | |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 948 | probe_ent = malloc(sizeof(struct ahci_probe_ent)); |
Roger Quadros | d73763a | 2013-11-11 16:56:37 +0200 | [diff] [blame] | 949 | if (!probe_ent) { |
| 950 | printf("%s: No memory for probe_ent\n", __func__); |
| 951 | return -ENOMEM; |
| 952 | } |
| 953 | |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 954 | memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); |
| 955 | |
| 956 | probe_ent->host_flags = ATA_FLAG_SATA |
| 957 | | ATA_FLAG_NO_LEGACY |
| 958 | | ATA_FLAG_MMIO |
| 959 | | ATA_FLAG_PIO_DMA |
| 960 | | ATA_FLAG_NO_ATAPI; |
| 961 | probe_ent->pio_mask = 0x1f; |
| 962 | probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ |
| 963 | |
| 964 | probe_ent->mmio_base = base; |
| 965 | |
| 966 | /* initialize adapter */ |
| 967 | rc = ahci_host_init(probe_ent); |
| 968 | if (rc) |
| 969 | goto err_out; |
| 970 | |
| 971 | ahci_print_info(probe_ent); |
| 972 | |
| 973 | linkmap = probe_ent->link_port_map; |
| 974 | |
| 975 | for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { |
| 976 | if (((linkmap >> i) & 0x01)) { |
| 977 | if (ahci_port_start((u8) i)) { |
| 978 | printf("Can not start port %d\n", i); |
| 979 | continue; |
| 980 | } |
Gabe Black | e81058c | 2012-10-29 05:23:52 +0000 | [diff] [blame] | 981 | #ifdef CONFIG_AHCI_SETFEATURES_XFER |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 982 | ahci_set_feature((u8) i); |
Gabe Black | e81058c | 2012-10-29 05:23:52 +0000 | [diff] [blame] | 983 | #endif |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 984 | } |
| 985 | } |
| 986 | err_out: |
| 987 | return rc; |
| 988 | } |
Ian Campbell | c6f3d50 | 2014-03-07 01:20:56 +0000 | [diff] [blame] | 989 | |
| 990 | void __weak scsi_init(void) |
| 991 | { |
| 992 | } |
| 993 | |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 994 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 995 | |
Marc Jones | 766b16f | 2012-10-29 05:24:02 +0000 | [diff] [blame] | 996 | /* |
| 997 | * In the general case of generic rotating media it makes sense to have a |
| 998 | * flush capability. It probably even makes sense in the case of SSDs because |
| 999 | * one cannot always know for sure what kind of internal cache/flush mechanism |
| 1000 | * is embodied therein. At first it was planned to invoke this after the last |
| 1001 | * write to disk and before rebooting. In practice, knowing, a priori, which |
| 1002 | * is the last write is difficult. Because writing to the disk in u-boot is |
| 1003 | * very rare, this flush command will be invoked after every block write. |
| 1004 | */ |
| 1005 | static int ata_io_flush(u8 port) |
| 1006 | { |
| 1007 | u8 fis[20]; |
| 1008 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
| 1009 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
| 1010 | u32 cmd_fis_len = 5; /* five dwords */ |
| 1011 | |
| 1012 | /* Preset the FIS */ |
| 1013 | memset(fis, 0, 20); |
| 1014 | fis[0] = 0x27; /* Host to device FIS. */ |
| 1015 | fis[1] = 1 << 7; /* Command FIS. */ |
Walter Murphy | fe1f808 | 2012-10-29 05:24:03 +0000 | [diff] [blame] | 1016 | fis[2] = ATA_CMD_FLUSH_EXT; |
Marc Jones | 766b16f | 2012-10-29 05:24:02 +0000 | [diff] [blame] | 1017 | |
| 1018 | memcpy((unsigned char *)pp->cmd_tbl, fis, 20); |
| 1019 | ahci_fill_cmd_slot(pp, cmd_fis_len); |
| 1020 | writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); |
| 1021 | |
| 1022 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, |
| 1023 | WAIT_MS_FLUSH, 0x1)) { |
| 1024 | debug("scsi_ahci: flush command timeout on port %d.\n", port); |
| 1025 | return -EIO; |
| 1026 | } |
| 1027 | |
| 1028 | return 0; |
| 1029 | } |
| 1030 | |
| 1031 | |
Dmitry Lifshitz | 1a33b73 | 2014-12-15 16:02:56 +0200 | [diff] [blame] | 1032 | __weak void scsi_bus_reset(void) |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 1033 | { |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 1034 | /*Not implement*/ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 1035 | } |
| 1036 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 1037 | void scsi_print_error(ccb * pccb) |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 1038 | { |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 1039 | /*The ahci error info can be read in the ahci driver*/ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 1040 | } |