blob: c8f65739e9778a1578dc7aa17eb3448e9c749a46 [file] [log] [blame]
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08001/*
Kumar Gala4c2e3da2009-07-28 21:49:52 -05002 * Copyright (C) Freescale Semiconductor, Inc. 2006.
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08003 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08007 *
8 * with the reference on libata and ahci drvier in kernel
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08009 */
10#include <common.h>
11
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080012#include <command.h>
13#include <pci.h>
14#include <asm/processor.h>
15#include <asm/errno.h>
16#include <asm/io.h>
17#include <malloc.h>
18#include <scsi.h>
Rob Herring344ca0b2013-08-24 10:10:54 -050019#include <libata.h>
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080020#include <linux/ctype.h>
21#include <ahci.h>
22
Marc Jones766b16f2012-10-29 05:24:02 +000023static int ata_io_flush(u8 port);
24
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080025struct ahci_probe_ent *probe_ent = NULL;
Rob Herring344ca0b2013-08-24 10:10:54 -050026u16 *ataid[AHCI_MAX_PORTS];
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080027
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -050028#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
29
Vadim Bendebury284231e2012-10-29 05:23:44 +000030/*
Hung-Te Linb7a21b72012-10-29 05:23:53 +000031 * Some controllers limit number of blocks they can read/write at once.
32 * Contemporary SSD devices work much faster if the read/write size is aligned
33 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
34 * needed.
Vadim Bendebury284231e2012-10-29 05:23:44 +000035 */
Hung-Te Linb7a21b72012-10-29 05:23:53 +000036#ifndef MAX_SATA_BLOCKS_READ_WRITE
37#define MAX_SATA_BLOCKS_READ_WRITE 0x80
Vadim Bendebury284231e2012-10-29 05:23:44 +000038#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080039
Walter Murphy57847662012-10-29 05:24:00 +000040/* Maximum timeouts for each event */
Rob Herring7610b412013-08-24 10:10:53 -050041#define WAIT_MS_SPINUP 20000
Walter Murphy57847662012-10-29 05:24:00 +000042#define WAIT_MS_DATAIO 5000
Marc Jones766b16f2012-10-29 05:24:02 +000043#define WAIT_MS_FLUSH 5000
Ian Campbell73545f72014-03-07 01:20:58 +000044#define WAIT_MS_LINKUP 40
Walter Murphy57847662012-10-29 05:24:00 +000045
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080046static inline u32 ahci_port_base(u32 base, u32 port)
47{
48 return base + 0x100 + (port * 0x80);
49}
50
51
52static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
53 unsigned int port_idx)
54{
55 base = ahci_port_base(base, port_idx);
56
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -050057 port->cmd_addr = base;
58 port->scr_addr = base + PORT_SCR;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080059}
60
61
62#define msleep(a) udelay(a * 1000)
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -050063
Taylor Hutt90b276f2012-10-29 05:23:59 +000064static void ahci_dcache_flush_range(unsigned begin, unsigned len)
65{
66 const unsigned long start = begin;
67 const unsigned long end = start + len;
68
69 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
70 flush_dcache_range(start, end);
71}
72
73/*
74 * SATA controller DMAs to physical RAM. Ensure data from the
75 * controller is invalidated from dcache; next access comes from
76 * physical RAM.
77 */
78static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)
79{
80 const unsigned long start = begin;
81 const unsigned long end = start + len;
82
83 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
84 invalidate_dcache_range(start, end);
85}
86
87/*
88 * Ensure data for SATA controller is flushed out of dcache and
89 * written to physical memory.
90 */
91static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
92{
93 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
94 AHCI_PORT_PRIV_DMA_SZ);
95}
96
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -050097static int waiting_for_cmd_completed(volatile u8 *offset,
98 int timeout_msec,
99 u32 sign)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800100{
101 int i;
102 u32 status;
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500103
104 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800105 msleep(1);
106
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500107 return (i < timeout_msec) ? 0 : -1;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800108}
109
Rob Herring124e9fa2013-08-24 10:10:51 -0500110int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port)
111{
112 u32 tmp;
113 int j = 0;
114 u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
115
Wolfgang Denk3765b3e2013-10-07 13:07:26 +0200116 /*
Rob Herring124e9fa2013-08-24 10:10:51 -0500117 * Bring up SATA link.
118 * SATA link bringup time is usually less than 1 ms; only very
119 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
120 */
121 while (j < WAIT_MS_LINKUP) {
122 tmp = readl(port_mmio + PORT_SCR_STAT);
123 tmp &= PORT_SCR_STAT_DET_MASK;
124 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
125 return 0;
126 udelay(1000);
127 j++;
128 }
129 return 1;
130}
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800131
132static int ahci_host_init(struct ahci_probe_ent *probe_ent)
133{
Rob Herring942e3142011-07-06 16:13:36 +0000134#ifndef CONFIG_SCSI_AHCI_PLAT
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800135 pci_dev_t pdev = probe_ent->dev;
Rob Herring942e3142011-07-06 16:13:36 +0000136 u16 tmp16;
137 unsigned short vendor;
138#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800139 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
Marc Jones2a0c61d2012-10-29 05:24:01 +0000140 u32 tmp, cap_save, cmd;
Rob Herring124e9fa2013-08-24 10:10:51 -0500141 int i, j, ret;
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500142 volatile u8 *port_mmio;
Richard Gibbs2915a022013-08-24 10:10:47 -0500143 u32 port_map;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800144
Vadim Bendebury284231e2012-10-29 05:23:44 +0000145 debug("ahci_host_init: start\n");
146
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800147 cap_save = readl(mmio + HOST_CAP);
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500148 cap_save &= ((1 << 28) | (1 << 17));
Marc Jones2a0c61d2012-10-29 05:24:01 +0000149 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800150
151 /* global controller reset */
152 tmp = readl(mmio + HOST_CTL);
153 if ((tmp & HOST_RESET) == 0)
154 writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
155
156 /* reset must complete within 1 second, or
157 * the hardware should be considered fried.
158 */
Stefan Reinauer9a65b872012-10-29 05:23:49 +0000159 i = 1000;
160 do {
161 udelay(1000);
162 tmp = readl(mmio + HOST_CTL);
163 if (!i--) {
164 debug("controller reset failed (0x%x)\n", tmp);
165 return -1;
166 }
167 } while (tmp & HOST_RESET);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800168
169 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
170 writel(cap_save, mmio + HOST_CAP);
171 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
172
Rob Herring942e3142011-07-06 16:13:36 +0000173#ifndef CONFIG_SCSI_AHCI_PLAT
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800174 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
175
176 if (vendor == PCI_VENDOR_ID_INTEL) {
177 u16 tmp16;
178 pci_read_config_word(pdev, 0x92, &tmp16);
179 tmp16 |= 0xf;
180 pci_write_config_word(pdev, 0x92, tmp16);
181 }
Rob Herring942e3142011-07-06 16:13:36 +0000182#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800183 probe_ent->cap = readl(mmio + HOST_CAP);
184 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
Richard Gibbs2915a022013-08-24 10:10:47 -0500185 port_map = probe_ent->port_map;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800186 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
187
188 debug("cap 0x%x port_map 0x%x n_ports %d\n",
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500189 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800190
Vadim Bendebury284231e2012-10-29 05:23:44 +0000191 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
192 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
193
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800194 for (i = 0; i < probe_ent->n_ports; i++) {
Richard Gibbs2915a022013-08-24 10:10:47 -0500195 if (!(port_map & (1 << i)))
196 continue;
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500197 probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
198 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
199 ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800200
201 /* make sure port is not active */
202 tmp = readl(port_mmio + PORT_CMD);
203 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
204 PORT_CMD_FIS_RX | PORT_CMD_START)) {
Stefan Reinauer7ba79172012-10-29 05:23:50 +0000205 debug("Port %d is active. Deactivating.\n", i);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800206 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
207 PORT_CMD_FIS_RX | PORT_CMD_START);
208 writel_with_flush(tmp, port_mmio + PORT_CMD);
209
210 /* spec says 500 msecs for each bit, so
211 * this is slightly incorrect.
212 */
213 msleep(500);
214 }
215
Marc Jones2a0c61d2012-10-29 05:24:01 +0000216 /* Add the spinup command to whatever mode bits may
217 * already be on in the command register.
218 */
219 cmd = readl(port_mmio + PORT_CMD);
220 cmd |= PORT_CMD_FIS_RX;
221 cmd |= PORT_CMD_SPIN_UP;
222 writel_with_flush(cmd, port_mmio + PORT_CMD);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800223
Rob Herring124e9fa2013-08-24 10:10:51 -0500224 /* Bring up SATA link. */
225 ret = ahci_link_up(probe_ent, i);
226 if (ret) {
Marc Jones2a0c61d2012-10-29 05:24:01 +0000227 printf("SATA link %d timeout.\n", i);
228 continue;
229 } else {
230 debug("SATA link ok.\n");
231 }
232
233 /* Clear error status */
234 tmp = readl(port_mmio + PORT_SCR_ERR);
235 if (tmp)
236 writel(tmp, port_mmio + PORT_SCR_ERR);
237
238 debug("Spinning up device on SATA port %d... ", i);
239
240 j = 0;
241 while (j < WAIT_MS_SPINUP) {
242 tmp = readl(port_mmio + PORT_TFDATA);
Rob Herring344ca0b2013-08-24 10:10:54 -0500243 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
Marc Jones2a0c61d2012-10-29 05:24:01 +0000244 break;
245 udelay(1000);
Rob Herring17821082013-08-24 10:10:52 -0500246 tmp = readl(port_mmio + PORT_SCR_STAT);
247 tmp &= PORT_SCR_STAT_DET_MASK;
248 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
249 break;
Marc Jones2a0c61d2012-10-29 05:24:01 +0000250 j++;
251 }
Rob Herring17821082013-08-24 10:10:52 -0500252
253 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
254 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
255 debug("SATA link %d down (COMINIT received), retrying...\n", i);
256 i--;
257 continue;
258 }
259
Marc Jones2a0c61d2012-10-29 05:24:01 +0000260 printf("Target spinup took %d ms.\n", j);
261 if (j == WAIT_MS_SPINUP)
Stefan Reinauer9a65b872012-10-29 05:23:49 +0000262 debug("timeout.\n");
263 else
264 debug("ok.\n");
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800265
266 tmp = readl(port_mmio + PORT_SCR_ERR);
267 debug("PORT_SCR_ERR 0x%x\n", tmp);
268 writel(tmp, port_mmio + PORT_SCR_ERR);
269
270 /* ack any pending irq events for this port */
271 tmp = readl(port_mmio + PORT_IRQ_STAT);
272 debug("PORT_IRQ_STAT 0x%x\n", tmp);
273 if (tmp)
274 writel(tmp, port_mmio + PORT_IRQ_STAT);
275
276 writel(1 << i, mmio + HOST_IRQ_STAT);
277
278 /* set irq mask (enables interrupts) */
279 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
280
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000281 /* register linkup ports */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800282 tmp = readl(port_mmio + PORT_SCR_STAT);
Marc Jones766b16f2012-10-29 05:24:02 +0000283 debug("SATA port %d status: 0x%x\n", i, tmp);
Rob Herring2bdb10d2013-08-24 10:10:50 -0500284 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500285 probe_ent->link_port_map |= (0x01 << i);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800286 }
287
288 tmp = readl(mmio + HOST_CTL);
289 debug("HOST_CTL 0x%x\n", tmp);
290 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
291 tmp = readl(mmio + HOST_CTL);
292 debug("HOST_CTL 0x%x\n", tmp);
Rob Herring942e3142011-07-06 16:13:36 +0000293#ifndef CONFIG_SCSI_AHCI_PLAT
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800294 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
295 tmp |= PCI_COMMAND_MASTER;
296 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
Rob Herring942e3142011-07-06 16:13:36 +0000297#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800298 return 0;
299}
300
301
302static void ahci_print_info(struct ahci_probe_ent *probe_ent)
303{
Rob Herring942e3142011-07-06 16:13:36 +0000304#ifndef CONFIG_SCSI_AHCI_PLAT
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800305 pci_dev_t pdev = probe_ent->dev;
Rob Herring942e3142011-07-06 16:13:36 +0000306 u16 cc;
307#endif
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500308 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000309 u32 vers, cap, cap2, impl, speed;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800310 const char *speed_s;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800311 const char *scc_s;
312
313 vers = readl(mmio + HOST_VERSION);
314 cap = probe_ent->cap;
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000315 cap2 = readl(mmio + HOST_CAP2);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800316 impl = probe_ent->port_map;
317
318 speed = (cap >> 20) & 0xf;
319 if (speed == 1)
320 speed_s = "1.5";
321 else if (speed == 2)
322 speed_s = "3";
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000323 else if (speed == 3)
324 speed_s = "6";
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800325 else
326 speed_s = "?";
327
Rob Herring942e3142011-07-06 16:13:36 +0000328#ifdef CONFIG_SCSI_AHCI_PLAT
329 scc_s = "SATA";
330#else
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800331 pci_read_config_word(pdev, 0x0a, &cc);
332 if (cc == 0x0101)
333 scc_s = "IDE";
334 else if (cc == 0x0106)
335 scc_s = "SATA";
336 else if (cc == 0x0104)
337 scc_s = "RAID";
338 else
339 scc_s = "unknown";
Rob Herring942e3142011-07-06 16:13:36 +0000340#endif
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500341 printf("AHCI %02x%02x.%02x%02x "
342 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
343 (vers >> 24) & 0xff,
344 (vers >> 16) & 0xff,
345 (vers >> 8) & 0xff,
346 vers & 0xff,
347 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800348
349 printf("flags: "
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000350 "%s%s%s%s%s%s%s"
351 "%s%s%s%s%s%s%s"
352 "%s%s%s%s%s%s\n",
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500353 cap & (1 << 31) ? "64bit " : "",
354 cap & (1 << 30) ? "ncq " : "",
355 cap & (1 << 28) ? "ilck " : "",
356 cap & (1 << 27) ? "stag " : "",
357 cap & (1 << 26) ? "pm " : "",
358 cap & (1 << 25) ? "led " : "",
359 cap & (1 << 24) ? "clo " : "",
360 cap & (1 << 19) ? "nz " : "",
361 cap & (1 << 18) ? "only " : "",
362 cap & (1 << 17) ? "pmp " : "",
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000363 cap & (1 << 16) ? "fbss " : "",
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500364 cap & (1 << 15) ? "pio " : "",
365 cap & (1 << 14) ? "slum " : "",
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000366 cap & (1 << 13) ? "part " : "",
367 cap & (1 << 7) ? "ccc " : "",
368 cap & (1 << 6) ? "ems " : "",
369 cap & (1 << 5) ? "sxs " : "",
370 cap2 & (1 << 2) ? "apst " : "",
371 cap2 & (1 << 1) ? "nvmp " : "",
372 cap2 & (1 << 0) ? "boh " : "");
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800373}
374
Rob Herring942e3142011-07-06 16:13:36 +0000375#ifndef CONFIG_SCSI_AHCI_PLAT
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500376static int ahci_init_one(pci_dev_t pdev)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800377{
Ed Swarthout63cec582007-08-02 14:09:49 -0500378 u16 vendor;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800379 int rc;
380
Ed Swarthout594e7982007-08-14 14:06:45 -0500381 probe_ent = malloc(sizeof(struct ahci_probe_ent));
Roger Quadrosd73763a2013-11-11 16:56:37 +0200382 if (!probe_ent) {
383 printf("%s: No memory for probe_ent\n", __func__);
384 return -ENOMEM;
385 }
386
Ed Swarthout594e7982007-08-14 14:06:45 -0500387 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800388 probe_ent->dev = pdev;
389
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500390 probe_ent->host_flags = ATA_FLAG_SATA
391 | ATA_FLAG_NO_LEGACY
392 | ATA_FLAG_MMIO
393 | ATA_FLAG_PIO_DMA
394 | ATA_FLAG_NO_ATAPI;
395 probe_ent->pio_mask = 0x1f;
396 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800397
Vadim Bendebury284231e2012-10-29 05:23:44 +0000398 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
399 debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800400
401 /* Take from kernel:
402 * JMicron-specific fixup:
403 * make sure we're in AHCI mode
404 */
405 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500406 if (vendor == 0x197b)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800407 pci_write_config_byte(pdev, 0x41, 0xa1);
408
409 /* initialize adapter */
410 rc = ahci_host_init(probe_ent);
411 if (rc)
412 goto err_out;
413
414 ahci_print_info(probe_ent);
415
416 return 0;
417
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500418 err_out:
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800419 return rc;
420}
Rob Herring942e3142011-07-06 16:13:36 +0000421#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800422
423#define MAX_DATA_BYTE_COUNT (4*1024*1024)
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500424
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800425static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
426{
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800427 struct ahci_ioports *pp = &(probe_ent->port[port]);
428 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
429 u32 sg_count;
430 int i;
431
432 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500433 if (sg_count > AHCI_MAX_SG) {
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800434 printf("Error:Too much sg!\n");
435 return -1;
436 }
437
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500438 for (i = 0; i < sg_count; i++) {
439 ahci_sg->addr =
440 cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800441 ahci_sg->addr_hi = 0;
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500442 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
443 (buf_len < MAX_DATA_BYTE_COUNT
444 ? (buf_len - 1)
445 : (MAX_DATA_BYTE_COUNT - 1)));
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800446 ahci_sg++;
447 buf_len -= MAX_DATA_BYTE_COUNT;
448 }
449
450 return sg_count;
451}
452
453
454static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
455{
456 pp->cmd_slot->opts = cpu_to_le32(opts);
457 pp->cmd_slot->status = 0;
458 pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
459 pp->cmd_slot->tbl_addr_hi = 0;
460}
461
462
Gabe Blacke81058c2012-10-29 05:23:52 +0000463#ifdef CONFIG_AHCI_SETFEATURES_XFER
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800464static void ahci_set_feature(u8 port)
465{
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800466 struct ahci_ioports *pp = &(probe_ent->port[port]);
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500467 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
468 u32 cmd_fis_len = 5; /* five dwords */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800469 u8 fis[20];
470
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000471 /* set feature */
Taylor Huttc8731112012-10-29 05:23:55 +0000472 memset(fis, 0, sizeof(fis));
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800473 fis[0] = 0x27;
474 fis[1] = 1 << 7;
Rob Herring344ca0b2013-08-24 10:10:54 -0500475 fis[2] = ATA_CMD_SET_FEATURES;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800476 fis[3] = SETFEATURES_XFER;
477 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
478
Taylor Huttc8731112012-10-29 05:23:55 +0000479 memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis));
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800480 ahci_fill_cmd_slot(pp, cmd_fis_len);
Taylor Hutt90b276f2012-10-29 05:23:59 +0000481 ahci_dcache_flush_sata_cmd(pp);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800482 writel(1, port_mmio + PORT_CMD_ISSUE);
483 readl(port_mmio + PORT_CMD_ISSUE);
484
Walter Murphy57847662012-10-29 05:24:00 +0000485 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
486 WAIT_MS_DATAIO, 0x1)) {
Stefan Reinauer4e422bc2012-10-29 05:23:51 +0000487 printf("set feature error on port %d!\n", port);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800488 }
489}
Gabe Blacke81058c2012-10-29 05:23:52 +0000490#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800491
492
493static int ahci_port_start(u8 port)
494{
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800495 struct ahci_ioports *pp = &(probe_ent->port[port]);
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500496 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800497 u32 port_status;
498 u32 mem;
499
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500500 debug("Enter start port: %d\n", port);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800501 port_status = readl(port_mmio + PORT_SCR_STAT);
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500502 debug("Port %d status: %x\n", port, port_status);
503 if ((port_status & 0xf) != 0x03) {
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800504 printf("No Link on this port!\n");
505 return -1;
506 }
507
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500508 mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800509 if (!mem) {
510 free(pp);
Roger Quadrosd73763a2013-11-11 16:56:37 +0200511 printf("%s: No mem for table!\n", __func__);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800512 return -ENOMEM;
513 }
514
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500515 mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
516 memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800517
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800518 /*
519 * First item in chunk of DMA memory: 32-slot command table,
520 * 32 bytes each in size
521 */
Taylor Hutt64738e82012-10-29 05:23:58 +0000522 pp->cmd_slot =
523 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
Vadim Bendebury284231e2012-10-29 05:23:44 +0000524 debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800525 mem += (AHCI_CMD_SLOT_SZ + 224);
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500526
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800527 /*
528 * Second item: Received-FIS area
529 */
Taylor Hutt64738e82012-10-29 05:23:58 +0000530 pp->rx_fis = virt_to_phys((void *)mem);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800531 mem += AHCI_RX_FIS_SZ;
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500532
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800533 /*
534 * Third item: data area for storing a single command
535 * and its scatter-gather table
536 */
Taylor Hutt64738e82012-10-29 05:23:58 +0000537 pp->cmd_tbl = virt_to_phys((void *)mem);
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500538 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800539
540 mem += AHCI_CMD_TBL_HDR;
Taylor Hutt64738e82012-10-29 05:23:58 +0000541 pp->cmd_tbl_sg =
542 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800543
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500544 writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800545
546 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
547
548 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500549 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
550 PORT_CMD_START, port_mmio + PORT_CMD);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800551
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500552 debug("Exit start port %d\n", port);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800553
554 return 0;
555}
556
557
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000558static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,
559 int buf_len, u8 is_write)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800560{
561
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500562 struct ahci_ioports *pp = &(probe_ent->port[port]);
563 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800564 u32 opts;
565 u32 port_status;
566 int sg_count;
567
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000568 debug("Enter %s: for port %d\n", __func__, port);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800569
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500570 if (port > probe_ent->n_ports) {
Taylor Hutt5a2b77f2012-10-29 05:23:56 +0000571 printf("Invalid port number %d\n", port);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800572 return -1;
573 }
574
575 port_status = readl(port_mmio + PORT_SCR_STAT);
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500576 if ((port_status & 0xf) != 0x03) {
577 debug("No Link on port %d!\n", port);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800578 return -1;
579 }
580
581 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
582
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500583 sg_count = ahci_fill_sg(port, buf, buf_len);
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000584 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800585 ahci_fill_cmd_slot(pp, opts);
586
Taylor Hutt90b276f2012-10-29 05:23:59 +0000587 ahci_dcache_flush_sata_cmd(pp);
588 ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len);
589
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800590 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
591
Walter Murphy57847662012-10-29 05:24:00 +0000592 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
593 WAIT_MS_DATAIO, 0x1)) {
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800594 printf("timeout exit!\n");
595 return -1;
596 }
Taylor Hutt90b276f2012-10-29 05:23:59 +0000597
598 ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len);
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000599 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800600
601 return 0;
602}
603
604
605static char *ata_id_strcpy(u16 *target, u16 *src, int len)
606{
607 int i;
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500608 for (i = 0; i < len / 2; i++)
Rob Herringe5a6c792011-06-01 09:10:26 +0000609 target[i] = swab16(src[i]);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800610 return (char *)target;
611}
612
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800613/*
614 * SCSI INQUIRY command operation.
615 */
616static int ata_scsiop_inquiry(ccb *pccb)
617{
Rob Herring48c3a872013-08-24 10:10:48 -0500618 static const u8 hdr[] = {
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800619 0,
620 0,
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500621 0x5, /* claim SPC-3 version compatibility */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800622 2,
623 95 - 4,
624 };
625 u8 fis[20];
Roger Quadros3f629712014-04-01 17:26:40 +0300626 u16 *idbuf;
Roger Quadros2faf5fb2013-11-11 16:56:38 +0200627 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800628 u8 port;
629
630 /* Clean ccb data buffer */
631 memset(pccb->pdata, 0, pccb->datalen);
632
633 memcpy(pccb->pdata, hdr, sizeof(hdr));
634
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500635 if (pccb->datalen <= 35)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800636 return 0;
637
Taylor Huttc8731112012-10-29 05:23:55 +0000638 memset(fis, 0, sizeof(fis));
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800639 /* Construct the FIS */
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500640 fis[0] = 0x27; /* Host to device FIS. */
641 fis[1] = 1 << 7; /* Command FIS. */
Rob Herring344ca0b2013-08-24 10:10:54 -0500642 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800643
644 /* Read id from sata */
645 port = pccb->target;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800646
Rob Herring344ca0b2013-08-24 10:10:54 -0500647 if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid,
648 ATA_ID_WORDS * 2, 0)) {
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800649 debug("scsi_ahci: SCSI inquiry command failure.\n");
650 return -EIO;
651 }
652
Roger Quadros3f629712014-04-01 17:26:40 +0300653 if (!ataid[port]) {
654 ataid[port] = malloc(ATA_ID_WORDS * 2);
655 if (!ataid[port]) {
656 printf("%s: No memory for ataid[port]\n", __func__);
657 return -ENOMEM;
658 }
659 }
660
661 idbuf = ataid[port];
662
663 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
664 ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800665
666 memcpy(&pccb->pdata[8], "ATA ", 8);
Roger Quadros3f629712014-04-01 17:26:40 +0300667 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
668 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800669
Rob Herring344ca0b2013-08-24 10:10:54 -0500670#ifdef DEBUG
Roger Quadros3f629712014-04-01 17:26:40 +0300671 ata_dump_id(idbuf);
Rob Herring344ca0b2013-08-24 10:10:54 -0500672#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800673 return 0;
674}
675
676
677/*
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000678 * SCSI READ10/WRITE10 command operation.
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800679 */
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000680static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800681{
Vadim Bendebury284231e2012-10-29 05:23:44 +0000682 u32 lba = 0;
683 u16 blocks = 0;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800684 u8 fis[20];
Vadim Bendebury284231e2012-10-29 05:23:44 +0000685 u8 *user_buffer = pccb->pdata;
686 u32 user_buffer_size = pccb->datalen;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800687
Vadim Bendebury284231e2012-10-29 05:23:44 +0000688 /* Retrieve the base LBA number from the ccb structure. */
689 memcpy(&lba, pccb->cmd + 2, sizeof(lba));
690 lba = be32_to_cpu(lba);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800691
Vadim Bendebury284231e2012-10-29 05:23:44 +0000692 /*
693 * And the number of blocks.
694 *
695 * For 10-byte and 16-byte SCSI R/W commands, transfer
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800696 * length 0 means transfer 0 block of data.
697 * However, for ATA R/W commands, sector count 0 means
698 * 256 or 65536 sectors, not 0 sectors as in SCSI.
699 *
700 * WARNING: one or two older ATA drives treat 0 as 0...
701 */
Vadim Bendebury284231e2012-10-29 05:23:44 +0000702 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
703
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000704 debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
705 is_write ? "write" : "read", (unsigned)lba, blocks);
Vadim Bendebury284231e2012-10-29 05:23:44 +0000706
707 /* Preset the FIS */
Taylor Huttc8731112012-10-29 05:23:55 +0000708 memset(fis, 0, sizeof(fis));
Vadim Bendebury284231e2012-10-29 05:23:44 +0000709 fis[0] = 0x27; /* Host to device FIS. */
710 fis[1] = 1 << 7; /* Command FIS. */
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000711 /* Command byte (read/write). */
Walter Murphyfe1f8082012-10-29 05:24:03 +0000712 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800713
Vadim Bendebury284231e2012-10-29 05:23:44 +0000714 while (blocks) {
715 u16 now_blocks; /* number of blocks per iteration */
716 u32 transfer_size; /* number of bytes per iteration */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800717
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000718 now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800719
Rob Herring344ca0b2013-08-24 10:10:54 -0500720 transfer_size = ATA_SECT_SIZE * now_blocks;
Vadim Bendebury284231e2012-10-29 05:23:44 +0000721 if (transfer_size > user_buffer_size) {
722 printf("scsi_ahci: Error: buffer too small.\n");
723 return -EIO;
724 }
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800725
Walter Murphyfe1f8082012-10-29 05:24:03 +0000726 /* LBA48 SATA command but only use 32bit address range within
727 * that. The next smaller command range (28bit) is too small.
728 */
Vadim Bendebury284231e2012-10-29 05:23:44 +0000729 fis[4] = (lba >> 0) & 0xff;
730 fis[5] = (lba >> 8) & 0xff;
731 fis[6] = (lba >> 16) & 0xff;
Walter Murphyfe1f8082012-10-29 05:24:03 +0000732 fis[7] = 1 << 6; /* device reg: set LBA mode */
733 fis[8] = ((lba >> 24) & 0xff);
734 fis[3] = 0xe0; /* features */
Vadim Bendebury284231e2012-10-29 05:23:44 +0000735
736 /* Block (sector) count */
737 fis[12] = (now_blocks >> 0) & 0xff;
738 fis[13] = (now_blocks >> 8) & 0xff;
739
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000740 /* Read/Write from ahci */
741 if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
742 user_buffer, user_buffer_size,
743 is_write)) {
744 debug("scsi_ahci: SCSI %s10 command failure.\n",
745 is_write ? "WRITE" : "READ");
Vadim Bendebury284231e2012-10-29 05:23:44 +0000746 return -EIO;
747 }
Marc Jones766b16f2012-10-29 05:24:02 +0000748
749 /* If this transaction is a write, do a following flush.
750 * Writes in u-boot are so rare, and the logic to know when is
751 * the last write and do a flush only there is sufficiently
752 * difficult. Just do a flush after every write. This incurs,
753 * usually, one extra flush when the rare writes do happen.
754 */
755 if (is_write) {
756 if (-EIO == ata_io_flush(pccb->target))
757 return -EIO;
758 }
Vadim Bendebury284231e2012-10-29 05:23:44 +0000759 user_buffer += transfer_size;
760 user_buffer_size -= transfer_size;
761 blocks -= now_blocks;
762 lba += now_blocks;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800763 }
764
765 return 0;
766}
767
768
769/*
770 * SCSI READ CAPACITY10 command operation.
771 */
772static int ata_scsiop_read_capacity10(ccb *pccb)
773{
Kumar Galacb6d0b72009-07-13 09:24:00 -0500774 u32 cap;
Rob Herring344ca0b2013-08-24 10:10:54 -0500775 u64 cap64;
Gabe Black19d1d412012-10-29 05:23:54 +0000776 u32 block_size;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800777
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500778 if (!ataid[pccb->target]) {
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800779 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500780 "\tNo ATA info!\n"
781 "\tPlease run SCSI commmand INQUIRY firstly!\n");
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800782 return -EPERM;
783 }
784
Rob Herring344ca0b2013-08-24 10:10:54 -0500785 cap64 = ata_id_n_sectors(ataid[pccb->target]);
786 if (cap64 > 0x100000000ULL)
787 cap64 = 0xffffffff;
Gabe Black19d1d412012-10-29 05:23:54 +0000788
Rob Herring344ca0b2013-08-24 10:10:54 -0500789 cap = cpu_to_be32(cap64);
Kumar Galacb6d0b72009-07-13 09:24:00 -0500790 memcpy(pccb->pdata, &cap, sizeof(cap));
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800791
Gabe Black19d1d412012-10-29 05:23:54 +0000792 block_size = cpu_to_be32((u32)512);
793 memcpy(&pccb->pdata[4], &block_size, 4);
794
795 return 0;
796}
797
798
799/*
800 * SCSI READ CAPACITY16 command operation.
801 */
802static int ata_scsiop_read_capacity16(ccb *pccb)
803{
804 u64 cap;
805 u64 block_size;
806
807 if (!ataid[pccb->target]) {
808 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
809 "\tNo ATA info!\n"
810 "\tPlease run SCSI commmand INQUIRY firstly!\n");
811 return -EPERM;
812 }
813
Rob Herring344ca0b2013-08-24 10:10:54 -0500814 cap = ata_id_n_sectors(ataid[pccb->target]);
Gabe Black19d1d412012-10-29 05:23:54 +0000815 cap = cpu_to_be64(cap);
816 memcpy(pccb->pdata, &cap, sizeof(cap));
817
818 block_size = cpu_to_be64((u64)512);
819 memcpy(&pccb->pdata[8], &block_size, 8);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800820
821 return 0;
822}
823
824
825/*
826 * SCSI TEST UNIT READY command operation.
827 */
828static int ata_scsiop_test_unit_ready(ccb *pccb)
829{
830 return (ataid[pccb->target]) ? 0 : -EPERM;
831}
832
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500833
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800834int scsi_exec(ccb *pccb)
835{
836 int ret;
837
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500838 switch (pccb->cmd[0]) {
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800839 case SCSI_READ10:
Hung-Te Linb7a21b72012-10-29 05:23:53 +0000840 ret = ata_scsiop_read_write(pccb, 0);
841 break;
842 case SCSI_WRITE10:
843 ret = ata_scsiop_read_write(pccb, 1);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800844 break;
Gabe Black19d1d412012-10-29 05:23:54 +0000845 case SCSI_RD_CAPAC10:
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800846 ret = ata_scsiop_read_capacity10(pccb);
847 break;
Gabe Black19d1d412012-10-29 05:23:54 +0000848 case SCSI_RD_CAPAC16:
849 ret = ata_scsiop_read_capacity16(pccb);
850 break;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800851 case SCSI_TST_U_RDY:
852 ret = ata_scsiop_test_unit_ready(pccb);
853 break;
854 case SCSI_INQUIRY:
855 ret = ata_scsiop_inquiry(pccb);
856 break;
857 default:
858 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
York Sun472d5462013-04-01 11:29:11 -0700859 return false;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800860 }
861
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500862 if (ret) {
863 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
York Sun472d5462013-04-01 11:29:11 -0700864 return false;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800865 }
York Sun472d5462013-04-01 11:29:11 -0700866 return true;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800867
868}
869
870
871void scsi_low_level_init(int busdevfunc)
872{
873 int i;
874 u32 linkmap;
875
Rob Herring942e3142011-07-06 16:13:36 +0000876#ifndef CONFIG_SCSI_AHCI_PLAT
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800877 ahci_init_one(busdevfunc);
Rob Herring942e3142011-07-06 16:13:36 +0000878#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800879
880 linkmap = probe_ent->link_port_map;
881
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200882 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500883 if (((linkmap >> i) & 0x01)) {
884 if (ahci_port_start((u8) i)) {
885 printf("Can not start port %d\n", i);
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800886 continue;
887 }
Gabe Blacke81058c2012-10-29 05:23:52 +0000888#ifdef CONFIG_AHCI_SETFEATURES_XFER
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500889 ahci_set_feature((u8) i);
Gabe Blacke81058c2012-10-29 05:23:52 +0000890#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800891 }
892 }
893}
894
Rob Herring942e3142011-07-06 16:13:36 +0000895#ifdef CONFIG_SCSI_AHCI_PLAT
896int ahci_init(u32 base)
897{
898 int i, rc = 0;
899 u32 linkmap;
900
Rob Herring942e3142011-07-06 16:13:36 +0000901 probe_ent = malloc(sizeof(struct ahci_probe_ent));
Roger Quadrosd73763a2013-11-11 16:56:37 +0200902 if (!probe_ent) {
903 printf("%s: No memory for probe_ent\n", __func__);
904 return -ENOMEM;
905 }
906
Rob Herring942e3142011-07-06 16:13:36 +0000907 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
908
909 probe_ent->host_flags = ATA_FLAG_SATA
910 | ATA_FLAG_NO_LEGACY
911 | ATA_FLAG_MMIO
912 | ATA_FLAG_PIO_DMA
913 | ATA_FLAG_NO_ATAPI;
914 probe_ent->pio_mask = 0x1f;
915 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
916
917 probe_ent->mmio_base = base;
918
919 /* initialize adapter */
920 rc = ahci_host_init(probe_ent);
921 if (rc)
922 goto err_out;
923
924 ahci_print_info(probe_ent);
925
926 linkmap = probe_ent->link_port_map;
927
928 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
929 if (((linkmap >> i) & 0x01)) {
930 if (ahci_port_start((u8) i)) {
931 printf("Can not start port %d\n", i);
932 continue;
933 }
Gabe Blacke81058c2012-10-29 05:23:52 +0000934#ifdef CONFIG_AHCI_SETFEATURES_XFER
Rob Herring942e3142011-07-06 16:13:36 +0000935 ahci_set_feature((u8) i);
Gabe Blacke81058c2012-10-29 05:23:52 +0000936#endif
Rob Herring942e3142011-07-06 16:13:36 +0000937 }
938 }
939err_out:
940 return rc;
941}
Ian Campbellc6f3d502014-03-07 01:20:56 +0000942
943void __weak scsi_init(void)
944{
945}
946
Rob Herring942e3142011-07-06 16:13:36 +0000947#endif
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800948
Marc Jones766b16f2012-10-29 05:24:02 +0000949/*
950 * In the general case of generic rotating media it makes sense to have a
951 * flush capability. It probably even makes sense in the case of SSDs because
952 * one cannot always know for sure what kind of internal cache/flush mechanism
953 * is embodied therein. At first it was planned to invoke this after the last
954 * write to disk and before rebooting. In practice, knowing, a priori, which
955 * is the last write is difficult. Because writing to the disk in u-boot is
956 * very rare, this flush command will be invoked after every block write.
957 */
958static int ata_io_flush(u8 port)
959{
960 u8 fis[20];
961 struct ahci_ioports *pp = &(probe_ent->port[port]);
962 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
963 u32 cmd_fis_len = 5; /* five dwords */
964
965 /* Preset the FIS */
966 memset(fis, 0, 20);
967 fis[0] = 0x27; /* Host to device FIS. */
968 fis[1] = 1 << 7; /* Command FIS. */
Walter Murphyfe1f8082012-10-29 05:24:03 +0000969 fis[2] = ATA_CMD_FLUSH_EXT;
Marc Jones766b16f2012-10-29 05:24:02 +0000970
971 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
972 ahci_fill_cmd_slot(pp, cmd_fis_len);
973 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
974
975 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
976 WAIT_MS_FLUSH, 0x1)) {
977 debug("scsi_ahci: flush command timeout on port %d.\n", port);
978 return -EIO;
979 }
980
981 return 0;
982}
983
984
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800985void scsi_bus_reset(void)
986{
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500987 /*Not implement*/
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800988}
989
990
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500991void scsi_print_error(ccb * pccb)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800992{
Jon Loeliger4a7cc0f2006-08-23 11:04:43 -0500993 /*The ahci error info can be read in the ahci driver*/
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800994}