Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 1 | /* |
Kumar Gala | 4c2e3da | 2009-07-28 21:49:52 -0500 | [diff] [blame] | 2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 3 | * Author: Jason Jin<Jason.jin@freescale.com> |
| 4 | * Zhang Wei<wei.zhang@freescale.com> |
| 5 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 7 | * |
| 8 | * with the reference on libata and ahci drvier in kernel |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 9 | */ |
| 10 | #include <common.h> |
| 11 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 12 | #include <command.h> |
| 13 | #include <pci.h> |
| 14 | #include <asm/processor.h> |
| 15 | #include <asm/errno.h> |
| 16 | #include <asm/io.h> |
| 17 | #include <malloc.h> |
| 18 | #include <scsi.h> |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 19 | #include <libata.h> |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 20 | #include <linux/ctype.h> |
| 21 | #include <ahci.h> |
| 22 | |
Marc Jones | 766b16f | 2012-10-29 05:24:02 +0000 | [diff] [blame] | 23 | static int ata_io_flush(u8 port); |
| 24 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 25 | struct ahci_probe_ent *probe_ent = NULL; |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 26 | u16 *ataid[AHCI_MAX_PORTS]; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 27 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 28 | #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) |
| 29 | |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 30 | /* |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 31 | * Some controllers limit number of blocks they can read/write at once. |
| 32 | * Contemporary SSD devices work much faster if the read/write size is aligned |
| 33 | * to a power of 2. Let's set default to 128 and allowing to be overwritten if |
| 34 | * needed. |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 35 | */ |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 36 | #ifndef MAX_SATA_BLOCKS_READ_WRITE |
| 37 | #define MAX_SATA_BLOCKS_READ_WRITE 0x80 |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 38 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 39 | |
Walter Murphy | 5784766 | 2012-10-29 05:24:00 +0000 | [diff] [blame] | 40 | /* Maximum timeouts for each event */ |
Rob Herring | 7610b41 | 2013-08-24 10:10:53 -0500 | [diff] [blame] | 41 | #define WAIT_MS_SPINUP 20000 |
Walter Murphy | 5784766 | 2012-10-29 05:24:00 +0000 | [diff] [blame] | 42 | #define WAIT_MS_DATAIO 5000 |
Marc Jones | 766b16f | 2012-10-29 05:24:02 +0000 | [diff] [blame] | 43 | #define WAIT_MS_FLUSH 5000 |
Walter Murphy | 5784766 | 2012-10-29 05:24:00 +0000 | [diff] [blame] | 44 | #define WAIT_MS_LINKUP 4 |
| 45 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 46 | static inline u32 ahci_port_base(u32 base, u32 port) |
| 47 | { |
| 48 | return base + 0x100 + (port * 0x80); |
| 49 | } |
| 50 | |
| 51 | |
| 52 | static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, |
| 53 | unsigned int port_idx) |
| 54 | { |
| 55 | base = ahci_port_base(base, port_idx); |
| 56 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 57 | port->cmd_addr = base; |
| 58 | port->scr_addr = base + PORT_SCR; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 59 | } |
| 60 | |
| 61 | |
| 62 | #define msleep(a) udelay(a * 1000) |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 63 | |
Taylor Hutt | 90b276f | 2012-10-29 05:23:59 +0000 | [diff] [blame] | 64 | static void ahci_dcache_flush_range(unsigned begin, unsigned len) |
| 65 | { |
| 66 | const unsigned long start = begin; |
| 67 | const unsigned long end = start + len; |
| 68 | |
| 69 | debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end); |
| 70 | flush_dcache_range(start, end); |
| 71 | } |
| 72 | |
| 73 | /* |
| 74 | * SATA controller DMAs to physical RAM. Ensure data from the |
| 75 | * controller is invalidated from dcache; next access comes from |
| 76 | * physical RAM. |
| 77 | */ |
| 78 | static void ahci_dcache_invalidate_range(unsigned begin, unsigned len) |
| 79 | { |
| 80 | const unsigned long start = begin; |
| 81 | const unsigned long end = start + len; |
| 82 | |
| 83 | debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end); |
| 84 | invalidate_dcache_range(start, end); |
| 85 | } |
| 86 | |
| 87 | /* |
| 88 | * Ensure data for SATA controller is flushed out of dcache and |
| 89 | * written to physical memory. |
| 90 | */ |
| 91 | static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp) |
| 92 | { |
| 93 | ahci_dcache_flush_range((unsigned long)pp->cmd_slot, |
| 94 | AHCI_PORT_PRIV_DMA_SZ); |
| 95 | } |
| 96 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 97 | static int waiting_for_cmd_completed(volatile u8 *offset, |
| 98 | int timeout_msec, |
| 99 | u32 sign) |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 100 | { |
| 101 | int i; |
| 102 | u32 status; |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 103 | |
| 104 | for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 105 | msleep(1); |
| 106 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 107 | return (i < timeout_msec) ? 0 : -1; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 108 | } |
| 109 | |
Rob Herring | 124e9fa | 2013-08-24 10:10:51 -0500 | [diff] [blame] | 110 | int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port) |
| 111 | { |
| 112 | u32 tmp; |
| 113 | int j = 0; |
| 114 | u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio; |
| 115 | |
Wolfgang Denk | 3765b3e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 116 | /* |
Rob Herring | 124e9fa | 2013-08-24 10:10:51 -0500 | [diff] [blame] | 117 | * Bring up SATA link. |
| 118 | * SATA link bringup time is usually less than 1 ms; only very |
| 119 | * rarely has it taken between 1-2 ms. Never seen it above 2 ms. |
| 120 | */ |
| 121 | while (j < WAIT_MS_LINKUP) { |
| 122 | tmp = readl(port_mmio + PORT_SCR_STAT); |
| 123 | tmp &= PORT_SCR_STAT_DET_MASK; |
| 124 | if (tmp == PORT_SCR_STAT_DET_PHYRDY) |
| 125 | return 0; |
| 126 | udelay(1000); |
| 127 | j++; |
| 128 | } |
| 129 | return 1; |
| 130 | } |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 131 | |
| 132 | static int ahci_host_init(struct ahci_probe_ent *probe_ent) |
| 133 | { |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 134 | #ifndef CONFIG_SCSI_AHCI_PLAT |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 135 | pci_dev_t pdev = probe_ent->dev; |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 136 | u16 tmp16; |
| 137 | unsigned short vendor; |
| 138 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 139 | volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; |
Marc Jones | 2a0c61d | 2012-10-29 05:24:01 +0000 | [diff] [blame] | 140 | u32 tmp, cap_save, cmd; |
Rob Herring | 124e9fa | 2013-08-24 10:10:51 -0500 | [diff] [blame] | 141 | int i, j, ret; |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 142 | volatile u8 *port_mmio; |
Richard Gibbs | 2915a02 | 2013-08-24 10:10:47 -0500 | [diff] [blame] | 143 | u32 port_map; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 144 | |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 145 | debug("ahci_host_init: start\n"); |
| 146 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 147 | cap_save = readl(mmio + HOST_CAP); |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 148 | cap_save &= ((1 << 28) | (1 << 17)); |
Marc Jones | 2a0c61d | 2012-10-29 05:24:01 +0000 | [diff] [blame] | 149 | cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 150 | |
| 151 | /* global controller reset */ |
| 152 | tmp = readl(mmio + HOST_CTL); |
| 153 | if ((tmp & HOST_RESET) == 0) |
| 154 | writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL); |
| 155 | |
| 156 | /* reset must complete within 1 second, or |
| 157 | * the hardware should be considered fried. |
| 158 | */ |
Stefan Reinauer | 9a65b87 | 2012-10-29 05:23:49 +0000 | [diff] [blame] | 159 | i = 1000; |
| 160 | do { |
| 161 | udelay(1000); |
| 162 | tmp = readl(mmio + HOST_CTL); |
| 163 | if (!i--) { |
| 164 | debug("controller reset failed (0x%x)\n", tmp); |
| 165 | return -1; |
| 166 | } |
| 167 | } while (tmp & HOST_RESET); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 168 | |
| 169 | writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); |
| 170 | writel(cap_save, mmio + HOST_CAP); |
| 171 | writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); |
| 172 | |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 173 | #ifndef CONFIG_SCSI_AHCI_PLAT |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 174 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); |
| 175 | |
| 176 | if (vendor == PCI_VENDOR_ID_INTEL) { |
| 177 | u16 tmp16; |
| 178 | pci_read_config_word(pdev, 0x92, &tmp16); |
| 179 | tmp16 |= 0xf; |
| 180 | pci_write_config_word(pdev, 0x92, tmp16); |
| 181 | } |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 182 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 183 | probe_ent->cap = readl(mmio + HOST_CAP); |
| 184 | probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); |
Richard Gibbs | 2915a02 | 2013-08-24 10:10:47 -0500 | [diff] [blame] | 185 | port_map = probe_ent->port_map; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 186 | probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; |
| 187 | |
| 188 | debug("cap 0x%x port_map 0x%x n_ports %d\n", |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 189 | probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 190 | |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 191 | if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID) |
| 192 | probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID; |
| 193 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 194 | for (i = 0; i < probe_ent->n_ports; i++) { |
Richard Gibbs | 2915a02 | 2013-08-24 10:10:47 -0500 | [diff] [blame] | 195 | if (!(port_map & (1 << i))) |
| 196 | continue; |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 197 | probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); |
| 198 | port_mmio = (u8 *) probe_ent->port[i].port_mmio; |
| 199 | ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 200 | |
| 201 | /* make sure port is not active */ |
| 202 | tmp = readl(port_mmio + PORT_CMD); |
| 203 | if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | |
| 204 | PORT_CMD_FIS_RX | PORT_CMD_START)) { |
Stefan Reinauer | 7ba7917 | 2012-10-29 05:23:50 +0000 | [diff] [blame] | 205 | debug("Port %d is active. Deactivating.\n", i); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 206 | tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | |
| 207 | PORT_CMD_FIS_RX | PORT_CMD_START); |
| 208 | writel_with_flush(tmp, port_mmio + PORT_CMD); |
| 209 | |
| 210 | /* spec says 500 msecs for each bit, so |
| 211 | * this is slightly incorrect. |
| 212 | */ |
| 213 | msleep(500); |
| 214 | } |
| 215 | |
Marc Jones | 2a0c61d | 2012-10-29 05:24:01 +0000 | [diff] [blame] | 216 | /* Add the spinup command to whatever mode bits may |
| 217 | * already be on in the command register. |
| 218 | */ |
| 219 | cmd = readl(port_mmio + PORT_CMD); |
| 220 | cmd |= PORT_CMD_FIS_RX; |
| 221 | cmd |= PORT_CMD_SPIN_UP; |
| 222 | writel_with_flush(cmd, port_mmio + PORT_CMD); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 223 | |
Rob Herring | 124e9fa | 2013-08-24 10:10:51 -0500 | [diff] [blame] | 224 | /* Bring up SATA link. */ |
| 225 | ret = ahci_link_up(probe_ent, i); |
| 226 | if (ret) { |
Marc Jones | 2a0c61d | 2012-10-29 05:24:01 +0000 | [diff] [blame] | 227 | printf("SATA link %d timeout.\n", i); |
| 228 | continue; |
| 229 | } else { |
| 230 | debug("SATA link ok.\n"); |
| 231 | } |
| 232 | |
| 233 | /* Clear error status */ |
| 234 | tmp = readl(port_mmio + PORT_SCR_ERR); |
| 235 | if (tmp) |
| 236 | writel(tmp, port_mmio + PORT_SCR_ERR); |
| 237 | |
| 238 | debug("Spinning up device on SATA port %d... ", i); |
| 239 | |
| 240 | j = 0; |
| 241 | while (j < WAIT_MS_SPINUP) { |
| 242 | tmp = readl(port_mmio + PORT_TFDATA); |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 243 | if (!(tmp & (ATA_BUSY | ATA_DRQ))) |
Marc Jones | 2a0c61d | 2012-10-29 05:24:01 +0000 | [diff] [blame] | 244 | break; |
| 245 | udelay(1000); |
Rob Herring | 1782108 | 2013-08-24 10:10:52 -0500 | [diff] [blame] | 246 | tmp = readl(port_mmio + PORT_SCR_STAT); |
| 247 | tmp &= PORT_SCR_STAT_DET_MASK; |
| 248 | if (tmp == PORT_SCR_STAT_DET_PHYRDY) |
| 249 | break; |
Marc Jones | 2a0c61d | 2012-10-29 05:24:01 +0000 | [diff] [blame] | 250 | j++; |
| 251 | } |
Rob Herring | 1782108 | 2013-08-24 10:10:52 -0500 | [diff] [blame] | 252 | |
| 253 | tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK; |
| 254 | if (tmp == PORT_SCR_STAT_DET_COMINIT) { |
| 255 | debug("SATA link %d down (COMINIT received), retrying...\n", i); |
| 256 | i--; |
| 257 | continue; |
| 258 | } |
| 259 | |
Marc Jones | 2a0c61d | 2012-10-29 05:24:01 +0000 | [diff] [blame] | 260 | printf("Target spinup took %d ms.\n", j); |
| 261 | if (j == WAIT_MS_SPINUP) |
Stefan Reinauer | 9a65b87 | 2012-10-29 05:23:49 +0000 | [diff] [blame] | 262 | debug("timeout.\n"); |
| 263 | else |
| 264 | debug("ok.\n"); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 265 | |
| 266 | tmp = readl(port_mmio + PORT_SCR_ERR); |
| 267 | debug("PORT_SCR_ERR 0x%x\n", tmp); |
| 268 | writel(tmp, port_mmio + PORT_SCR_ERR); |
| 269 | |
| 270 | /* ack any pending irq events for this port */ |
| 271 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 272 | debug("PORT_IRQ_STAT 0x%x\n", tmp); |
| 273 | if (tmp) |
| 274 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
| 275 | |
| 276 | writel(1 << i, mmio + HOST_IRQ_STAT); |
| 277 | |
| 278 | /* set irq mask (enables interrupts) */ |
| 279 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); |
| 280 | |
Stefan Reinauer | 4e422bc | 2012-10-29 05:23:51 +0000 | [diff] [blame] | 281 | /* register linkup ports */ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 282 | tmp = readl(port_mmio + PORT_SCR_STAT); |
Marc Jones | 766b16f | 2012-10-29 05:24:02 +0000 | [diff] [blame] | 283 | debug("SATA port %d status: 0x%x\n", i, tmp); |
Rob Herring | 2bdb10d | 2013-08-24 10:10:50 -0500 | [diff] [blame] | 284 | if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY) |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 285 | probe_ent->link_port_map |= (0x01 << i); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 286 | } |
| 287 | |
| 288 | tmp = readl(mmio + HOST_CTL); |
| 289 | debug("HOST_CTL 0x%x\n", tmp); |
| 290 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); |
| 291 | tmp = readl(mmio + HOST_CTL); |
| 292 | debug("HOST_CTL 0x%x\n", tmp); |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 293 | #ifndef CONFIG_SCSI_AHCI_PLAT |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 294 | pci_read_config_word(pdev, PCI_COMMAND, &tmp16); |
| 295 | tmp |= PCI_COMMAND_MASTER; |
| 296 | pci_write_config_word(pdev, PCI_COMMAND, tmp16); |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 297 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 298 | return 0; |
| 299 | } |
| 300 | |
| 301 | |
| 302 | static void ahci_print_info(struct ahci_probe_ent *probe_ent) |
| 303 | { |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 304 | #ifndef CONFIG_SCSI_AHCI_PLAT |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 305 | pci_dev_t pdev = probe_ent->dev; |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 306 | u16 cc; |
| 307 | #endif |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 308 | volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; |
Stefan Reinauer | 4e422bc | 2012-10-29 05:23:51 +0000 | [diff] [blame] | 309 | u32 vers, cap, cap2, impl, speed; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 310 | const char *speed_s; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 311 | const char *scc_s; |
| 312 | |
| 313 | vers = readl(mmio + HOST_VERSION); |
| 314 | cap = probe_ent->cap; |
Stefan Reinauer | 4e422bc | 2012-10-29 05:23:51 +0000 | [diff] [blame] | 315 | cap2 = readl(mmio + HOST_CAP2); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 316 | impl = probe_ent->port_map; |
| 317 | |
| 318 | speed = (cap >> 20) & 0xf; |
| 319 | if (speed == 1) |
| 320 | speed_s = "1.5"; |
| 321 | else if (speed == 2) |
| 322 | speed_s = "3"; |
Stefan Reinauer | 4e422bc | 2012-10-29 05:23:51 +0000 | [diff] [blame] | 323 | else if (speed == 3) |
| 324 | speed_s = "6"; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 325 | else |
| 326 | speed_s = "?"; |
| 327 | |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 328 | #ifdef CONFIG_SCSI_AHCI_PLAT |
| 329 | scc_s = "SATA"; |
| 330 | #else |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 331 | pci_read_config_word(pdev, 0x0a, &cc); |
| 332 | if (cc == 0x0101) |
| 333 | scc_s = "IDE"; |
| 334 | else if (cc == 0x0106) |
| 335 | scc_s = "SATA"; |
| 336 | else if (cc == 0x0104) |
| 337 | scc_s = "RAID"; |
| 338 | else |
| 339 | scc_s = "unknown"; |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 340 | #endif |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 341 | printf("AHCI %02x%02x.%02x%02x " |
| 342 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n", |
| 343 | (vers >> 24) & 0xff, |
| 344 | (vers >> 16) & 0xff, |
| 345 | (vers >> 8) & 0xff, |
| 346 | vers & 0xff, |
| 347 | ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 348 | |
| 349 | printf("flags: " |
Stefan Reinauer | 4e422bc | 2012-10-29 05:23:51 +0000 | [diff] [blame] | 350 | "%s%s%s%s%s%s%s" |
| 351 | "%s%s%s%s%s%s%s" |
| 352 | "%s%s%s%s%s%s\n", |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 353 | cap & (1 << 31) ? "64bit " : "", |
| 354 | cap & (1 << 30) ? "ncq " : "", |
| 355 | cap & (1 << 28) ? "ilck " : "", |
| 356 | cap & (1 << 27) ? "stag " : "", |
| 357 | cap & (1 << 26) ? "pm " : "", |
| 358 | cap & (1 << 25) ? "led " : "", |
| 359 | cap & (1 << 24) ? "clo " : "", |
| 360 | cap & (1 << 19) ? "nz " : "", |
| 361 | cap & (1 << 18) ? "only " : "", |
| 362 | cap & (1 << 17) ? "pmp " : "", |
Stefan Reinauer | 4e422bc | 2012-10-29 05:23:51 +0000 | [diff] [blame] | 363 | cap & (1 << 16) ? "fbss " : "", |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 364 | cap & (1 << 15) ? "pio " : "", |
| 365 | cap & (1 << 14) ? "slum " : "", |
Stefan Reinauer | 4e422bc | 2012-10-29 05:23:51 +0000 | [diff] [blame] | 366 | cap & (1 << 13) ? "part " : "", |
| 367 | cap & (1 << 7) ? "ccc " : "", |
| 368 | cap & (1 << 6) ? "ems " : "", |
| 369 | cap & (1 << 5) ? "sxs " : "", |
| 370 | cap2 & (1 << 2) ? "apst " : "", |
| 371 | cap2 & (1 << 1) ? "nvmp " : "", |
| 372 | cap2 & (1 << 0) ? "boh " : ""); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 373 | } |
| 374 | |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 375 | #ifndef CONFIG_SCSI_AHCI_PLAT |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 376 | static int ahci_init_one(pci_dev_t pdev) |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 377 | { |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 378 | u16 vendor; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 379 | int rc; |
| 380 | |
Ed Swarthout | 594e798 | 2007-08-14 14:06:45 -0500 | [diff] [blame] | 381 | probe_ent = malloc(sizeof(struct ahci_probe_ent)); |
Roger Quadros | d73763a | 2013-11-11 16:56:37 +0200 | [diff] [blame] | 382 | if (!probe_ent) { |
| 383 | printf("%s: No memory for probe_ent\n", __func__); |
| 384 | return -ENOMEM; |
| 385 | } |
| 386 | |
Ed Swarthout | 594e798 | 2007-08-14 14:06:45 -0500 | [diff] [blame] | 387 | memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 388 | probe_ent->dev = pdev; |
| 389 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 390 | probe_ent->host_flags = ATA_FLAG_SATA |
| 391 | | ATA_FLAG_NO_LEGACY |
| 392 | | ATA_FLAG_MMIO |
| 393 | | ATA_FLAG_PIO_DMA |
| 394 | | ATA_FLAG_NO_ATAPI; |
| 395 | probe_ent->pio_mask = 0x1f; |
| 396 | probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 397 | |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 398 | pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base); |
| 399 | debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 400 | |
| 401 | /* Take from kernel: |
| 402 | * JMicron-specific fixup: |
| 403 | * make sure we're in AHCI mode |
| 404 | */ |
| 405 | pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 406 | if (vendor == 0x197b) |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 407 | pci_write_config_byte(pdev, 0x41, 0xa1); |
| 408 | |
| 409 | /* initialize adapter */ |
| 410 | rc = ahci_host_init(probe_ent); |
| 411 | if (rc) |
| 412 | goto err_out; |
| 413 | |
| 414 | ahci_print_info(probe_ent); |
| 415 | |
| 416 | return 0; |
| 417 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 418 | err_out: |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 419 | return rc; |
| 420 | } |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 421 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 422 | |
| 423 | #define MAX_DATA_BYTE_COUNT (4*1024*1024) |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 424 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 425 | static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) |
| 426 | { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 427 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
| 428 | struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; |
| 429 | u32 sg_count; |
| 430 | int i; |
| 431 | |
| 432 | sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 433 | if (sg_count > AHCI_MAX_SG) { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 434 | printf("Error:Too much sg!\n"); |
| 435 | return -1; |
| 436 | } |
| 437 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 438 | for (i = 0; i < sg_count; i++) { |
| 439 | ahci_sg->addr = |
| 440 | cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 441 | ahci_sg->addr_hi = 0; |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 442 | ahci_sg->flags_size = cpu_to_le32(0x3fffff & |
| 443 | (buf_len < MAX_DATA_BYTE_COUNT |
| 444 | ? (buf_len - 1) |
| 445 | : (MAX_DATA_BYTE_COUNT - 1))); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 446 | ahci_sg++; |
| 447 | buf_len -= MAX_DATA_BYTE_COUNT; |
| 448 | } |
| 449 | |
| 450 | return sg_count; |
| 451 | } |
| 452 | |
| 453 | |
| 454 | static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) |
| 455 | { |
| 456 | pp->cmd_slot->opts = cpu_to_le32(opts); |
| 457 | pp->cmd_slot->status = 0; |
| 458 | pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); |
| 459 | pp->cmd_slot->tbl_addr_hi = 0; |
| 460 | } |
| 461 | |
| 462 | |
Gabe Black | e81058c | 2012-10-29 05:23:52 +0000 | [diff] [blame] | 463 | #ifdef CONFIG_AHCI_SETFEATURES_XFER |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 464 | static void ahci_set_feature(u8 port) |
| 465 | { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 466 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 467 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
| 468 | u32 cmd_fis_len = 5; /* five dwords */ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 469 | u8 fis[20]; |
| 470 | |
Stefan Reinauer | 4e422bc | 2012-10-29 05:23:51 +0000 | [diff] [blame] | 471 | /* set feature */ |
Taylor Hutt | c873111 | 2012-10-29 05:23:55 +0000 | [diff] [blame] | 472 | memset(fis, 0, sizeof(fis)); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 473 | fis[0] = 0x27; |
| 474 | fis[1] = 1 << 7; |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 475 | fis[2] = ATA_CMD_SET_FEATURES; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 476 | fis[3] = SETFEATURES_XFER; |
| 477 | fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; |
| 478 | |
Taylor Hutt | c873111 | 2012-10-29 05:23:55 +0000 | [diff] [blame] | 479 | memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis)); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 480 | ahci_fill_cmd_slot(pp, cmd_fis_len); |
Taylor Hutt | 90b276f | 2012-10-29 05:23:59 +0000 | [diff] [blame] | 481 | ahci_dcache_flush_sata_cmd(pp); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 482 | writel(1, port_mmio + PORT_CMD_ISSUE); |
| 483 | readl(port_mmio + PORT_CMD_ISSUE); |
| 484 | |
Walter Murphy | 5784766 | 2012-10-29 05:24:00 +0000 | [diff] [blame] | 485 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, |
| 486 | WAIT_MS_DATAIO, 0x1)) { |
Stefan Reinauer | 4e422bc | 2012-10-29 05:23:51 +0000 | [diff] [blame] | 487 | printf("set feature error on port %d!\n", port); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 488 | } |
| 489 | } |
Gabe Black | e81058c | 2012-10-29 05:23:52 +0000 | [diff] [blame] | 490 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 491 | |
| 492 | |
| 493 | static int ahci_port_start(u8 port) |
| 494 | { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 495 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 496 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 497 | u32 port_status; |
| 498 | u32 mem; |
| 499 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 500 | debug("Enter start port: %d\n", port); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 501 | port_status = readl(port_mmio + PORT_SCR_STAT); |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 502 | debug("Port %d status: %x\n", port, port_status); |
| 503 | if ((port_status & 0xf) != 0x03) { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 504 | printf("No Link on this port!\n"); |
| 505 | return -1; |
| 506 | } |
| 507 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 508 | mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 509 | if (!mem) { |
| 510 | free(pp); |
Roger Quadros | d73763a | 2013-11-11 16:56:37 +0200 | [diff] [blame] | 511 | printf("%s: No mem for table!\n", __func__); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 512 | return -ENOMEM; |
| 513 | } |
| 514 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 515 | mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ |
| 516 | memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 517 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 518 | /* |
| 519 | * First item in chunk of DMA memory: 32-slot command table, |
| 520 | * 32 bytes each in size |
| 521 | */ |
Taylor Hutt | 64738e8 | 2012-10-29 05:23:58 +0000 | [diff] [blame] | 522 | pp->cmd_slot = |
| 523 | (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem); |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 524 | debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 525 | mem += (AHCI_CMD_SLOT_SZ + 224); |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 526 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 527 | /* |
| 528 | * Second item: Received-FIS area |
| 529 | */ |
Taylor Hutt | 64738e8 | 2012-10-29 05:23:58 +0000 | [diff] [blame] | 530 | pp->rx_fis = virt_to_phys((void *)mem); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 531 | mem += AHCI_RX_FIS_SZ; |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 532 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 533 | /* |
| 534 | * Third item: data area for storing a single command |
| 535 | * and its scatter-gather table |
| 536 | */ |
Taylor Hutt | 64738e8 | 2012-10-29 05:23:58 +0000 | [diff] [blame] | 537 | pp->cmd_tbl = virt_to_phys((void *)mem); |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 538 | debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 539 | |
| 540 | mem += AHCI_CMD_TBL_HDR; |
Taylor Hutt | 64738e8 | 2012-10-29 05:23:58 +0000 | [diff] [blame] | 541 | pp->cmd_tbl_sg = |
| 542 | (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 543 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 544 | writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 545 | |
| 546 | writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); |
| 547 | |
| 548 | writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 549 | PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | |
| 550 | PORT_CMD_START, port_mmio + PORT_CMD); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 551 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 552 | debug("Exit start port %d\n", port); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 553 | |
| 554 | return 0; |
| 555 | } |
| 556 | |
| 557 | |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 558 | static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, |
| 559 | int buf_len, u8 is_write) |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 560 | { |
| 561 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 562 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
| 563 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 564 | u32 opts; |
| 565 | u32 port_status; |
| 566 | int sg_count; |
| 567 | |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 568 | debug("Enter %s: for port %d\n", __func__, port); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 569 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 570 | if (port > probe_ent->n_ports) { |
Taylor Hutt | 5a2b77f | 2012-10-29 05:23:56 +0000 | [diff] [blame] | 571 | printf("Invalid port number %d\n", port); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 572 | return -1; |
| 573 | } |
| 574 | |
| 575 | port_status = readl(port_mmio + PORT_SCR_STAT); |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 576 | if ((port_status & 0xf) != 0x03) { |
| 577 | debug("No Link on port %d!\n", port); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 578 | return -1; |
| 579 | } |
| 580 | |
| 581 | memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); |
| 582 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 583 | sg_count = ahci_fill_sg(port, buf, buf_len); |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 584 | opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 585 | ahci_fill_cmd_slot(pp, opts); |
| 586 | |
Taylor Hutt | 90b276f | 2012-10-29 05:23:59 +0000 | [diff] [blame] | 587 | ahci_dcache_flush_sata_cmd(pp); |
| 588 | ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len); |
| 589 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 590 | writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); |
| 591 | |
Walter Murphy | 5784766 | 2012-10-29 05:24:00 +0000 | [diff] [blame] | 592 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, |
| 593 | WAIT_MS_DATAIO, 0x1)) { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 594 | printf("timeout exit!\n"); |
| 595 | return -1; |
| 596 | } |
Taylor Hutt | 90b276f | 2012-10-29 05:23:59 +0000 | [diff] [blame] | 597 | |
| 598 | ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len); |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 599 | debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 600 | |
| 601 | return 0; |
| 602 | } |
| 603 | |
| 604 | |
| 605 | static char *ata_id_strcpy(u16 *target, u16 *src, int len) |
| 606 | { |
| 607 | int i; |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 608 | for (i = 0; i < len / 2; i++) |
Rob Herring | e5a6c79 | 2011-06-01 09:10:26 +0000 | [diff] [blame] | 609 | target[i] = swab16(src[i]); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 610 | return (char *)target; |
| 611 | } |
| 612 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 613 | /* |
| 614 | * SCSI INQUIRY command operation. |
| 615 | */ |
| 616 | static int ata_scsiop_inquiry(ccb *pccb) |
| 617 | { |
Rob Herring | 48c3a87 | 2013-08-24 10:10:48 -0500 | [diff] [blame] | 618 | static const u8 hdr[] = { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 619 | 0, |
| 620 | 0, |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 621 | 0x5, /* claim SPC-3 version compatibility */ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 622 | 2, |
| 623 | 95 - 4, |
| 624 | }; |
| 625 | u8 fis[20]; |
Roger Quadros | 2faf5fb | 2013-11-11 16:56:38 +0200 | [diff] [blame] | 626 | ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 627 | u8 port; |
| 628 | |
| 629 | /* Clean ccb data buffer */ |
| 630 | memset(pccb->pdata, 0, pccb->datalen); |
| 631 | |
| 632 | memcpy(pccb->pdata, hdr, sizeof(hdr)); |
| 633 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 634 | if (pccb->datalen <= 35) |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 635 | return 0; |
| 636 | |
Taylor Hutt | c873111 | 2012-10-29 05:23:55 +0000 | [diff] [blame] | 637 | memset(fis, 0, sizeof(fis)); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 638 | /* Construct the FIS */ |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 639 | fis[0] = 0x27; /* Host to device FIS. */ |
| 640 | fis[1] = 1 << 7; /* Command FIS. */ |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 641 | fis[2] = ATA_CMD_ID_ATA; /* Command byte. */ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 642 | |
| 643 | /* Read id from sata */ |
| 644 | port = pccb->target; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 645 | |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 646 | if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid, |
| 647 | ATA_ID_WORDS * 2, 0)) { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 648 | debug("scsi_ahci: SCSI inquiry command failure.\n"); |
| 649 | return -EIO; |
| 650 | } |
| 651 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 652 | if (ataid[port]) |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 653 | free(ataid[port]); |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 654 | ataid[port] = tmpid; |
| 655 | ata_swap_buf_le16(tmpid, ATA_ID_WORDS); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 656 | |
| 657 | memcpy(&pccb->pdata[8], "ATA ", 8); |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 658 | ata_id_strcpy((u16 *) &pccb->pdata[16], &tmpid[ATA_ID_PROD], 16); |
| 659 | ata_id_strcpy((u16 *) &pccb->pdata[32], &tmpid[ATA_ID_FW_REV], 4); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 660 | |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 661 | #ifdef DEBUG |
| 662 | ata_dump_id(tmpid); |
| 663 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 664 | return 0; |
| 665 | } |
| 666 | |
| 667 | |
| 668 | /* |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 669 | * SCSI READ10/WRITE10 command operation. |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 670 | */ |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 671 | static int ata_scsiop_read_write(ccb *pccb, u8 is_write) |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 672 | { |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 673 | u32 lba = 0; |
| 674 | u16 blocks = 0; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 675 | u8 fis[20]; |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 676 | u8 *user_buffer = pccb->pdata; |
| 677 | u32 user_buffer_size = pccb->datalen; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 678 | |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 679 | /* Retrieve the base LBA number from the ccb structure. */ |
| 680 | memcpy(&lba, pccb->cmd + 2, sizeof(lba)); |
| 681 | lba = be32_to_cpu(lba); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 682 | |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 683 | /* |
| 684 | * And the number of blocks. |
| 685 | * |
| 686 | * For 10-byte and 16-byte SCSI R/W commands, transfer |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 687 | * length 0 means transfer 0 block of data. |
| 688 | * However, for ATA R/W commands, sector count 0 means |
| 689 | * 256 or 65536 sectors, not 0 sectors as in SCSI. |
| 690 | * |
| 691 | * WARNING: one or two older ATA drives treat 0 as 0... |
| 692 | */ |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 693 | blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]); |
| 694 | |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 695 | debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n", |
| 696 | is_write ? "write" : "read", (unsigned)lba, blocks); |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 697 | |
| 698 | /* Preset the FIS */ |
Taylor Hutt | c873111 | 2012-10-29 05:23:55 +0000 | [diff] [blame] | 699 | memset(fis, 0, sizeof(fis)); |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 700 | fis[0] = 0x27; /* Host to device FIS. */ |
| 701 | fis[1] = 1 << 7; /* Command FIS. */ |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 702 | /* Command byte (read/write). */ |
Walter Murphy | fe1f808 | 2012-10-29 05:24:03 +0000 | [diff] [blame] | 703 | fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 704 | |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 705 | while (blocks) { |
| 706 | u16 now_blocks; /* number of blocks per iteration */ |
| 707 | u32 transfer_size; /* number of bytes per iteration */ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 708 | |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 709 | now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 710 | |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 711 | transfer_size = ATA_SECT_SIZE * now_blocks; |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 712 | if (transfer_size > user_buffer_size) { |
| 713 | printf("scsi_ahci: Error: buffer too small.\n"); |
| 714 | return -EIO; |
| 715 | } |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 716 | |
Walter Murphy | fe1f808 | 2012-10-29 05:24:03 +0000 | [diff] [blame] | 717 | /* LBA48 SATA command but only use 32bit address range within |
| 718 | * that. The next smaller command range (28bit) is too small. |
| 719 | */ |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 720 | fis[4] = (lba >> 0) & 0xff; |
| 721 | fis[5] = (lba >> 8) & 0xff; |
| 722 | fis[6] = (lba >> 16) & 0xff; |
Walter Murphy | fe1f808 | 2012-10-29 05:24:03 +0000 | [diff] [blame] | 723 | fis[7] = 1 << 6; /* device reg: set LBA mode */ |
| 724 | fis[8] = ((lba >> 24) & 0xff); |
| 725 | fis[3] = 0xe0; /* features */ |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 726 | |
| 727 | /* Block (sector) count */ |
| 728 | fis[12] = (now_blocks >> 0) & 0xff; |
| 729 | fis[13] = (now_blocks >> 8) & 0xff; |
| 730 | |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 731 | /* Read/Write from ahci */ |
| 732 | if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis), |
| 733 | user_buffer, user_buffer_size, |
| 734 | is_write)) { |
| 735 | debug("scsi_ahci: SCSI %s10 command failure.\n", |
| 736 | is_write ? "WRITE" : "READ"); |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 737 | return -EIO; |
| 738 | } |
Marc Jones | 766b16f | 2012-10-29 05:24:02 +0000 | [diff] [blame] | 739 | |
| 740 | /* If this transaction is a write, do a following flush. |
| 741 | * Writes in u-boot are so rare, and the logic to know when is |
| 742 | * the last write and do a flush only there is sufficiently |
| 743 | * difficult. Just do a flush after every write. This incurs, |
| 744 | * usually, one extra flush when the rare writes do happen. |
| 745 | */ |
| 746 | if (is_write) { |
| 747 | if (-EIO == ata_io_flush(pccb->target)) |
| 748 | return -EIO; |
| 749 | } |
Vadim Bendebury | 284231e | 2012-10-29 05:23:44 +0000 | [diff] [blame] | 750 | user_buffer += transfer_size; |
| 751 | user_buffer_size -= transfer_size; |
| 752 | blocks -= now_blocks; |
| 753 | lba += now_blocks; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 754 | } |
| 755 | |
| 756 | return 0; |
| 757 | } |
| 758 | |
| 759 | |
| 760 | /* |
| 761 | * SCSI READ CAPACITY10 command operation. |
| 762 | */ |
| 763 | static int ata_scsiop_read_capacity10(ccb *pccb) |
| 764 | { |
Kumar Gala | cb6d0b7 | 2009-07-13 09:24:00 -0500 | [diff] [blame] | 765 | u32 cap; |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 766 | u64 cap64; |
Gabe Black | 19d1d41 | 2012-10-29 05:23:54 +0000 | [diff] [blame] | 767 | u32 block_size; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 768 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 769 | if (!ataid[pccb->target]) { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 770 | printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 771 | "\tNo ATA info!\n" |
| 772 | "\tPlease run SCSI commmand INQUIRY firstly!\n"); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 773 | return -EPERM; |
| 774 | } |
| 775 | |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 776 | cap64 = ata_id_n_sectors(ataid[pccb->target]); |
| 777 | if (cap64 > 0x100000000ULL) |
| 778 | cap64 = 0xffffffff; |
Gabe Black | 19d1d41 | 2012-10-29 05:23:54 +0000 | [diff] [blame] | 779 | |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 780 | cap = cpu_to_be32(cap64); |
Kumar Gala | cb6d0b7 | 2009-07-13 09:24:00 -0500 | [diff] [blame] | 781 | memcpy(pccb->pdata, &cap, sizeof(cap)); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 782 | |
Gabe Black | 19d1d41 | 2012-10-29 05:23:54 +0000 | [diff] [blame] | 783 | block_size = cpu_to_be32((u32)512); |
| 784 | memcpy(&pccb->pdata[4], &block_size, 4); |
| 785 | |
| 786 | return 0; |
| 787 | } |
| 788 | |
| 789 | |
| 790 | /* |
| 791 | * SCSI READ CAPACITY16 command operation. |
| 792 | */ |
| 793 | static int ata_scsiop_read_capacity16(ccb *pccb) |
| 794 | { |
| 795 | u64 cap; |
| 796 | u64 block_size; |
| 797 | |
| 798 | if (!ataid[pccb->target]) { |
| 799 | printf("scsi_ahci: SCSI READ CAPACITY16 command failure. " |
| 800 | "\tNo ATA info!\n" |
| 801 | "\tPlease run SCSI commmand INQUIRY firstly!\n"); |
| 802 | return -EPERM; |
| 803 | } |
| 804 | |
Rob Herring | 344ca0b | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 805 | cap = ata_id_n_sectors(ataid[pccb->target]); |
Gabe Black | 19d1d41 | 2012-10-29 05:23:54 +0000 | [diff] [blame] | 806 | cap = cpu_to_be64(cap); |
| 807 | memcpy(pccb->pdata, &cap, sizeof(cap)); |
| 808 | |
| 809 | block_size = cpu_to_be64((u64)512); |
| 810 | memcpy(&pccb->pdata[8], &block_size, 8); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 811 | |
| 812 | return 0; |
| 813 | } |
| 814 | |
| 815 | |
| 816 | /* |
| 817 | * SCSI TEST UNIT READY command operation. |
| 818 | */ |
| 819 | static int ata_scsiop_test_unit_ready(ccb *pccb) |
| 820 | { |
| 821 | return (ataid[pccb->target]) ? 0 : -EPERM; |
| 822 | } |
| 823 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 824 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 825 | int scsi_exec(ccb *pccb) |
| 826 | { |
| 827 | int ret; |
| 828 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 829 | switch (pccb->cmd[0]) { |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 830 | case SCSI_READ10: |
Hung-Te Lin | b7a21b7 | 2012-10-29 05:23:53 +0000 | [diff] [blame] | 831 | ret = ata_scsiop_read_write(pccb, 0); |
| 832 | break; |
| 833 | case SCSI_WRITE10: |
| 834 | ret = ata_scsiop_read_write(pccb, 1); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 835 | break; |
Gabe Black | 19d1d41 | 2012-10-29 05:23:54 +0000 | [diff] [blame] | 836 | case SCSI_RD_CAPAC10: |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 837 | ret = ata_scsiop_read_capacity10(pccb); |
| 838 | break; |
Gabe Black | 19d1d41 | 2012-10-29 05:23:54 +0000 | [diff] [blame] | 839 | case SCSI_RD_CAPAC16: |
| 840 | ret = ata_scsiop_read_capacity16(pccb); |
| 841 | break; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 842 | case SCSI_TST_U_RDY: |
| 843 | ret = ata_scsiop_test_unit_ready(pccb); |
| 844 | break; |
| 845 | case SCSI_INQUIRY: |
| 846 | ret = ata_scsiop_inquiry(pccb); |
| 847 | break; |
| 848 | default: |
| 849 | printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); |
York Sun | 472d546 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 850 | return false; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 851 | } |
| 852 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 853 | if (ret) { |
| 854 | debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); |
York Sun | 472d546 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 855 | return false; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 856 | } |
York Sun | 472d546 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 857 | return true; |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 858 | |
| 859 | } |
| 860 | |
| 861 | |
| 862 | void scsi_low_level_init(int busdevfunc) |
| 863 | { |
| 864 | int i; |
| 865 | u32 linkmap; |
| 866 | |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 867 | #ifndef CONFIG_SCSI_AHCI_PLAT |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 868 | ahci_init_one(busdevfunc); |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 869 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 870 | |
| 871 | linkmap = probe_ent->link_port_map; |
| 872 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 873 | for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 874 | if (((linkmap >> i) & 0x01)) { |
| 875 | if (ahci_port_start((u8) i)) { |
| 876 | printf("Can not start port %d\n", i); |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 877 | continue; |
| 878 | } |
Gabe Black | e81058c | 2012-10-29 05:23:52 +0000 | [diff] [blame] | 879 | #ifdef CONFIG_AHCI_SETFEATURES_XFER |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 880 | ahci_set_feature((u8) i); |
Gabe Black | e81058c | 2012-10-29 05:23:52 +0000 | [diff] [blame] | 881 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 882 | } |
| 883 | } |
| 884 | } |
| 885 | |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 886 | #ifdef CONFIG_SCSI_AHCI_PLAT |
| 887 | int ahci_init(u32 base) |
| 888 | { |
| 889 | int i, rc = 0; |
| 890 | u32 linkmap; |
| 891 | |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 892 | probe_ent = malloc(sizeof(struct ahci_probe_ent)); |
Roger Quadros | d73763a | 2013-11-11 16:56:37 +0200 | [diff] [blame] | 893 | if (!probe_ent) { |
| 894 | printf("%s: No memory for probe_ent\n", __func__); |
| 895 | return -ENOMEM; |
| 896 | } |
| 897 | |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 898 | memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); |
| 899 | |
| 900 | probe_ent->host_flags = ATA_FLAG_SATA |
| 901 | | ATA_FLAG_NO_LEGACY |
| 902 | | ATA_FLAG_MMIO |
| 903 | | ATA_FLAG_PIO_DMA |
| 904 | | ATA_FLAG_NO_ATAPI; |
| 905 | probe_ent->pio_mask = 0x1f; |
| 906 | probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ |
| 907 | |
| 908 | probe_ent->mmio_base = base; |
| 909 | |
| 910 | /* initialize adapter */ |
| 911 | rc = ahci_host_init(probe_ent); |
| 912 | if (rc) |
| 913 | goto err_out; |
| 914 | |
| 915 | ahci_print_info(probe_ent); |
| 916 | |
| 917 | linkmap = probe_ent->link_port_map; |
| 918 | |
| 919 | for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { |
| 920 | if (((linkmap >> i) & 0x01)) { |
| 921 | if (ahci_port_start((u8) i)) { |
| 922 | printf("Can not start port %d\n", i); |
| 923 | continue; |
| 924 | } |
Gabe Black | e81058c | 2012-10-29 05:23:52 +0000 | [diff] [blame] | 925 | #ifdef CONFIG_AHCI_SETFEATURES_XFER |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 926 | ahci_set_feature((u8) i); |
Gabe Black | e81058c | 2012-10-29 05:23:52 +0000 | [diff] [blame] | 927 | #endif |
Rob Herring | 942e314 | 2011-07-06 16:13:36 +0000 | [diff] [blame] | 928 | } |
| 929 | } |
| 930 | err_out: |
| 931 | return rc; |
| 932 | } |
| 933 | #endif |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 934 | |
Marc Jones | 766b16f | 2012-10-29 05:24:02 +0000 | [diff] [blame] | 935 | /* |
| 936 | * In the general case of generic rotating media it makes sense to have a |
| 937 | * flush capability. It probably even makes sense in the case of SSDs because |
| 938 | * one cannot always know for sure what kind of internal cache/flush mechanism |
| 939 | * is embodied therein. At first it was planned to invoke this after the last |
| 940 | * write to disk and before rebooting. In practice, knowing, a priori, which |
| 941 | * is the last write is difficult. Because writing to the disk in u-boot is |
| 942 | * very rare, this flush command will be invoked after every block write. |
| 943 | */ |
| 944 | static int ata_io_flush(u8 port) |
| 945 | { |
| 946 | u8 fis[20]; |
| 947 | struct ahci_ioports *pp = &(probe_ent->port[port]); |
| 948 | volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; |
| 949 | u32 cmd_fis_len = 5; /* five dwords */ |
| 950 | |
| 951 | /* Preset the FIS */ |
| 952 | memset(fis, 0, 20); |
| 953 | fis[0] = 0x27; /* Host to device FIS. */ |
| 954 | fis[1] = 1 << 7; /* Command FIS. */ |
Walter Murphy | fe1f808 | 2012-10-29 05:24:03 +0000 | [diff] [blame] | 955 | fis[2] = ATA_CMD_FLUSH_EXT; |
Marc Jones | 766b16f | 2012-10-29 05:24:02 +0000 | [diff] [blame] | 956 | |
| 957 | memcpy((unsigned char *)pp->cmd_tbl, fis, 20); |
| 958 | ahci_fill_cmd_slot(pp, cmd_fis_len); |
| 959 | writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); |
| 960 | |
| 961 | if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, |
| 962 | WAIT_MS_FLUSH, 0x1)) { |
| 963 | debug("scsi_ahci: flush command timeout on port %d.\n", port); |
| 964 | return -EIO; |
| 965 | } |
| 966 | |
| 967 | return 0; |
| 968 | } |
| 969 | |
| 970 | |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 971 | void scsi_bus_reset(void) |
| 972 | { |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 973 | /*Not implement*/ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 974 | } |
| 975 | |
| 976 | |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 977 | void scsi_print_error(ccb * pccb) |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 978 | { |
Jon Loeliger | 4a7cc0f | 2006-08-23 11:04:43 -0500 | [diff] [blame] | 979 | /*The ahci error info can be read in the ahci driver*/ |
Jin Zhengxiong | 4782ac8 | 2006-08-23 19:10:44 +0800 | [diff] [blame] | 980 | } |