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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ilya Yanok0b23fb32009-07-21 19:32:21 +04002/*
3 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
4 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
5 * (C) Copyright 2008 Armadeus Systems nc
6 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
Ilya Yanok0b23fb32009-07-21 19:32:21 +04008 */
9
10#include <common.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070011#include <cpu_func.h>
Jagan Teki60752ca2016-12-06 00:00:49 +010012#include <dm.h>
Simon Glass9fb625c2019-08-01 09:46:51 -060013#include <env.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060014#include <log.h>
Ilya Yanok0b23fb32009-07-21 19:32:21 +040015#include <malloc.h>
Simon Glasscf92e052015-09-02 17:24:58 -060016#include <memalign.h>
Jagan Teki567173a2016-12-06 00:00:50 +010017#include <miiphy.h>
Ilya Yanok0b23fb32009-07-21 19:32:21 +040018#include <net.h>
Jeroen Hofstee84f64c82014-10-08 22:57:40 +020019#include <netdev.h>
Simon Glass90526e92020-05-10 11:39:56 -060020#include <asm/cache.h>
Simon Glass401d1c42020-10-30 21:38:53 -060021#include <asm/global_data.h>
Simon Glassc05ed002020-05-10 11:40:11 -060022#include <linux/delay.h>
Martin Fuzzeyad8c43c2018-10-04 19:59:20 +020023#include <power/regulator.h>
Ilya Yanok0b23fb32009-07-21 19:32:21 +040024
Jagan Teki567173a2016-12-06 00:00:50 +010025#include <asm/io.h>
26#include <linux/errno.h>
27#include <linux/compiler.h>
28
Ilya Yanok0b23fb32009-07-21 19:32:21 +040029#include <asm/arch/clock.h>
30#include <asm/arch/imx-regs.h>
Stefano Babic552a8482017-06-29 10:16:06 +020031#include <asm/mach-imx/sys_proto.h>
Michael Trimarchiefd0b792018-06-17 15:22:39 +020032#include <asm-generic/gpio.h>
33
34#include "fec_mxc.h"
Ye Li6a895d02020-05-03 22:41:15 +080035#include <eth_phy.h>
Ilya Yanok0b23fb32009-07-21 19:32:21 +040036
37DECLARE_GLOBAL_DATA_PTR;
38
Marek Vasutbc1ce152012-08-29 03:49:49 +000039/*
40 * Timeout the transfer after 5 mS. This is usually a bit more, since
41 * the code in the tightloops this timeout is used in adds some overhead.
42 */
43#define FEC_XFER_TIMEOUT 5000
44
Fabio Estevamdb5b7f52014-08-25 13:34:16 -030045/*
46 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
47 * 64-byte alignment in the DMA RX FEC buffer.
48 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
49 * satisfies the alignment on other SoCs (32-bytes)
50 */
51#define FEC_DMA_RX_MINALIGN 64
52
Ilya Yanok0b23fb32009-07-21 19:32:21 +040053#ifndef CONFIG_MII
54#error "CONFIG_MII has to be defined!"
55#endif
56
Eric Nelson5c1ad3e2012-03-15 18:33:25 +000057#ifndef CONFIG_FEC_XCV_TYPE
58#define CONFIG_FEC_XCV_TYPE MII100
Marek Vasut392b8502011-09-11 18:05:33 +000059#endif
60
Marek Vasutbe7e87e2011-11-08 23:18:10 +000061/*
62 * The i.MX28 operates with packets in big endian. We need to swap them before
63 * sending and after receiving.
64 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +000065#ifdef CONFIG_MX28
66#define CONFIG_FEC_MXC_SWAP_PACKET
67#endif
68
69#define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
70
71/* Check various alignment issues at compile time */
72#if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
73#error "ARCH_DMA_MINALIGN must be multiple of 16!"
74#endif
75
76#if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
77 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
78#error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
Marek Vasutbe7e87e2011-11-08 23:18:10 +000079#endif
80
Ilya Yanok0b23fb32009-07-21 19:32:21 +040081#undef DEBUG
82
Eric Nelson5c1ad3e2012-03-15 18:33:25 +000083#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Marek Vasutbe7e87e2011-11-08 23:18:10 +000084static void swap_packet(uint32_t *packet, int length)
85{
86 int i;
87
88 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
89 packet[i] = __swab32(packet[i]);
90}
91#endif
92
Jagan Teki567173a2016-12-06 00:00:50 +010093/* MII-interface related functions */
94static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
95 uint8_t regaddr)
Ilya Yanok0b23fb32009-07-21 19:32:21 +040096{
Ilya Yanok0b23fb32009-07-21 19:32:21 +040097 uint32_t reg; /* convenient holder for the PHY register */
98 uint32_t phy; /* convenient holder for the PHY */
99 uint32_t start;
Troy Kisky13947f42012-02-07 14:08:47 +0000100 int val;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400101
102 /*
103 * reading from any PHY's register is done by properly
104 * programming the FEC's MII data register.
105 */
Marek Vasutd133b882011-09-11 18:05:34 +0000106 writel(FEC_IEVENT_MII, &eth->ievent);
Jagan Teki567173a2016-12-06 00:00:50 +0100107 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
108 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400109
110 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
Marek Vasutd133b882011-09-11 18:05:34 +0000111 phy | reg, &eth->mii_data);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400112
Jagan Teki567173a2016-12-06 00:00:50 +0100113 /* wait for the related interrupt */
Graeme Russa60d1e52011-07-15 23:31:37 +0000114 start = get_timer(0);
Marek Vasutd133b882011-09-11 18:05:34 +0000115 while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400116 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
117 printf("Read MDIO failed...\n");
118 return -1;
119 }
120 }
121
Jagan Teki567173a2016-12-06 00:00:50 +0100122 /* clear mii interrupt bit */
Marek Vasutd133b882011-09-11 18:05:34 +0000123 writel(FEC_IEVENT_MII, &eth->ievent);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400124
Jagan Teki567173a2016-12-06 00:00:50 +0100125 /* it's now safe to read the PHY's register */
Troy Kisky13947f42012-02-07 14:08:47 +0000126 val = (unsigned short)readl(&eth->mii_data);
Jagan Teki567173a2016-12-06 00:00:50 +0100127 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
128 regaddr, val);
Troy Kisky13947f42012-02-07 14:08:47 +0000129 return val;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400130}
131
Peng Fan673f6592019-10-25 09:48:02 +0000132#ifndef imx_get_fecclk
133u32 __weak imx_get_fecclk(void)
134{
135 return 0;
136}
137#endif
138
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +0200139static int fec_get_clk_rate(void *udev, int idx)
140{
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +0200141 struct fec_priv *fec;
142 struct udevice *dev;
143 int ret;
144
Peng Fan673f6592019-10-25 09:48:02 +0000145 if (IS_ENABLED(CONFIG_IMX8) ||
146 CONFIG_IS_ENABLED(CLK_CCF)) {
147 dev = udev;
148 if (!dev) {
Tim Harveyb247fa72021-06-30 16:50:03 -0700149 ret = uclass_get_device_by_seq(UCLASS_ETH, idx, &dev);
Peng Fan673f6592019-10-25 09:48:02 +0000150 if (ret < 0) {
151 debug("Can't get FEC udev: %d\n", ret);
152 return ret;
153 }
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +0200154 }
Peng Fan673f6592019-10-25 09:48:02 +0000155
156 fec = dev_get_priv(dev);
157 if (fec)
158 return fec->clk_rate;
159
160 return -EINVAL;
161 } else {
162 return imx_get_fecclk();
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +0200163 }
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +0200164}
165
Troy Kisky575c5cc2012-10-22 16:40:41 +0000166static void fec_mii_setspeed(struct ethernet_regs *eth)
Stefano Babic4294b242010-02-01 14:51:30 +0100167{
168 /*
169 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
170 * and do not drop the Preamble.
Måns Rullgård843a3e52015-12-08 15:38:45 +0000171 *
172 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
173 * MII_SPEED) register that defines the MDIO output hold time. Earlier
174 * versions are RAZ there, so just ignore the difference and write the
175 * register always.
176 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
177 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
178 * output.
179 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
180 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
181 * holdtime cannot result in a value greater than 3.
Stefano Babic4294b242010-02-01 14:51:30 +0100182 */
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +0200183 u32 pclk;
184 u32 speed;
185 u32 hold;
186 int ret;
187
188 ret = fec_get_clk_rate(NULL, 0);
189 if (ret < 0) {
190 printf("Can't find FEC0 clk rate: %d\n", ret);
191 return;
192 }
193 pclk = ret;
194 speed = DIV_ROUND_UP(pclk, 5000000);
195 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
196
Markus Niebel6ba45cc2014-02-05 10:54:11 +0100197#ifdef FEC_QUIRK_ENET_MAC
198 speed--;
199#endif
Måns Rullgård843a3e52015-12-08 15:38:45 +0000200 writel(speed << 1 | hold << 8, &eth->mii_speed);
Troy Kisky575c5cc2012-10-22 16:40:41 +0000201 debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));
Stefano Babic4294b242010-02-01 14:51:30 +0100202}
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400203
Jagan Teki567173a2016-12-06 00:00:50 +0100204static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
205 uint8_t regaddr, uint16_t data)
Troy Kisky13947f42012-02-07 14:08:47 +0000206{
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400207 uint32_t reg; /* convenient holder for the PHY register */
208 uint32_t phy; /* convenient holder for the PHY */
209 uint32_t start;
210
Jagan Teki567173a2016-12-06 00:00:50 +0100211 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
212 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400213
214 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
Marek Vasutd133b882011-09-11 18:05:34 +0000215 FEC_MII_DATA_TA | phy | reg | data, &eth->mii_data);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400216
Jagan Teki567173a2016-12-06 00:00:50 +0100217 /* wait for the MII interrupt */
Graeme Russa60d1e52011-07-15 23:31:37 +0000218 start = get_timer(0);
Marek Vasutd133b882011-09-11 18:05:34 +0000219 while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400220 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
221 printf("Write MDIO failed...\n");
222 return -1;
223 }
224 }
225
Jagan Teki567173a2016-12-06 00:00:50 +0100226 /* clear MII interrupt bit */
Marek Vasutd133b882011-09-11 18:05:34 +0000227 writel(FEC_IEVENT_MII, &eth->ievent);
Jagan Teki567173a2016-12-06 00:00:50 +0100228 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
229 regaddr, data);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400230
231 return 0;
232}
233
Jagan Teki567173a2016-12-06 00:00:50 +0100234static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
235 int regaddr)
Troy Kisky13947f42012-02-07 14:08:47 +0000236{
Jagan Teki567173a2016-12-06 00:00:50 +0100237 return fec_mdio_read(bus->priv, phyaddr, regaddr);
Troy Kisky13947f42012-02-07 14:08:47 +0000238}
239
Jagan Teki567173a2016-12-06 00:00:50 +0100240static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
241 int regaddr, u16 data)
Troy Kisky13947f42012-02-07 14:08:47 +0000242{
Jagan Teki567173a2016-12-06 00:00:50 +0100243 return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
Troy Kisky13947f42012-02-07 14:08:47 +0000244}
245
246#ifndef CONFIG_PHYLIB
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400247static int miiphy_restart_aneg(struct eth_device *dev)
248{
Stefano Babicb774fe92012-02-22 00:24:35 +0000249 int ret = 0;
250#if !defined(CONFIG_FEC_MXC_NO_ANEG)
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200251 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Troy Kisky13947f42012-02-07 14:08:47 +0000252 struct ethernet_regs *eth = fec->bus->priv;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200253
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400254 /*
255 * Wake up from sleep if necessary
256 * Reset PHY, then delay 300ns
257 */
John Rigbycb17b922010-01-25 23:12:55 -0700258#ifdef CONFIG_MX27
Troy Kisky13947f42012-02-07 14:08:47 +0000259 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
John Rigbycb17b922010-01-25 23:12:55 -0700260#endif
Troy Kisky13947f42012-02-07 14:08:47 +0000261 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400262 udelay(1000);
263
Jagan Teki567173a2016-12-06 00:00:50 +0100264 /* Set the auto-negotiation advertisement register bits */
Troy Kisky13947f42012-02-07 14:08:47 +0000265 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
Jagan Teki567173a2016-12-06 00:00:50 +0100266 LPA_100FULL | LPA_100HALF | LPA_10FULL |
267 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
Troy Kisky13947f42012-02-07 14:08:47 +0000268 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
Jagan Teki567173a2016-12-06 00:00:50 +0100269 BMCR_ANENABLE | BMCR_ANRESTART);
Marek Vasut2e5f4422011-09-11 18:05:36 +0000270
271 if (fec->mii_postcall)
272 ret = fec->mii_postcall(fec->phy_id);
273
Stefano Babicb774fe92012-02-22 00:24:35 +0000274#endif
Marek Vasut2e5f4422011-09-11 18:05:36 +0000275 return ret;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400276}
277
Hannes Schmelzer07507012016-06-22 12:07:14 +0200278#ifndef CONFIG_FEC_FIXED_SPEED
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400279static int miiphy_wait_aneg(struct eth_device *dev)
280{
281 uint32_t start;
Troy Kisky13947f42012-02-07 14:08:47 +0000282 int status;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200283 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Troy Kisky13947f42012-02-07 14:08:47 +0000284 struct ethernet_regs *eth = fec->bus->priv;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400285
Jagan Teki567173a2016-12-06 00:00:50 +0100286 /* Wait for AN completion */
Graeme Russa60d1e52011-07-15 23:31:37 +0000287 start = get_timer(0);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400288 do {
289 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
290 printf("%s: Autonegotiation timeout\n", dev->name);
291 return -1;
292 }
293
Troy Kisky13947f42012-02-07 14:08:47 +0000294 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
295 if (status < 0) {
296 printf("%s: Autonegotiation failed. status: %d\n",
Jagan Teki567173a2016-12-06 00:00:50 +0100297 dev->name, status);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400298 return -1;
299 }
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500300 } while (!(status & BMSR_LSTATUS));
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400301
302 return 0;
303}
Hannes Schmelzer07507012016-06-22 12:07:14 +0200304#endif /* CONFIG_FEC_FIXED_SPEED */
Troy Kisky13947f42012-02-07 14:08:47 +0000305#endif
306
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400307static int fec_rx_task_enable(struct fec_priv *fec)
308{
Marek Vasutc0b5a3b2012-08-29 03:49:51 +0000309 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400310 return 0;
311}
312
313static int fec_rx_task_disable(struct fec_priv *fec)
314{
315 return 0;
316}
317
318static int fec_tx_task_enable(struct fec_priv *fec)
319{
Marek Vasutc0b5a3b2012-08-29 03:49:51 +0000320 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400321 return 0;
322}
323
324static int fec_tx_task_disable(struct fec_priv *fec)
325{
326 return 0;
327}
328
329/**
330 * Initialize receive task's buffer descriptors
331 * @param[in] fec all we know about the device yet
332 * @param[in] count receive buffer count to be allocated
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000333 * @param[in] dsize desired size of each receive buffer
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400334 * @return 0 on success
335 *
Marek Vasut79e5f272013-10-12 20:36:25 +0200336 * Init all RX descriptors to default values.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400337 */
Marek Vasut79e5f272013-10-12 20:36:25 +0200338static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400339{
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000340 uint32_t size;
Ye Lif24e4822018-01-10 13:20:44 +0800341 ulong data;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000342 int i;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400343
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400344 /*
Marek Vasut79e5f272013-10-12 20:36:25 +0200345 * Reload the RX descriptors with default values and wipe
346 * the RX buffers.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400347 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000348 size = roundup(dsize, ARCH_DMA_MINALIGN);
349 for (i = 0; i < count; i++) {
Ye Lif24e4822018-01-10 13:20:44 +0800350 data = fec->rbd_base[i].data_pointer;
351 memset((void *)data, 0, dsize);
352 flush_dcache_range(data, data + size);
Marek Vasut79e5f272013-10-12 20:36:25 +0200353
354 fec->rbd_base[i].status = FEC_RBD_EMPTY;
355 fec->rbd_base[i].data_length = 0;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000356 }
357
358 /* Mark the last RBD to close the ring. */
Marek Vasut79e5f272013-10-12 20:36:25 +0200359 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400360 fec->rbd_index = 0;
361
Ye Lif24e4822018-01-10 13:20:44 +0800362 flush_dcache_range((ulong)fec->rbd_base,
363 (ulong)fec->rbd_base + size);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400364}
365
366/**
367 * Initialize transmit task's buffer descriptors
368 * @param[in] fec all we know about the device yet
369 *
370 * Transmit buffers are created externally. We only have to init the BDs here.\n
371 * Note: There is a race condition in the hardware. When only one BD is in
372 * use it must be marked with the WRAP bit to use it for every transmitt.
373 * This bit in combination with the READY bit results into double transmit
374 * of each data buffer. It seems the state machine checks READY earlier then
375 * resetting it after the first transfer.
376 * Using two BDs solves this issue.
377 */
378static void fec_tbd_init(struct fec_priv *fec)
379{
Ye Lif24e4822018-01-10 13:20:44 +0800380 ulong addr = (ulong)fec->tbd_base;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000381 unsigned size = roundup(2 * sizeof(struct fec_bd),
382 ARCH_DMA_MINALIGN);
Marek Vasut79e5f272013-10-12 20:36:25 +0200383
384 memset(fec->tbd_base, 0, size);
385 fec->tbd_base[0].status = 0;
386 fec->tbd_base[1].status = FEC_TBD_WRAP;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400387 fec->tbd_index = 0;
Marek Vasut79e5f272013-10-12 20:36:25 +0200388 flush_dcache_range(addr, addr + size);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400389}
390
391/**
392 * Mark the given read buffer descriptor as free
393 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
Jagan Teki567173a2016-12-06 00:00:50 +0100394 * @param[in] prbd buffer descriptor to mark free again
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400395 */
Jagan Teki567173a2016-12-06 00:00:50 +0100396static void fec_rbd_clean(int last, struct fec_bd *prbd)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400397{
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000398 unsigned short flags = FEC_RBD_EMPTY;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400399 if (last)
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000400 flags |= FEC_RBD_WRAP;
Jagan Teki567173a2016-12-06 00:00:50 +0100401 writew(flags, &prbd->status);
402 writew(0, &prbd->data_length);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400403}
404
Jagan Tekif54183e2016-12-06 00:00:48 +0100405static int fec_get_hwaddr(int dev_id, unsigned char *mac)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400406{
Fabio Estevambe252b62011-12-20 05:46:31 +0000407 imx_get_mac_from_fuse(dev_id, mac);
Joe Hershberger0adb5b72015-04-08 01:41:04 -0500408 return !is_valid_ethaddr(mac);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400409}
410
Jagan Teki60752ca2016-12-06 00:00:49 +0100411#ifdef CONFIG_DM_ETH
412static int fecmxc_set_hwaddr(struct udevice *dev)
413#else
Stefano Babic4294b242010-02-01 14:51:30 +0100414static int fec_set_hwaddr(struct eth_device *dev)
Jagan Teki60752ca2016-12-06 00:00:49 +0100415#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400416{
Jagan Teki60752ca2016-12-06 00:00:49 +0100417#ifdef CONFIG_DM_ETH
418 struct fec_priv *fec = dev_get_priv(dev);
Simon Glassc69cda22020-12-03 16:55:20 -0700419 struct eth_pdata *pdata = dev_get_plat(dev);
Jagan Teki60752ca2016-12-06 00:00:49 +0100420 uchar *mac = pdata->enetaddr;
421#else
Stefano Babic4294b242010-02-01 14:51:30 +0100422 uchar *mac = dev->enetaddr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400423 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki60752ca2016-12-06 00:00:49 +0100424#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400425
426 writel(0, &fec->eth->iaddr1);
427 writel(0, &fec->eth->iaddr2);
428 writel(0, &fec->eth->gaddr1);
429 writel(0, &fec->eth->gaddr2);
430
Jagan Teki567173a2016-12-06 00:00:50 +0100431 /* Set physical address */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400432 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
Jagan Teki567173a2016-12-06 00:00:50 +0100433 &fec->eth->paddr1);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400434 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
435
436 return 0;
437}
438
Jagan Teki567173a2016-12-06 00:00:50 +0100439/* Do initial configuration of the FEC registers */
Marek Vasuta5990b22012-05-01 11:09:41 +0000440static void fec_reg_setup(struct fec_priv *fec)
441{
442 uint32_t rcntrl;
443
Jagan Teki567173a2016-12-06 00:00:50 +0100444 /* Set interrupt mask register */
Marek Vasuta5990b22012-05-01 11:09:41 +0000445 writel(0x00000000, &fec->eth->imask);
446
Jagan Teki567173a2016-12-06 00:00:50 +0100447 /* Clear FEC-Lite interrupt event register(IEVENT) */
Marek Vasuta5990b22012-05-01 11:09:41 +0000448 writel(0xffffffff, &fec->eth->ievent);
449
Jagan Teki567173a2016-12-06 00:00:50 +0100450 /* Set FEC-Lite receive control register(R_CNTRL): */
Marek Vasuta5990b22012-05-01 11:09:41 +0000451
452 /* Start with frame length = 1518, common for all modes. */
453 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
benoit.thebaudeau@advans9d2d9242012-07-19 02:12:46 +0000454 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
455 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
456 if (fec->xcv_type == RGMII)
Marek Vasuta5990b22012-05-01 11:09:41 +0000457 rcntrl |= FEC_RCNTRL_RGMII;
458 else if (fec->xcv_type == RMII)
459 rcntrl |= FEC_RCNTRL_RMII;
Marek Vasuta5990b22012-05-01 11:09:41 +0000460
Tim Harvey87550a82021-06-30 16:50:06 -0700461 if (fec->promisc)
462 rcntrl |= 0x8;
463
Marek Vasuta5990b22012-05-01 11:09:41 +0000464 writel(rcntrl, &fec->eth->r_cntrl);
465}
466
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400467/**
468 * Start the FEC engine
469 * @param[in] dev Our device to handle
470 */
Jagan Teki60752ca2016-12-06 00:00:49 +0100471#ifdef CONFIG_DM_ETH
472static int fec_open(struct udevice *dev)
473#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400474static int fec_open(struct eth_device *edev)
Jagan Teki60752ca2016-12-06 00:00:49 +0100475#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400476{
Jagan Teki60752ca2016-12-06 00:00:49 +0100477#ifdef CONFIG_DM_ETH
478 struct fec_priv *fec = dev_get_priv(dev);
479#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400480 struct fec_priv *fec = (struct fec_priv *)edev->priv;
Jagan Teki60752ca2016-12-06 00:00:49 +0100481#endif
Troy Kisky28774cb2012-02-07 14:08:46 +0000482 int speed;
Ye Lif24e4822018-01-10 13:20:44 +0800483 ulong addr, size;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000484 int i;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400485
486 debug("fec_open: fec_open(dev)\n");
487 /* full-duplex, heartbeat disabled */
488 writel(1 << 2, &fec->eth->x_cntrl);
489 fec->rbd_index = 0;
490
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000491 /* Invalidate all descriptors */
492 for (i = 0; i < FEC_RBD_NUM - 1; i++)
493 fec_rbd_clean(0, &fec->rbd_base[i]);
494 fec_rbd_clean(1, &fec->rbd_base[i]);
495
496 /* Flush the descriptors into RAM */
497 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
498 ARCH_DMA_MINALIGN);
Ye Lif24e4822018-01-10 13:20:44 +0800499 addr = (ulong)fec->rbd_base;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000500 flush_dcache_range(addr, addr + size);
501
Troy Kisky28774cb2012-02-07 14:08:46 +0000502#ifdef FEC_QUIRK_ENET_MAC
Jason Liu2ef2b952011-12-16 05:17:07 +0000503 /* Enable ENET HW endian SWAP */
504 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
Jagan Teki567173a2016-12-06 00:00:50 +0100505 &fec->eth->ecntrl);
Jason Liu2ef2b952011-12-16 05:17:07 +0000506 /* Enable ENET store and forward mode */
507 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
Jagan Teki567173a2016-12-06 00:00:50 +0100508 &fec->eth->x_wmrk);
Jason Liu2ef2b952011-12-16 05:17:07 +0000509#endif
Jagan Teki567173a2016-12-06 00:00:50 +0100510 /* Enable FEC-Lite controller */
John Rigbycb17b922010-01-25 23:12:55 -0700511 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
Jagan Teki567173a2016-12-06 00:00:50 +0100512 &fec->eth->ecntrl);
513
Philippe Schenkera1a34fa2020-03-11 11:52:58 +0100514#ifdef FEC_ENET_ENABLE_TXC_DELAY
515 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_TXC_DLY,
516 &fec->eth->ecntrl);
517#endif
518
519#ifdef FEC_ENET_ENABLE_RXC_DELAY
520 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RXC_DLY,
521 &fec->eth->ecntrl);
522#endif
523
Tom Rini8ba59602021-09-09 07:54:50 -0400524#if defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
John Rigby740d6ae2010-01-25 23:12:57 -0700525 udelay(100);
John Rigby740d6ae2010-01-25 23:12:57 -0700526
Jagan Teki567173a2016-12-06 00:00:50 +0100527 /* setup the MII gasket for RMII mode */
John Rigby740d6ae2010-01-25 23:12:57 -0700528 /* disable the gasket */
529 writew(0, &fec->eth->miigsk_enr);
530
531 /* wait for the gasket to be disabled */
532 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
533 udelay(2);
534
535 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
536 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
537
538 /* re-enable the gasket */
539 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
540
541 /* wait until MII gasket is ready */
542 int max_loops = 10;
543 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
544 if (--max_loops <= 0) {
545 printf("WAIT for MII Gasket ready timed out\n");
546 break;
547 }
548 }
549#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400550
Troy Kisky13947f42012-02-07 14:08:47 +0000551#ifdef CONFIG_PHYLIB
Troy Kisky4dc27ee2012-10-22 16:40:45 +0000552 {
Troy Kisky13947f42012-02-07 14:08:47 +0000553 /* Start up the PHY */
Timur Tabi11af8d62012-07-09 08:52:43 +0000554 int ret = phy_startup(fec->phydev);
555
556 if (ret) {
557 printf("Could not initialize PHY %s\n",
558 fec->phydev->dev->name);
559 return ret;
560 }
Troy Kisky13947f42012-02-07 14:08:47 +0000561 speed = fec->phydev->speed;
Troy Kisky13947f42012-02-07 14:08:47 +0000562 }
Hannes Schmelzer07507012016-06-22 12:07:14 +0200563#elif CONFIG_FEC_FIXED_SPEED
564 speed = CONFIG_FEC_FIXED_SPEED;
Troy Kisky13947f42012-02-07 14:08:47 +0000565#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400566 miiphy_wait_aneg(edev);
Troy Kisky28774cb2012-02-07 14:08:46 +0000567 speed = miiphy_speed(edev->name, fec->phy_id);
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200568 miiphy_duplex(edev->name, fec->phy_id);
Troy Kisky13947f42012-02-07 14:08:47 +0000569#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400570
Troy Kisky28774cb2012-02-07 14:08:46 +0000571#ifdef FEC_QUIRK_ENET_MAC
572 {
573 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
Alison Wangbcb6e902013-05-27 22:55:43 +0000574 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
Troy Kisky28774cb2012-02-07 14:08:46 +0000575 if (speed == _1000BASET)
576 ecr |= FEC_ECNTRL_SPEED;
577 else if (speed != _100BASET)
578 rcr |= FEC_RCNTRL_RMII_10T;
579 writel(ecr, &fec->eth->ecntrl);
580 writel(rcr, &fec->eth->r_cntrl);
581 }
582#endif
583 debug("%s:Speed=%i\n", __func__, speed);
584
Jagan Teki567173a2016-12-06 00:00:50 +0100585 /* Enable SmartDMA receive task */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400586 fec_rx_task_enable(fec);
587
588 udelay(100000);
589 return 0;
590}
591
Jagan Teki60752ca2016-12-06 00:00:49 +0100592#ifdef CONFIG_DM_ETH
593static int fecmxc_init(struct udevice *dev)
594#else
Masahiro Yamadabb5a2cf2020-06-26 15:13:34 +0900595static int fec_init(struct eth_device *dev, struct bd_info *bd)
Jagan Teki60752ca2016-12-06 00:00:49 +0100596#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400597{
Jagan Teki60752ca2016-12-06 00:00:49 +0100598#ifdef CONFIG_DM_ETH
599 struct fec_priv *fec = dev_get_priv(dev);
600#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400601 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki60752ca2016-12-06 00:00:49 +0100602#endif
Ye Lif24e4822018-01-10 13:20:44 +0800603 u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
604 u8 *i;
605 ulong addr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400606
John Rigbye9319f12010-10-13 14:31:08 -0600607 /* Initialize MAC address */
Jagan Teki60752ca2016-12-06 00:00:49 +0100608#ifdef CONFIG_DM_ETH
609 fecmxc_set_hwaddr(dev);
610#else
John Rigbye9319f12010-10-13 14:31:08 -0600611 fec_set_hwaddr(dev);
Jagan Teki60752ca2016-12-06 00:00:49 +0100612#endif
John Rigbye9319f12010-10-13 14:31:08 -0600613
Jagan Teki567173a2016-12-06 00:00:50 +0100614 /* Setup transmit descriptors, there are two in total. */
Marek Vasut79e5f272013-10-12 20:36:25 +0200615 fec_tbd_init(fec);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400616
Marek Vasut79e5f272013-10-12 20:36:25 +0200617 /* Setup receive descriptors. */
618 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400619
Marek Vasuta5990b22012-05-01 11:09:41 +0000620 fec_reg_setup(fec);
Marek Vasut9eb37702011-09-11 18:05:31 +0000621
benoit.thebaudeau@advansf41471e2012-07-19 02:12:58 +0000622 if (fec->xcv_type != SEVENWIRE)
Troy Kisky575c5cc2012-10-22 16:40:41 +0000623 fec_mii_setspeed(fec->bus->priv);
Marek Vasut9eb37702011-09-11 18:05:31 +0000624
Jagan Teki567173a2016-12-06 00:00:50 +0100625 /* Set Opcode/Pause Duration Register */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400626 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
627 writel(0x2, &fec->eth->x_wmrk);
Jagan Teki567173a2016-12-06 00:00:50 +0100628
629 /* Set multicast address filter */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400630 writel(0x00000000, &fec->eth->gaddr1);
631 writel(0x00000000, &fec->eth->gaddr2);
632
Peng Fan238a53c2018-01-10 13:20:43 +0800633 /* Do not access reserved register */
Peng Fan06918de2021-08-07 16:00:42 +0800634 if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() && !is_imx8ulp()) {
Peng Fanfbecbaa2015-08-12 17:46:51 +0800635 /* clear MIB RAM */
636 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
637 writel(0, i);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400638
Peng Fanfbecbaa2015-08-12 17:46:51 +0800639 /* FIFO receive start register */
640 writel(0x520, &fec->eth->r_fstart);
641 }
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400642
643 /* size and address of each buffer */
644 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
Ye Lif24e4822018-01-10 13:20:44 +0800645
646 addr = (ulong)fec->tbd_base;
647 writel((uint32_t)addr, &fec->eth->etdsr);
648
649 addr = (ulong)fec->rbd_base;
650 writel((uint32_t)addr, &fec->eth->erdsr);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400651
Troy Kisky13947f42012-02-07 14:08:47 +0000652#ifndef CONFIG_PHYLIB
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400653 if (fec->xcv_type != SEVENWIRE)
654 miiphy_restart_aneg(dev);
Troy Kisky13947f42012-02-07 14:08:47 +0000655#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400656 fec_open(dev);
657 return 0;
658}
659
660/**
661 * Halt the FEC engine
662 * @param[in] dev Our device to handle
663 */
Jagan Teki60752ca2016-12-06 00:00:49 +0100664#ifdef CONFIG_DM_ETH
665static void fecmxc_halt(struct udevice *dev)
666#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400667static void fec_halt(struct eth_device *dev)
Jagan Teki60752ca2016-12-06 00:00:49 +0100668#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400669{
Jagan Teki60752ca2016-12-06 00:00:49 +0100670#ifdef CONFIG_DM_ETH
671 struct fec_priv *fec = dev_get_priv(dev);
672#else
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200673 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki60752ca2016-12-06 00:00:49 +0100674#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400675 int counter = 0xffff;
676
Jagan Teki567173a2016-12-06 00:00:50 +0100677 /* issue graceful stop command to the FEC transmitter if necessary */
John Rigbycb17b922010-01-25 23:12:55 -0700678 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
Jagan Teki567173a2016-12-06 00:00:50 +0100679 &fec->eth->x_cntrl);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400680
681 debug("eth_halt: wait for stop regs\n");
Jagan Teki567173a2016-12-06 00:00:50 +0100682 /* wait for graceful stop to register */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400683 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
John Rigbycb17b922010-01-25 23:12:55 -0700684 udelay(1);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400685
Jagan Teki567173a2016-12-06 00:00:50 +0100686 /* Disable SmartDMA tasks */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400687 fec_tx_task_disable(fec);
688 fec_rx_task_disable(fec);
689
690 /*
691 * Disable the Ethernet Controller
692 * Note: this will also reset the BD index counter!
693 */
John Rigby740d6ae2010-01-25 23:12:57 -0700694 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
Jagan Teki567173a2016-12-06 00:00:50 +0100695 &fec->eth->ecntrl);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400696 fec->rbd_index = 0;
697 fec->tbd_index = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400698 debug("eth_halt: done\n");
699}
700
701/**
702 * Transmit one frame
703 * @param[in] dev Our ethernet device to handle
704 * @param[in] packet Pointer to the data to be transmitted
705 * @param[in] length Data count in bytes
706 * @return 0 on success
707 */
Jagan Teki60752ca2016-12-06 00:00:49 +0100708#ifdef CONFIG_DM_ETH
709static int fecmxc_send(struct udevice *dev, void *packet, int length)
710#else
Joe Hershberger442dac42012-05-21 14:45:27 +0000711static int fec_send(struct eth_device *dev, void *packet, int length)
Jagan Teki60752ca2016-12-06 00:00:49 +0100712#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400713{
714 unsigned int status;
Ye Lif24e4822018-01-10 13:20:44 +0800715 u32 size;
716 ulong addr, end;
Marek Vasutbc1ce152012-08-29 03:49:49 +0000717 int timeout = FEC_XFER_TIMEOUT;
718 int ret = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400719
720 /*
721 * This routine transmits one frame. This routine only accepts
722 * 6-byte Ethernet addresses.
723 */
Jagan Teki60752ca2016-12-06 00:00:49 +0100724#ifdef CONFIG_DM_ETH
725 struct fec_priv *fec = dev_get_priv(dev);
726#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400727 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki60752ca2016-12-06 00:00:49 +0100728#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400729
730 /*
731 * Check for valid length of data.
732 */
733 if ((length > 1500) || (length <= 0)) {
Stefano Babic4294b242010-02-01 14:51:30 +0100734 printf("Payload (%d) too large\n", length);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400735 return -1;
736 }
737
738 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000739 * Setup the transmit buffer. We are always using the first buffer for
740 * transmission, the second will be empty and only used to stop the DMA
741 * engine. We also flush the packet to RAM here to avoid cache trouble.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400742 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000743#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Marek Vasutbe7e87e2011-11-08 23:18:10 +0000744 swap_packet((uint32_t *)packet, length);
745#endif
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000746
Ye Lif24e4822018-01-10 13:20:44 +0800747 addr = (ulong)packet;
Marek Vasutefe24d22012-08-26 10:19:21 +0000748 end = roundup(addr + length, ARCH_DMA_MINALIGN);
749 addr &= ~(ARCH_DMA_MINALIGN - 1);
750 flush_dcache_range(addr, end);
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000751
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400752 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
Ye Lif24e4822018-01-10 13:20:44 +0800753 writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000754
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400755 /*
756 * update BD's status now
757 * This block:
758 * - is always the last in a chain (means no chain)
759 * - should transmitt the CRC
760 * - might be the last BD in the list, so the address counter should
761 * wrap (-> keep the WRAP flag)
762 */
763 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
764 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
765 writew(status, &fec->tbd_base[fec->tbd_index].status);
766
767 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000768 * Flush data cache. This code flushes both TX descriptors to RAM.
769 * After this code, the descriptors will be safely in RAM and we
770 * can start DMA.
771 */
772 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
Ye Lif24e4822018-01-10 13:20:44 +0800773 addr = (ulong)fec->tbd_base;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000774 flush_dcache_range(addr, addr + size);
775
776 /*
Marek Vasutab94cd42013-07-12 01:03:04 +0200777 * Below we read the DMA descriptor's last four bytes back from the
778 * DRAM. This is important in order to make sure that all WRITE
779 * operations on the bus that were triggered by previous cache FLUSH
780 * have completed.
781 *
782 * Otherwise, on MX28, it is possible to observe a corruption of the
783 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
784 * for the bus structure of MX28. The scenario is as follows:
785 *
786 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
787 * to DRAM due to flush_dcache_range()
788 * 2) ARM core writes the FEC registers via AHB_ARB2
789 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
790 *
791 * Note that 2) does sometimes finish before 1) due to reordering of
792 * WRITE accesses on the AHB bus, therefore triggering 3) before the
793 * DMA descriptor is fully written into DRAM. This results in occasional
794 * corruption of the DMA descriptor.
795 */
796 readl(addr + size - 4);
797
Jagan Teki567173a2016-12-06 00:00:50 +0100798 /* Enable SmartDMA transmit task */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400799 fec_tx_task_enable(fec);
800
801 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000802 * Wait until frame is sent. On each turn of the wait cycle, we must
803 * invalidate data cache to see what's really in RAM. Also, we need
804 * barrier here.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400805 */
Marek Vasut67449092012-08-29 03:49:50 +0000806 while (--timeout) {
Marek Vasutc0b5a3b2012-08-29 03:49:51 +0000807 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
Marek Vasutbc1ce152012-08-29 03:49:49 +0000808 break;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400809 }
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000810
Fabio Estevamf5992882014-08-25 13:34:17 -0300811 if (!timeout) {
812 ret = -EINVAL;
813 goto out;
814 }
815
816 /*
817 * The TDAR bit is cleared when the descriptors are all out from TX
818 * but on mx6solox we noticed that the READY bit is still not cleared
819 * right after TDAR.
820 * These are two distinct signals, and in IC simulation, we found that
821 * TDAR always gets cleared prior than the READY bit of last BD becomes
822 * cleared.
823 * In mx6solox, we use a later version of FEC IP. It looks like that
824 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
825 * version.
826 *
827 * Fix this by polling the READY bit of BD after the TDAR polling,
828 * which covers the mx6solox case and does not harm the other SoCs.
829 */
830 timeout = FEC_XFER_TIMEOUT;
831 while (--timeout) {
832 invalidate_dcache_range(addr, addr + size);
833 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
834 FEC_TBD_READY))
835 break;
836 }
837
Marek Vasut67449092012-08-29 03:49:50 +0000838 if (!timeout)
839 ret = -EINVAL;
840
Fabio Estevamf5992882014-08-25 13:34:17 -0300841out:
Marek Vasut67449092012-08-29 03:49:50 +0000842 debug("fec_send: status 0x%x index %d ret %i\n",
Jagan Teki567173a2016-12-06 00:00:50 +0100843 readw(&fec->tbd_base[fec->tbd_index].status),
844 fec->tbd_index, ret);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400845 /* for next transmission use the other buffer */
846 if (fec->tbd_index)
847 fec->tbd_index = 0;
848 else
849 fec->tbd_index = 1;
850
Marek Vasutbc1ce152012-08-29 03:49:49 +0000851 return ret;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400852}
853
854/**
855 * Pull one frame from the card
856 * @param[in] dev Our ethernet device to handle
857 * @return Length of packet read
858 */
Jagan Teki60752ca2016-12-06 00:00:49 +0100859#ifdef CONFIG_DM_ETH
860static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
861#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400862static int fec_recv(struct eth_device *dev)
Jagan Teki60752ca2016-12-06 00:00:49 +0100863#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400864{
Jagan Teki60752ca2016-12-06 00:00:49 +0100865#ifdef CONFIG_DM_ETH
866 struct fec_priv *fec = dev_get_priv(dev);
867#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400868 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki60752ca2016-12-06 00:00:49 +0100869#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400870 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
871 unsigned long ievent;
872 int frame_length, len = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400873 uint16_t bd_status;
Ye Lif24e4822018-01-10 13:20:44 +0800874 ulong addr, size, end;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000875 int i;
Ye Li07763ac2018-03-28 20:54:11 +0800876
877#ifdef CONFIG_DM_ETH
878 *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
879 if (*packetp == 0) {
880 printf("%s: error allocating packetp\n", __func__);
881 return -ENOMEM;
882 }
883#else
Fabio Estevamfd37f192013-09-17 23:13:10 -0300884 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
Ye Li07763ac2018-03-28 20:54:11 +0800885#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400886
Jagan Teki567173a2016-12-06 00:00:50 +0100887 /* Check if any critical events have happened */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400888 ievent = readl(&fec->eth->ievent);
889 writel(ievent, &fec->eth->ievent);
Marek Vasuteda959f2011-10-24 23:40:03 +0000890 debug("fec_recv: ievent 0x%lx\n", ievent);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400891 if (ievent & FEC_IEVENT_BABR) {
Jagan Teki60752ca2016-12-06 00:00:49 +0100892#ifdef CONFIG_DM_ETH
893 fecmxc_halt(dev);
894 fecmxc_init(dev);
895#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400896 fec_halt(dev);
897 fec_init(dev, fec->bd);
Jagan Teki60752ca2016-12-06 00:00:49 +0100898#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400899 printf("some error: 0x%08lx\n", ievent);
900 return 0;
901 }
902 if (ievent & FEC_IEVENT_HBERR) {
903 /* Heartbeat error */
904 writel(0x00000001 | readl(&fec->eth->x_cntrl),
Jagan Teki567173a2016-12-06 00:00:50 +0100905 &fec->eth->x_cntrl);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400906 }
907 if (ievent & FEC_IEVENT_GRA) {
908 /* Graceful stop complete */
909 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
Jagan Teki60752ca2016-12-06 00:00:49 +0100910#ifdef CONFIG_DM_ETH
911 fecmxc_halt(dev);
912#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400913 fec_halt(dev);
Jagan Teki60752ca2016-12-06 00:00:49 +0100914#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400915 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
Jagan Teki567173a2016-12-06 00:00:50 +0100916 &fec->eth->x_cntrl);
Jagan Teki60752ca2016-12-06 00:00:49 +0100917#ifdef CONFIG_DM_ETH
918 fecmxc_init(dev);
919#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400920 fec_init(dev, fec->bd);
Jagan Teki60752ca2016-12-06 00:00:49 +0100921#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400922 }
923 }
924
925 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000926 * Read the buffer status. Before the status can be read, the data cache
927 * must be invalidated, because the data in RAM might have been changed
928 * by DMA. The descriptors are properly aligned to cachelines so there's
929 * no need to worry they'd overlap.
930 *
931 * WARNING: By invalidating the descriptor here, we also invalidate
932 * the descriptors surrounding this one. Therefore we can NOT change the
933 * contents of this descriptor nor the surrounding ones. The problem is
934 * that in order to mark the descriptor as processed, we need to change
935 * the descriptor. The solution is to mark the whole cache line when all
936 * descriptors in the cache line are processed.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400937 */
Ye Lif24e4822018-01-10 13:20:44 +0800938 addr = (ulong)rbd;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000939 addr &= ~(ARCH_DMA_MINALIGN - 1);
940 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
941 invalidate_dcache_range(addr, addr + size);
942
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400943 bd_status = readw(&rbd->status);
944 debug("fec_recv: status 0x%x\n", bd_status);
945
946 if (!(bd_status & FEC_RBD_EMPTY)) {
947 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
Jagan Teki567173a2016-12-06 00:00:50 +0100948 ((readw(&rbd->data_length) - 4) > 14)) {
949 /* Get buffer address and size */
Albert ARIBAUD \(3ADEV\)b1895842015-06-19 14:18:27 +0200950 addr = readl(&rbd->data_pointer);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400951 frame_length = readw(&rbd->data_length) - 4;
Jagan Teki567173a2016-12-06 00:00:50 +0100952 /* Invalidate data cache over the buffer */
Marek Vasutefe24d22012-08-26 10:19:21 +0000953 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
954 addr &= ~(ARCH_DMA_MINALIGN - 1);
955 invalidate_dcache_range(addr, end);
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000956
Jagan Teki567173a2016-12-06 00:00:50 +0100957 /* Fill the buffer and pass it to upper layers */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000958#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Albert ARIBAUD \(3ADEV\)b1895842015-06-19 14:18:27 +0200959 swap_packet((uint32_t *)addr, frame_length);
Marek Vasutbe7e87e2011-11-08 23:18:10 +0000960#endif
Ye Li07763ac2018-03-28 20:54:11 +0800961
962#ifdef CONFIG_DM_ETH
963 memcpy(*packetp, (char *)addr, frame_length);
964#else
Albert ARIBAUD \(3ADEV\)b1895842015-06-19 14:18:27 +0200965 memcpy(buff, (char *)addr, frame_length);
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500966 net_process_received_packet(buff, frame_length);
Ye Li07763ac2018-03-28 20:54:11 +0800967#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400968 len = frame_length;
969 } else {
970 if (bd_status & FEC_RBD_ERR)
Ye Lif24e4822018-01-10 13:20:44 +0800971 debug("error frame: 0x%08lx 0x%08x\n",
972 addr, bd_status);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400973 }
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000974
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400975 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000976 * Free the current buffer, restart the engine and move forward
977 * to the next buffer. Here we check if the whole cacheline of
978 * descriptors was already processed and if so, we mark it free
979 * as whole.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400980 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000981 size = RXDESC_PER_CACHELINE - 1;
982 if ((fec->rbd_index & size) == size) {
983 i = fec->rbd_index - size;
Ye Lif24e4822018-01-10 13:20:44 +0800984 addr = (ulong)&fec->rbd_base[i];
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000985 for (; i <= fec->rbd_index ; i++) {
986 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
987 &fec->rbd_base[i]);
988 }
989 flush_dcache_range(addr,
Jagan Teki567173a2016-12-06 00:00:50 +0100990 addr + ARCH_DMA_MINALIGN);
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000991 }
992
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400993 fec_rx_task_enable(fec);
994 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
995 }
996 debug("fec_recv: stop\n");
997
998 return len;
999}
1000
Troy Kiskyef8e3a32012-10-22 16:40:44 +00001001static void fec_set_dev_name(char *dest, int dev_id)
1002{
1003 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
1004}
1005
Marek Vasut79e5f272013-10-12 20:36:25 +02001006static int fec_alloc_descs(struct fec_priv *fec)
1007{
1008 unsigned int size;
1009 int i;
1010 uint8_t *data;
Ye Lif24e4822018-01-10 13:20:44 +08001011 ulong addr;
Marek Vasut79e5f272013-10-12 20:36:25 +02001012
1013 /* Allocate TX descriptors. */
1014 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
1015 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
1016 if (!fec->tbd_base)
1017 goto err_tx;
1018
1019 /* Allocate RX descriptors. */
1020 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
1021 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
1022 if (!fec->rbd_base)
1023 goto err_rx;
1024
1025 memset(fec->rbd_base, 0, size);
1026
1027 /* Allocate RX buffers. */
1028
1029 /* Maximum RX buffer size. */
Fabio Estevamdb5b7f52014-08-25 13:34:16 -03001030 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
Marek Vasut79e5f272013-10-12 20:36:25 +02001031 for (i = 0; i < FEC_RBD_NUM; i++) {
Fabio Estevamdb5b7f52014-08-25 13:34:16 -03001032 data = memalign(FEC_DMA_RX_MINALIGN, size);
Marek Vasut79e5f272013-10-12 20:36:25 +02001033 if (!data) {
1034 printf("%s: error allocating rxbuf %d\n", __func__, i);
1035 goto err_ring;
1036 }
1037
1038 memset(data, 0, size);
1039
Ye Lif24e4822018-01-10 13:20:44 +08001040 addr = (ulong)data;
1041 fec->rbd_base[i].data_pointer = (uint32_t)addr;
Marek Vasut79e5f272013-10-12 20:36:25 +02001042 fec->rbd_base[i].status = FEC_RBD_EMPTY;
1043 fec->rbd_base[i].data_length = 0;
1044 /* Flush the buffer to memory. */
Ye Lif24e4822018-01-10 13:20:44 +08001045 flush_dcache_range(addr, addr + size);
Marek Vasut79e5f272013-10-12 20:36:25 +02001046 }
1047
1048 /* Mark the last RBD to close the ring. */
1049 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
1050
1051 fec->rbd_index = 0;
1052 fec->tbd_index = 0;
1053
1054 return 0;
1055
1056err_ring:
Ye Lif24e4822018-01-10 13:20:44 +08001057 for (; i >= 0; i--) {
1058 addr = fec->rbd_base[i].data_pointer;
1059 free((void *)addr);
1060 }
Marek Vasut79e5f272013-10-12 20:36:25 +02001061 free(fec->rbd_base);
1062err_rx:
1063 free(fec->tbd_base);
1064err_tx:
1065 return -ENOMEM;
1066}
1067
1068static void fec_free_descs(struct fec_priv *fec)
1069{
1070 int i;
Ye Lif24e4822018-01-10 13:20:44 +08001071 ulong addr;
Marek Vasut79e5f272013-10-12 20:36:25 +02001072
Ye Lif24e4822018-01-10 13:20:44 +08001073 for (i = 0; i < FEC_RBD_NUM; i++) {
1074 addr = fec->rbd_base[i].data_pointer;
1075 free((void *)addr);
1076 }
Marek Vasut79e5f272013-10-12 20:36:25 +02001077 free(fec->rbd_base);
1078 free(fec->tbd_base);
1079}
1080
Peng Fan1bcabd72018-03-28 20:54:12 +08001081struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
Jagan Teki60752ca2016-12-06 00:00:49 +01001082{
Peng Fan1bcabd72018-03-28 20:54:12 +08001083 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
Jagan Teki60752ca2016-12-06 00:00:49 +01001084 struct mii_dev *bus;
1085 int ret;
1086
1087 bus = mdio_alloc();
1088 if (!bus) {
1089 printf("mdio_alloc failed\n");
1090 return NULL;
1091 }
1092 bus->read = fec_phy_read;
1093 bus->write = fec_phy_write;
1094 bus->priv = eth;
1095 fec_set_dev_name(bus->name, dev_id);
1096
1097 ret = mdio_register(bus);
1098 if (ret) {
1099 printf("mdio_register failed\n");
1100 free(bus);
1101 return NULL;
1102 }
1103 fec_mii_setspeed(eth);
1104 return bus;
1105}
1106
1107#ifndef CONFIG_DM_ETH
Troy Kiskyfe428b92012-10-22 16:40:46 +00001108#ifdef CONFIG_PHYLIB
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +09001109int fec_probe(struct bd_info *bd, int dev_id, uint32_t base_addr,
Troy Kiskyfe428b92012-10-22 16:40:46 +00001110 struct mii_dev *bus, struct phy_device *phydev)
1111#else
Masahiro Yamadabb5a2cf2020-06-26 15:13:34 +09001112static int fec_probe(struct bd_info *bd, int dev_id, uint32_t base_addr,
Troy Kiskyfe428b92012-10-22 16:40:46 +00001113 struct mii_dev *bus, int phy_id)
1114#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001115{
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001116 struct eth_device *edev;
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001117 struct fec_priv *fec;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001118 unsigned char ethaddr[6];
Andy Duan979a5892017-04-10 19:44:35 +08001119 char mac[16];
Marek Vasute382fb42011-09-11 18:05:37 +00001120 uint32_t start;
1121 int ret = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001122
1123 /* create and fill edev struct */
1124 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
1125 if (!edev) {
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001126 puts("fec_mxc: not enough malloc memory for eth_device\n");
Marek Vasute382fb42011-09-11 18:05:37 +00001127 ret = -ENOMEM;
1128 goto err1;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001129 }
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001130
1131 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
1132 if (!fec) {
1133 puts("fec_mxc: not enough malloc memory for fec_priv\n");
Marek Vasute382fb42011-09-11 18:05:37 +00001134 ret = -ENOMEM;
1135 goto err2;
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001136 }
1137
Nobuhiro Iwamatsude0b9572010-10-19 14:03:42 +09001138 memset(edev, 0, sizeof(*edev));
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001139 memset(fec, 0, sizeof(*fec));
1140
Marek Vasut79e5f272013-10-12 20:36:25 +02001141 ret = fec_alloc_descs(fec);
1142 if (ret)
1143 goto err3;
1144
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001145 edev->priv = fec;
1146 edev->init = fec_init;
1147 edev->send = fec_send;
1148 edev->recv = fec_recv;
1149 edev->halt = fec_halt;
Heiko Schocherfb57ec92010-04-27 07:43:52 +02001150 edev->write_hwaddr = fec_set_hwaddr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001151
Ye Lif24e4822018-01-10 13:20:44 +08001152 fec->eth = (struct ethernet_regs *)(ulong)base_addr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001153 fec->bd = bd;
1154
Marek Vasut392b8502011-09-11 18:05:33 +00001155 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001156
1157 /* Reset chip. */
John Rigbycb17b922010-01-25 23:12:55 -07001158 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
Marek Vasute382fb42011-09-11 18:05:37 +00001159 start = get_timer(0);
1160 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1161 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
Vagrant Cascadian3450a852016-10-23 20:45:19 -07001162 printf("FEC MXC: Timeout resetting chip\n");
Marek Vasut79e5f272013-10-12 20:36:25 +02001163 goto err4;
Marek Vasute382fb42011-09-11 18:05:37 +00001164 }
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001165 udelay(10);
Marek Vasute382fb42011-09-11 18:05:37 +00001166 }
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001167
Marek Vasuta5990b22012-05-01 11:09:41 +00001168 fec_reg_setup(fec);
Troy Kiskyef8e3a32012-10-22 16:40:44 +00001169 fec_set_dev_name(edev->name, dev_id);
1170 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
Troy Kisky13947f42012-02-07 14:08:47 +00001171 fec->bus = bus;
Troy Kiskyfe428b92012-10-22 16:40:46 +00001172 fec_mii_setspeed(bus->priv);
1173#ifdef CONFIG_PHYLIB
1174 fec->phydev = phydev;
1175 phy_connect_dev(phydev, edev);
1176 /* Configure phy */
1177 phy_config(phydev);
1178#else
1179 fec->phy_id = phy_id;
1180#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001181 eth_register(edev);
Andy Duan979a5892017-04-10 19:44:35 +08001182 /* only support one eth device, the index number pointed by dev_id */
1183 edev->index = fec->dev_id;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001184
Andy Duanf01e4e12017-04-10 19:44:34 +08001185 if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
1186 debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
Stefano Babic4294b242010-02-01 14:51:30 +01001187 memcpy(edev->enetaddr, ethaddr, 6);
Andy Duan979a5892017-04-10 19:44:35 +08001188 if (fec->dev_id)
1189 sprintf(mac, "eth%daddr", fec->dev_id);
1190 else
1191 strcpy(mac, "ethaddr");
Simon Glass00caae62017-08-03 12:22:12 -06001192 if (!env_get(mac))
Simon Glassfd1e9592017-08-03 12:22:11 -06001193 eth_env_set_enetaddr(mac, ethaddr);
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001194 }
Marek Vasute382fb42011-09-11 18:05:37 +00001195 return ret;
Marek Vasut79e5f272013-10-12 20:36:25 +02001196err4:
1197 fec_free_descs(fec);
Marek Vasute382fb42011-09-11 18:05:37 +00001198err3:
1199 free(fec);
1200err2:
1201 free(edev);
1202err1:
1203 return ret;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001204}
1205
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +09001206int fecmxc_initialize_multi(struct bd_info *bd, int dev_id, int phy_id,
1207 uint32_t addr)
Troy Kiskyeef24482012-10-22 16:40:42 +00001208{
Troy Kiskyfe428b92012-10-22 16:40:46 +00001209 uint32_t base_mii;
1210 struct mii_dev *bus = NULL;
1211#ifdef CONFIG_PHYLIB
1212 struct phy_device *phydev = NULL;
1213#endif
1214 int ret;
1215
Peng Fan3b26d522020-05-01 22:08:37 +08001216 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
1217 if (enet_fused((ulong)addr)) {
1218 printf("SoC fuse indicates Ethernet@0x%x is unavailable.\n", addr);
1219 return -ENODEV;
1220 }
1221 }
1222
Peng Fanfbada482018-03-28 20:54:14 +08001223#ifdef CONFIG_FEC_MXC_MDIO_BASE
Troy Kiskyfe428b92012-10-22 16:40:46 +00001224 /*
1225 * The i.MX28 has two ethernet interfaces, but they are not equal.
1226 * Only the first one can access the MDIO bus.
1227 */
Peng Fanfbada482018-03-28 20:54:14 +08001228 base_mii = CONFIG_FEC_MXC_MDIO_BASE;
Troy Kiskyfe428b92012-10-22 16:40:46 +00001229#else
1230 base_mii = addr;
1231#endif
Troy Kiskyeef24482012-10-22 16:40:42 +00001232 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
Troy Kiskyfe428b92012-10-22 16:40:46 +00001233 bus = fec_get_miibus(base_mii, dev_id);
1234 if (!bus)
1235 return -ENOMEM;
1236#ifdef CONFIG_PHYLIB
1237 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1238 if (!phydev) {
Måns Rullgård845a57b2015-12-08 15:38:46 +00001239 mdio_unregister(bus);
Troy Kiskyfe428b92012-10-22 16:40:46 +00001240 free(bus);
1241 return -ENOMEM;
1242 }
1243 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1244#else
1245 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1246#endif
1247 if (ret) {
1248#ifdef CONFIG_PHYLIB
1249 free(phydev);
1250#endif
Måns Rullgård845a57b2015-12-08 15:38:46 +00001251 mdio_unregister(bus);
Troy Kiskyfe428b92012-10-22 16:40:46 +00001252 free(bus);
1253 }
1254 return ret;
Troy Kiskyeef24482012-10-22 16:40:42 +00001255}
1256
Troy Kisky09439c32012-10-22 16:40:40 +00001257#ifdef CONFIG_FEC_MXC_PHYADDR
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +09001258int fecmxc_initialize(struct bd_info *bd)
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001259{
Troy Kiskyeef24482012-10-22 16:40:42 +00001260 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1261 IMX_FEC_BASE);
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001262}
1263#endif
1264
Troy Kisky13947f42012-02-07 14:08:47 +00001265#ifndef CONFIG_PHYLIB
Marek Vasut2e5f4422011-09-11 18:05:36 +00001266int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1267{
1268 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1269 fec->mii_postcall = cb;
1270 return 0;
1271}
Troy Kisky13947f42012-02-07 14:08:47 +00001272#endif
Jagan Teki60752ca2016-12-06 00:00:49 +01001273
1274#else
1275
Jagan Teki1ed25702016-12-06 00:00:51 +01001276static int fecmxc_read_rom_hwaddr(struct udevice *dev)
1277{
1278 struct fec_priv *priv = dev_get_priv(dev);
Simon Glassc69cda22020-12-03 16:55:20 -07001279 struct eth_pdata *pdata = dev_get_plat(dev);
Jagan Teki1ed25702016-12-06 00:00:51 +01001280
1281 return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
1282}
1283
Tim Harvey87550a82021-06-30 16:50:06 -07001284static int fecmxc_set_promisc(struct udevice *dev, bool enable)
1285{
1286 struct fec_priv *priv = dev_get_priv(dev);
1287
1288 priv->promisc = enable;
1289
1290 return 0;
1291}
1292
Ye Li07763ac2018-03-28 20:54:11 +08001293static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
1294{
1295 if (packet)
1296 free(packet);
1297
1298 return 0;
1299}
1300
Jagan Teki60752ca2016-12-06 00:00:49 +01001301static const struct eth_ops fecmxc_ops = {
1302 .start = fecmxc_init,
1303 .send = fecmxc_send,
1304 .recv = fecmxc_recv,
Ye Li07763ac2018-03-28 20:54:11 +08001305 .free_pkt = fecmxc_free_pkt,
Jagan Teki60752ca2016-12-06 00:00:49 +01001306 .stop = fecmxc_halt,
1307 .write_hwaddr = fecmxc_set_hwaddr,
Jagan Teki1ed25702016-12-06 00:00:51 +01001308 .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
Tim Harvey87550a82021-06-30 16:50:06 -07001309 .set_promisc = fecmxc_set_promisc,
Jagan Teki60752ca2016-12-06 00:00:49 +01001310};
1311
Fabio Estevam89b5bd52020-06-18 20:21:18 -03001312static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev)
Martyn Welch774ec602018-12-11 11:34:45 +00001313{
1314 struct ofnode_phandle_args phandle_args;
Sean Andersoneccd1322021-04-15 13:06:08 -04001315 int reg, ret;
Martyn Welch774ec602018-12-11 11:34:45 +00001316
Sean Andersoneccd1322021-04-15 13:06:08 -04001317 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1318 &phandle_args);
1319 if (ret) {
Tim Harvey69c81d62021-06-30 16:50:04 -07001320 priv->phy_of_node = ofnode_find_subnode(dev_ofnode(dev),
1321 "fixed-link");
1322 if (ofnode_valid(priv->phy_of_node))
1323 return 0;
1324 debug("Failed to find phy-handle (err = %d)\n", ret);
Sean Andersoneccd1322021-04-15 13:06:08 -04001325 return ret;
Martyn Welch774ec602018-12-11 11:34:45 +00001326 }
1327
Sean Andersoneccd1322021-04-15 13:06:08 -04001328 if (!ofnode_is_available(phandle_args.node))
1329 return -ENOENT;
Fabio Estevam89b5bd52020-06-18 20:21:18 -03001330
Sean Andersoneccd1322021-04-15 13:06:08 -04001331 priv->phy_of_node = phandle_args.node;
Martyn Welch774ec602018-12-11 11:34:45 +00001332 reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
1333
1334 return reg;
1335}
1336
Jagan Teki60752ca2016-12-06 00:00:49 +01001337static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
1338{
1339 struct phy_device *phydev;
Martyn Welch774ec602018-12-11 11:34:45 +00001340 int addr;
Jagan Teki60752ca2016-12-06 00:00:49 +01001341
Fabio Estevam89b5bd52020-06-18 20:21:18 -03001342 addr = device_get_phy_addr(priv, dev);
Lukasz Majewski178d4f02018-04-15 21:45:54 +02001343#ifdef CONFIG_FEC_MXC_PHYADDR
Hannes Schmelzerb8820052019-02-15 10:30:18 +01001344 addr = CONFIG_FEC_MXC_PHYADDR;
Jagan Teki60752ca2016-12-06 00:00:49 +01001345#endif
1346
Hannes Schmelzerb8820052019-02-15 10:30:18 +01001347 phydev = phy_connect(priv->bus, addr, dev, priv->interface);
Jagan Teki60752ca2016-12-06 00:00:49 +01001348 if (!phydev)
1349 return -ENODEV;
1350
Jagan Teki60752ca2016-12-06 00:00:49 +01001351 priv->phydev = phydev;
Fabio Estevam89b5bd52020-06-18 20:21:18 -03001352 priv->phydev->node = priv->phy_of_node;
Jagan Teki60752ca2016-12-06 00:00:49 +01001353 phy_config(phydev);
1354
1355 return 0;
1356}
1357
Simon Glassbcee8d62019-12-06 21:41:35 -07001358#if CONFIG_IS_ENABLED(DM_GPIO)
Michael Trimarchiefd0b792018-06-17 15:22:39 +02001359/* FEC GPIO reset */
1360static void fec_gpio_reset(struct fec_priv *priv)
1361{
1362 debug("fec_gpio_reset: fec_gpio_reset(dev)\n");
1363 if (dm_gpio_is_valid(&priv->phy_reset_gpio)) {
1364 dm_gpio_set_value(&priv->phy_reset_gpio, 1);
Martin Fuzzey9b8b9182018-10-04 19:59:18 +02001365 mdelay(priv->reset_delay);
Michael Trimarchiefd0b792018-06-17 15:22:39 +02001366 dm_gpio_set_value(&priv->phy_reset_gpio, 0);
Andrejs Cainikovs31d40452019-03-01 13:27:59 +00001367 if (priv->reset_post_delay)
1368 mdelay(priv->reset_post_delay);
Michael Trimarchiefd0b792018-06-17 15:22:39 +02001369 }
1370}
1371#endif
1372
Jagan Teki60752ca2016-12-06 00:00:49 +01001373static int fecmxc_probe(struct udevice *dev)
1374{
Sean Andersoncd435912021-04-15 13:06:09 -04001375 bool dm_mii_bus = true;
Simon Glassc69cda22020-12-03 16:55:20 -07001376 struct eth_pdata *pdata = dev_get_plat(dev);
Jagan Teki60752ca2016-12-06 00:00:49 +01001377 struct fec_priv *priv = dev_get_priv(dev);
1378 struct mii_dev *bus = NULL;
Jagan Teki60752ca2016-12-06 00:00:49 +01001379 uint32_t start;
1380 int ret;
1381
Peng Fan3b26d522020-05-01 22:08:37 +08001382 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
1383 if (enet_fused((ulong)priv->eth)) {
1384 printf("SoC fuse indicates Ethernet@0x%lx is unavailable.\n", (ulong)priv->eth);
1385 return -ENODEV;
1386 }
1387 }
1388
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +02001389 if (IS_ENABLED(CONFIG_IMX8)) {
1390 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1391 if (ret < 0) {
1392 debug("Can't get FEC ipg clk: %d\n", ret);
1393 return ret;
1394 }
1395 ret = clk_enable(&priv->ipg_clk);
1396 if (ret < 0) {
1397 debug("Can't enable FEC ipg clk: %d\n", ret);
1398 return ret;
1399 }
1400
1401 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
Peng Fan673f6592019-10-25 09:48:02 +00001402 } else if (CONFIG_IS_ENABLED(CLK_CCF)) {
1403 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1404 if (ret < 0) {
1405 debug("Can't get FEC ipg clk: %d\n", ret);
1406 return ret;
1407 }
1408 ret = clk_enable(&priv->ipg_clk);
1409 if(ret)
1410 return ret;
1411
1412 ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
1413 if (ret < 0) {
1414 debug("Can't get FEC ahb clk: %d\n", ret);
1415 return ret;
1416 }
1417 ret = clk_enable(&priv->ahb_clk);
1418 if (ret)
1419 return ret;
1420
1421 ret = clk_get_by_name(dev, "enet_out", &priv->clk_enet_out);
1422 if (!ret) {
1423 ret = clk_enable(&priv->clk_enet_out);
1424 if (ret)
1425 return ret;
1426 }
1427
1428 ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref);
1429 if (!ret) {
1430 ret = clk_enable(&priv->clk_ref);
1431 if (ret)
1432 return ret;
1433 }
1434
1435 ret = clk_get_by_name(dev, "ptp", &priv->clk_ptp);
1436 if (!ret) {
1437 ret = clk_enable(&priv->clk_ptp);
1438 if (ret)
1439 return ret;
1440 }
1441
1442 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +02001443 }
1444
Jagan Teki60752ca2016-12-06 00:00:49 +01001445 ret = fec_alloc_descs(priv);
1446 if (ret)
1447 return ret;
1448
Martin Fuzzeyad8c43c2018-10-04 19:59:20 +02001449#ifdef CONFIG_DM_REGULATOR
1450 if (priv->phy_supply) {
Adam Ford8f1a5ac2019-01-15 11:26:48 -06001451 ret = regulator_set_enable(priv->phy_supply, true);
Martin Fuzzeyad8c43c2018-10-04 19:59:20 +02001452 if (ret) {
1453 printf("%s: Error enabling phy supply\n", dev->name);
1454 return ret;
1455 }
1456 }
1457#endif
1458
Simon Glassbcee8d62019-12-06 21:41:35 -07001459#if CONFIG_IS_ENABLED(DM_GPIO)
Michael Trimarchiefd0b792018-06-17 15:22:39 +02001460 fec_gpio_reset(priv);
1461#endif
Jagan Teki60752ca2016-12-06 00:00:49 +01001462 /* Reset chip. */
Jagan Teki567173a2016-12-06 00:00:50 +01001463 writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
1464 &priv->eth->ecntrl);
Jagan Teki60752ca2016-12-06 00:00:49 +01001465 start = get_timer(0);
1466 while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
1467 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1468 printf("FEC MXC: Timeout reseting chip\n");
1469 goto err_timeout;
1470 }
1471 udelay(10);
1472 }
1473
1474 fec_reg_setup(priv);
Jagan Teki60752ca2016-12-06 00:00:49 +01001475
Simon Glass8b85dfc2020-12-16 21:20:07 -07001476 priv->dev_id = dev_seq(dev);
Ye Li6a895d02020-05-03 22:41:15 +08001477
1478#ifdef CONFIG_DM_ETH_PHY
1479 bus = eth_phy_get_mdio_bus(dev);
Peng Fanfbada482018-03-28 20:54:14 +08001480#endif
Ye Li6a895d02020-05-03 22:41:15 +08001481
1482 if (!bus) {
Sean Andersoncd435912021-04-15 13:06:09 -04001483 dm_mii_bus = false;
Ye Li6a895d02020-05-03 22:41:15 +08001484#ifdef CONFIG_FEC_MXC_MDIO_BASE
Simon Glass8b85dfc2020-12-16 21:20:07 -07001485 bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE,
1486 dev_seq(dev));
Ye Li6a895d02020-05-03 22:41:15 +08001487#else
Simon Glass8b85dfc2020-12-16 21:20:07 -07001488 bus = fec_get_miibus((ulong)priv->eth, dev_seq(dev));
Ye Li6a895d02020-05-03 22:41:15 +08001489#endif
1490 }
Lothar Waßmann306dd7d2017-06-27 15:23:16 +02001491 if (!bus) {
1492 ret = -ENOMEM;
1493 goto err_mii;
1494 }
1495
Ye Li6a895d02020-05-03 22:41:15 +08001496#ifdef CONFIG_DM_ETH_PHY
1497 eth_phy_set_mdio_bus(dev, bus);
1498#endif
1499
Lothar Waßmann306dd7d2017-06-27 15:23:16 +02001500 priv->bus = bus;
Lothar Waßmann306dd7d2017-06-27 15:23:16 +02001501 priv->interface = pdata->phy_interface;
Martin Fuzzey0126c642018-10-04 19:59:21 +02001502 switch (priv->interface) {
1503 case PHY_INTERFACE_MODE_MII:
1504 priv->xcv_type = MII100;
1505 break;
1506 case PHY_INTERFACE_MODE_RMII:
1507 priv->xcv_type = RMII;
1508 break;
1509 case PHY_INTERFACE_MODE_RGMII:
1510 case PHY_INTERFACE_MODE_RGMII_ID:
1511 case PHY_INTERFACE_MODE_RGMII_RXID:
1512 case PHY_INTERFACE_MODE_RGMII_TXID:
1513 priv->xcv_type = RGMII;
1514 break;
1515 default:
1516 priv->xcv_type = CONFIG_FEC_XCV_TYPE;
1517 printf("Unsupported interface type %d defaulting to %d\n",
1518 priv->interface, priv->xcv_type);
1519 break;
1520 }
1521
Lothar Waßmann306dd7d2017-06-27 15:23:16 +02001522 ret = fec_phy_init(priv, dev);
1523 if (ret)
1524 goto err_phy;
1525
Jagan Teki60752ca2016-12-06 00:00:49 +01001526 return 0;
1527
Jagan Teki60752ca2016-12-06 00:00:49 +01001528err_phy:
Sean Andersoncd435912021-04-15 13:06:09 -04001529 if (!dm_mii_bus) {
1530 mdio_unregister(bus);
1531 free(bus);
1532 }
Jagan Teki60752ca2016-12-06 00:00:49 +01001533err_mii:
Ye Li2087eac2018-03-28 20:54:16 +08001534err_timeout:
Jagan Teki60752ca2016-12-06 00:00:49 +01001535 fec_free_descs(priv);
1536 return ret;
1537}
1538
1539static int fecmxc_remove(struct udevice *dev)
1540{
1541 struct fec_priv *priv = dev_get_priv(dev);
1542
1543 free(priv->phydev);
1544 fec_free_descs(priv);
1545 mdio_unregister(priv->bus);
1546 mdio_free(priv->bus);
1547
Martin Fuzzeyad8c43c2018-10-04 19:59:20 +02001548#ifdef CONFIG_DM_REGULATOR
1549 if (priv->phy_supply)
1550 regulator_set_enable(priv->phy_supply, false);
1551#endif
1552
Jagan Teki60752ca2016-12-06 00:00:49 +01001553 return 0;
1554}
1555
Simon Glassd1998a92020-12-03 16:55:21 -07001556static int fecmxc_of_to_plat(struct udevice *dev)
Jagan Teki60752ca2016-12-06 00:00:49 +01001557{
Michael Trimarchiefd0b792018-06-17 15:22:39 +02001558 int ret = 0;
Simon Glassc69cda22020-12-03 16:55:20 -07001559 struct eth_pdata *pdata = dev_get_plat(dev);
Jagan Teki60752ca2016-12-06 00:00:49 +01001560 struct fec_priv *priv = dev_get_priv(dev);
1561 const char *phy_mode;
1562
Masahiro Yamada25484932020-07-17 14:36:48 +09001563 pdata->iobase = dev_read_addr(dev);
Jagan Teki60752ca2016-12-06 00:00:49 +01001564 priv->eth = (struct ethernet_regs *)pdata->iobase;
1565
1566 pdata->phy_interface = -1;
Simon Glasse160f7d2017-01-17 16:52:55 -07001567 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1568 NULL);
Jagan Teki60752ca2016-12-06 00:00:49 +01001569 if (phy_mode)
1570 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1571 if (pdata->phy_interface == -1) {
1572 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1573 return -EINVAL;
1574 }
1575
Martin Fuzzeyad8c43c2018-10-04 19:59:20 +02001576#ifdef CONFIG_DM_REGULATOR
1577 device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
1578#endif
1579
Simon Glassbcee8d62019-12-06 21:41:35 -07001580#if CONFIG_IS_ENABLED(DM_GPIO)
Michael Trimarchiefd0b792018-06-17 15:22:39 +02001581 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
Martin Fuzzey331fcab2018-10-04 19:59:19 +02001582 &priv->phy_reset_gpio, GPIOD_IS_OUT);
1583 if (ret < 0)
1584 return 0; /* property is optional, don't return error! */
Jagan Teki60752ca2016-12-06 00:00:49 +01001585
Martin Fuzzey331fcab2018-10-04 19:59:19 +02001586 priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1);
Michael Trimarchiefd0b792018-06-17 15:22:39 +02001587 if (priv->reset_delay > 1000) {
Martin Fuzzey331fcab2018-10-04 19:59:19 +02001588 printf("FEC MXC: phy reset duration should be <= 1000ms\n");
1589 /* property value wrong, use default value */
1590 priv->reset_delay = 1;
Michael Trimarchiefd0b792018-06-17 15:22:39 +02001591 }
Andrejs Cainikovs31d40452019-03-01 13:27:59 +00001592
1593 priv->reset_post_delay = dev_read_u32_default(dev,
1594 "phy-reset-post-delay",
1595 0);
1596 if (priv->reset_post_delay > 1000) {
1597 printf("FEC MXC: phy reset post delay should be <= 1000ms\n");
1598 /* property value wrong, use default value */
1599 priv->reset_post_delay = 0;
1600 }
Michael Trimarchiefd0b792018-06-17 15:22:39 +02001601#endif
1602
Martin Fuzzey331fcab2018-10-04 19:59:19 +02001603 return 0;
Jagan Teki60752ca2016-12-06 00:00:49 +01001604}
1605
1606static const struct udevice_id fecmxc_ids[] = {
Lukasz Majewski7782f4e2019-06-19 17:31:03 +02001607 { .compatible = "fsl,imx28-fec" },
Jagan Teki60752ca2016-12-06 00:00:49 +01001608 { .compatible = "fsl,imx6q-fec" },
Peng Fan979e0fc2018-03-28 20:54:15 +08001609 { .compatible = "fsl,imx6sl-fec" },
1610 { .compatible = "fsl,imx6sx-fec" },
1611 { .compatible = "fsl,imx6ul-fec" },
Lukasz Majewski948239e2018-04-15 21:54:22 +02001612 { .compatible = "fsl,imx53-fec" },
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +02001613 { .compatible = "fsl,imx7d-fec" },
Lukasz Majewski27589e72019-02-13 22:46:38 +01001614 { .compatible = "fsl,mvf600-fec" },
Jagan Teki60752ca2016-12-06 00:00:49 +01001615 { }
1616};
1617
1618U_BOOT_DRIVER(fecmxc_gem) = {
1619 .name = "fecmxc",
1620 .id = UCLASS_ETH,
1621 .of_match = fecmxc_ids,
Simon Glassd1998a92020-12-03 16:55:21 -07001622 .of_to_plat = fecmxc_of_to_plat,
Jagan Teki60752ca2016-12-06 00:00:49 +01001623 .probe = fecmxc_probe,
1624 .remove = fecmxc_remove,
1625 .ops = &fecmxc_ops,
Simon Glass41575d82020-12-03 16:55:17 -07001626 .priv_auto = sizeof(struct fec_priv),
Simon Glasscaa4daa2020-12-03 16:55:18 -07001627 .plat_auto = sizeof(struct eth_pdata),
Jagan Teki60752ca2016-12-06 00:00:49 +01001628};
1629#endif