blob: fbfc842aca05a0faa7aecfab89a49f50b88bdba5 [file] [log] [blame]
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001/*
2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <malloc.h>
26#include <net.h>
27#include <miiphy.h>
28#include "fec_mxc.h"
29
30#include <asm/arch/clock.h>
31#include <asm/arch/imx-regs.h>
32#include <asm/io.h>
33#include <asm/errno.h>
34
35DECLARE_GLOBAL_DATA_PTR;
36
37#ifndef CONFIG_MII
38#error "CONFIG_MII has to be defined!"
39#endif
40
Eric Nelson5c1ad3e2012-03-15 18:33:25 +000041#ifndef CONFIG_FEC_XCV_TYPE
42#define CONFIG_FEC_XCV_TYPE MII100
Marek Vasut392b8502011-09-11 18:05:33 +000043#endif
44
Marek Vasutbe7e87e2011-11-08 23:18:10 +000045/*
46 * The i.MX28 operates with packets in big endian. We need to swap them before
47 * sending and after receiving.
48 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +000049#ifdef CONFIG_MX28
50#define CONFIG_FEC_MXC_SWAP_PACKET
51#endif
52
53#define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
54
55/* Check various alignment issues at compile time */
56#if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
57#error "ARCH_DMA_MINALIGN must be multiple of 16!"
58#endif
59
60#if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
61 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
62#error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
Marek Vasutbe7e87e2011-11-08 23:18:10 +000063#endif
64
Ilya Yanok0b23fb32009-07-21 19:32:21 +040065#undef DEBUG
66
67struct nbuf {
68 uint8_t data[1500]; /**< actual data */
69 int length; /**< actual length */
70 int used; /**< buffer in use or not */
71 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
72};
73
Eric Nelson5c1ad3e2012-03-15 18:33:25 +000074#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Marek Vasutbe7e87e2011-11-08 23:18:10 +000075static void swap_packet(uint32_t *packet, int length)
76{
77 int i;
78
79 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
80 packet[i] = __swab32(packet[i]);
81}
82#endif
83
84/*
Ilya Yanok0b23fb32009-07-21 19:32:21 +040085 * MII-interface related functions
86 */
Troy Kisky13947f42012-02-07 14:08:47 +000087static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
88 uint8_t regAddr)
Ilya Yanok0b23fb32009-07-21 19:32:21 +040089{
Ilya Yanok0b23fb32009-07-21 19:32:21 +040090 uint32_t reg; /* convenient holder for the PHY register */
91 uint32_t phy; /* convenient holder for the PHY */
92 uint32_t start;
Troy Kisky13947f42012-02-07 14:08:47 +000093 int val;
Ilya Yanok0b23fb32009-07-21 19:32:21 +040094
95 /*
96 * reading from any PHY's register is done by properly
97 * programming the FEC's MII data register.
98 */
Marek Vasutd133b882011-09-11 18:05:34 +000099 writel(FEC_IEVENT_MII, &eth->ievent);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400100 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
101 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
102
103 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
Marek Vasutd133b882011-09-11 18:05:34 +0000104 phy | reg, &eth->mii_data);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400105
106 /*
107 * wait for the related interrupt
108 */
Graeme Russa60d1e52011-07-15 23:31:37 +0000109 start = get_timer(0);
Marek Vasutd133b882011-09-11 18:05:34 +0000110 while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400111 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
112 printf("Read MDIO failed...\n");
113 return -1;
114 }
115 }
116
117 /*
118 * clear mii interrupt bit
119 */
Marek Vasutd133b882011-09-11 18:05:34 +0000120 writel(FEC_IEVENT_MII, &eth->ievent);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400121
122 /*
123 * it's now safe to read the PHY's register
124 */
Troy Kisky13947f42012-02-07 14:08:47 +0000125 val = (unsigned short)readl(&eth->mii_data);
126 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
127 regAddr, val);
128 return val;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400129}
130
Stefano Babic4294b242010-02-01 14:51:30 +0100131static void fec_mii_setspeed(struct fec_priv *fec)
132{
133 /*
134 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
135 * and do not drop the Preamble.
136 */
137 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
138 &fec->eth->mii_speed);
Troy Kisky13947f42012-02-07 14:08:47 +0000139 debug("%s: mii_speed %08x\n", __func__, readl(&fec->eth->mii_speed));
Stefano Babic4294b242010-02-01 14:51:30 +0100140}
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400141
Troy Kisky13947f42012-02-07 14:08:47 +0000142static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
143 uint8_t regAddr, uint16_t data)
144{
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400145 uint32_t reg; /* convenient holder for the PHY register */
146 uint32_t phy; /* convenient holder for the PHY */
147 uint32_t start;
148
149 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
150 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
151
152 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
Marek Vasutd133b882011-09-11 18:05:34 +0000153 FEC_MII_DATA_TA | phy | reg | data, &eth->mii_data);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400154
155 /*
156 * wait for the MII interrupt
157 */
Graeme Russa60d1e52011-07-15 23:31:37 +0000158 start = get_timer(0);
Marek Vasutd133b882011-09-11 18:05:34 +0000159 while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400160 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
161 printf("Write MDIO failed...\n");
162 return -1;
163 }
164 }
165
166 /*
167 * clear MII interrupt bit
168 */
Marek Vasutd133b882011-09-11 18:05:34 +0000169 writel(FEC_IEVENT_MII, &eth->ievent);
Troy Kisky13947f42012-02-07 14:08:47 +0000170 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400171 regAddr, data);
172
173 return 0;
174}
175
Troy Kisky13947f42012-02-07 14:08:47 +0000176int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr)
177{
178 return fec_mdio_read(bus->priv, phyAddr, regAddr);
179}
180
181int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr,
182 u16 data)
183{
184 return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
185}
186
187#ifndef CONFIG_PHYLIB
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400188static int miiphy_restart_aneg(struct eth_device *dev)
189{
Stefano Babicb774fe92012-02-22 00:24:35 +0000190 int ret = 0;
191#if !defined(CONFIG_FEC_MXC_NO_ANEG)
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200192 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Troy Kisky13947f42012-02-07 14:08:47 +0000193 struct ethernet_regs *eth = fec->bus->priv;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200194
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400195 /*
196 * Wake up from sleep if necessary
197 * Reset PHY, then delay 300ns
198 */
John Rigbycb17b922010-01-25 23:12:55 -0700199#ifdef CONFIG_MX27
Troy Kisky13947f42012-02-07 14:08:47 +0000200 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
John Rigbycb17b922010-01-25 23:12:55 -0700201#endif
Troy Kisky13947f42012-02-07 14:08:47 +0000202 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400203 udelay(1000);
204
205 /*
206 * Set the auto-negotiation advertisement register bits
207 */
Troy Kisky13947f42012-02-07 14:08:47 +0000208 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500209 LPA_100FULL | LPA_100HALF | LPA_10FULL |
210 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
Troy Kisky13947f42012-02-07 14:08:47 +0000211 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500212 BMCR_ANENABLE | BMCR_ANRESTART);
Marek Vasut2e5f4422011-09-11 18:05:36 +0000213
214 if (fec->mii_postcall)
215 ret = fec->mii_postcall(fec->phy_id);
216
Stefano Babicb774fe92012-02-22 00:24:35 +0000217#endif
Marek Vasut2e5f4422011-09-11 18:05:36 +0000218 return ret;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400219}
220
221static int miiphy_wait_aneg(struct eth_device *dev)
222{
223 uint32_t start;
Troy Kisky13947f42012-02-07 14:08:47 +0000224 int status;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200225 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Troy Kisky13947f42012-02-07 14:08:47 +0000226 struct ethernet_regs *eth = fec->bus->priv;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400227
228 /*
229 * Wait for AN completion
230 */
Graeme Russa60d1e52011-07-15 23:31:37 +0000231 start = get_timer(0);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400232 do {
233 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
234 printf("%s: Autonegotiation timeout\n", dev->name);
235 return -1;
236 }
237
Troy Kisky13947f42012-02-07 14:08:47 +0000238 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
239 if (status < 0) {
240 printf("%s: Autonegotiation failed. status: %d\n",
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400241 dev->name, status);
242 return -1;
243 }
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500244 } while (!(status & BMSR_LSTATUS));
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400245
246 return 0;
247}
Troy Kisky13947f42012-02-07 14:08:47 +0000248#endif
249
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400250static int fec_rx_task_enable(struct fec_priv *fec)
251{
252 writel(1 << 24, &fec->eth->r_des_active);
253 return 0;
254}
255
256static int fec_rx_task_disable(struct fec_priv *fec)
257{
258 return 0;
259}
260
261static int fec_tx_task_enable(struct fec_priv *fec)
262{
263 writel(1 << 24, &fec->eth->x_des_active);
264 return 0;
265}
266
267static int fec_tx_task_disable(struct fec_priv *fec)
268{
269 return 0;
270}
271
272/**
273 * Initialize receive task's buffer descriptors
274 * @param[in] fec all we know about the device yet
275 * @param[in] count receive buffer count to be allocated
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000276 * @param[in] dsize desired size of each receive buffer
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400277 * @return 0 on success
278 *
279 * For this task we need additional memory for the data buffers. And each
280 * data buffer requires some alignment. Thy must be aligned to a specific
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000281 * boundary each.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400282 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000283static int fec_rbd_init(struct fec_priv *fec, int count, int dsize)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400284{
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000285 uint32_t size;
286 int i;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400287
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400288 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000289 * Allocate memory for the buffers. This allocation respects the
290 * alignment
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400291 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000292 size = roundup(dsize, ARCH_DMA_MINALIGN);
293 for (i = 0; i < count; i++) {
294 uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
295 if (data_ptr == 0) {
296 uint8_t *data = memalign(ARCH_DMA_MINALIGN,
297 size);
298 if (!data) {
299 printf("%s: error allocating rxbuf %d\n",
300 __func__, i);
301 goto err;
302 }
303 writel((uint32_t)data, &fec->rbd_base[i].data_pointer);
304 } /* needs allocation */
305 writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status);
306 writew(0, &fec->rbd_base[i].data_length);
307 }
308
309 /* Mark the last RBD to close the ring. */
310 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400311 fec->rbd_index = 0;
312
313 return 0;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000314
315err:
316 for (; i >= 0; i--) {
317 uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
318 free((void *)data_ptr);
319 }
320
321 return -ENOMEM;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400322}
323
324/**
325 * Initialize transmit task's buffer descriptors
326 * @param[in] fec all we know about the device yet
327 *
328 * Transmit buffers are created externally. We only have to init the BDs here.\n
329 * Note: There is a race condition in the hardware. When only one BD is in
330 * use it must be marked with the WRAP bit to use it for every transmitt.
331 * This bit in combination with the READY bit results into double transmit
332 * of each data buffer. It seems the state machine checks READY earlier then
333 * resetting it after the first transfer.
334 * Using two BDs solves this issue.
335 */
336static void fec_tbd_init(struct fec_priv *fec)
337{
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000338 unsigned addr = (unsigned)fec->tbd_base;
339 unsigned size = roundup(2 * sizeof(struct fec_bd),
340 ARCH_DMA_MINALIGN);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400341 writew(0x0000, &fec->tbd_base[0].status);
342 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
343 fec->tbd_index = 0;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000344 flush_dcache_range(addr, addr+size);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400345}
346
347/**
348 * Mark the given read buffer descriptor as free
349 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
350 * @param[in] pRbd buffer descriptor to mark free again
351 */
352static void fec_rbd_clean(int last, struct fec_bd *pRbd)
353{
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000354 unsigned short flags = FEC_RBD_EMPTY;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400355 if (last)
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000356 flags |= FEC_RBD_WRAP;
357 writew(flags, &pRbd->status);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400358 writew(0, &pRbd->data_length);
359}
360
Fabio Estevambe252b62011-12-20 05:46:31 +0000361static int fec_get_hwaddr(struct eth_device *dev, int dev_id,
362 unsigned char *mac)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400363{
Fabio Estevambe252b62011-12-20 05:46:31 +0000364 imx_get_mac_from_fuse(dev_id, mac);
Eric Jarrige2e236bf2010-04-16 00:03:19 +0200365 return !is_valid_ether_addr(mac);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400366}
367
Stefano Babic4294b242010-02-01 14:51:30 +0100368static int fec_set_hwaddr(struct eth_device *dev)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400369{
Stefano Babic4294b242010-02-01 14:51:30 +0100370 uchar *mac = dev->enetaddr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400371 struct fec_priv *fec = (struct fec_priv *)dev->priv;
372
373 writel(0, &fec->eth->iaddr1);
374 writel(0, &fec->eth->iaddr2);
375 writel(0, &fec->eth->gaddr1);
376 writel(0, &fec->eth->gaddr2);
377
378 /*
379 * Set physical address
380 */
381 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
382 &fec->eth->paddr1);
383 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
384
385 return 0;
386}
387
Troy Kisky13947f42012-02-07 14:08:47 +0000388static void fec_eth_phy_config(struct eth_device *dev)
389{
390#ifdef CONFIG_PHYLIB
391 struct fec_priv *fec = (struct fec_priv *)dev->priv;
392 struct phy_device *phydev;
393
394 phydev = phy_connect(fec->bus, fec->phy_id, dev,
395 PHY_INTERFACE_MODE_RGMII);
396 if (phydev) {
397 fec->phydev = phydev;
398 phy_config(phydev);
399 }
400#endif
401}
402
Marek Vasuta5990b22012-05-01 11:09:41 +0000403/*
404 * Do initial configuration of the FEC registers
405 */
406static void fec_reg_setup(struct fec_priv *fec)
407{
408 uint32_t rcntrl;
409
410 /*
411 * Set interrupt mask register
412 */
413 writel(0x00000000, &fec->eth->imask);
414
415 /*
416 * Clear FEC-Lite interrupt event register(IEVENT)
417 */
418 writel(0xffffffff, &fec->eth->ievent);
419
420
421 /*
422 * Set FEC-Lite receive control register(R_CNTRL):
423 */
424
425 /* Start with frame length = 1518, common for all modes. */
426 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
benoit.thebaudeau@advans9d2d9242012-07-19 02:12:46 +0000427 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
428 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
429 if (fec->xcv_type == RGMII)
Marek Vasuta5990b22012-05-01 11:09:41 +0000430 rcntrl |= FEC_RCNTRL_RGMII;
431 else if (fec->xcv_type == RMII)
432 rcntrl |= FEC_RCNTRL_RMII;
Marek Vasuta5990b22012-05-01 11:09:41 +0000433
434 writel(rcntrl, &fec->eth->r_cntrl);
435}
436
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400437/**
438 * Start the FEC engine
439 * @param[in] dev Our device to handle
440 */
441static int fec_open(struct eth_device *edev)
442{
443 struct fec_priv *fec = (struct fec_priv *)edev->priv;
Troy Kisky28774cb2012-02-07 14:08:46 +0000444 int speed;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000445 uint32_t addr, size;
446 int i;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400447
448 debug("fec_open: fec_open(dev)\n");
449 /* full-duplex, heartbeat disabled */
450 writel(1 << 2, &fec->eth->x_cntrl);
451 fec->rbd_index = 0;
452
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000453 /* Invalidate all descriptors */
454 for (i = 0; i < FEC_RBD_NUM - 1; i++)
455 fec_rbd_clean(0, &fec->rbd_base[i]);
456 fec_rbd_clean(1, &fec->rbd_base[i]);
457
458 /* Flush the descriptors into RAM */
459 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
460 ARCH_DMA_MINALIGN);
461 addr = (uint32_t)fec->rbd_base;
462 flush_dcache_range(addr, addr + size);
463
Troy Kisky28774cb2012-02-07 14:08:46 +0000464#ifdef FEC_QUIRK_ENET_MAC
Jason Liu2ef2b952011-12-16 05:17:07 +0000465 /* Enable ENET HW endian SWAP */
466 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
467 &fec->eth->ecntrl);
468 /* Enable ENET store and forward mode */
469 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
470 &fec->eth->x_wmrk);
471#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400472 /*
473 * Enable FEC-Lite controller
474 */
John Rigbycb17b922010-01-25 23:12:55 -0700475 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
476 &fec->eth->ecntrl);
Liu Hui-R6434396912452011-01-03 22:27:36 +0000477#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
John Rigby740d6ae2010-01-25 23:12:57 -0700478 udelay(100);
479 /*
480 * setup the MII gasket for RMII mode
481 */
482
483 /* disable the gasket */
484 writew(0, &fec->eth->miigsk_enr);
485
486 /* wait for the gasket to be disabled */
487 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
488 udelay(2);
489
490 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
491 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
492
493 /* re-enable the gasket */
494 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
495
496 /* wait until MII gasket is ready */
497 int max_loops = 10;
498 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
499 if (--max_loops <= 0) {
500 printf("WAIT for MII Gasket ready timed out\n");
501 break;
502 }
503 }
504#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400505
Troy Kisky13947f42012-02-07 14:08:47 +0000506#ifdef CONFIG_PHYLIB
507 if (!fec->phydev)
508 fec_eth_phy_config(edev);
509 if (fec->phydev) {
510 /* Start up the PHY */
Timur Tabi11af8d62012-07-09 08:52:43 +0000511 int ret = phy_startup(fec->phydev);
512
513 if (ret) {
514 printf("Could not initialize PHY %s\n",
515 fec->phydev->dev->name);
516 return ret;
517 }
Troy Kisky13947f42012-02-07 14:08:47 +0000518 speed = fec->phydev->speed;
519 } else {
520 speed = _100BASET;
521 }
522#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400523 miiphy_wait_aneg(edev);
Troy Kisky28774cb2012-02-07 14:08:46 +0000524 speed = miiphy_speed(edev->name, fec->phy_id);
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200525 miiphy_duplex(edev->name, fec->phy_id);
Troy Kisky13947f42012-02-07 14:08:47 +0000526#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400527
Troy Kisky28774cb2012-02-07 14:08:46 +0000528#ifdef FEC_QUIRK_ENET_MAC
529 {
530 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
531 u32 rcr = (readl(&fec->eth->r_cntrl) &
532 ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) |
533 FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE;
534 if (speed == _1000BASET)
535 ecr |= FEC_ECNTRL_SPEED;
536 else if (speed != _100BASET)
537 rcr |= FEC_RCNTRL_RMII_10T;
538 writel(ecr, &fec->eth->ecntrl);
539 writel(rcr, &fec->eth->r_cntrl);
540 }
541#endif
542 debug("%s:Speed=%i\n", __func__, speed);
543
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400544 /*
545 * Enable SmartDMA receive task
546 */
547 fec_rx_task_enable(fec);
548
549 udelay(100000);
550 return 0;
551}
552
553static int fec_init(struct eth_device *dev, bd_t* bd)
554{
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400555 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200556 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000557 uint32_t size;
558 int i, ret;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400559
John Rigbye9319f12010-10-13 14:31:08 -0600560 /* Initialize MAC address */
561 fec_set_hwaddr(dev);
562
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400563 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000564 * Allocate transmit descriptors, there are two in total. This
565 * allocation respects cache alignment.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400566 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000567 if (!fec->tbd_base) {
568 size = roundup(2 * sizeof(struct fec_bd),
569 ARCH_DMA_MINALIGN);
570 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
571 if (!fec->tbd_base) {
572 ret = -ENOMEM;
573 goto err1;
574 }
575 memset(fec->tbd_base, 0, size);
576 fec_tbd_init(fec);
577 flush_dcache_range((unsigned)fec->tbd_base, size);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400578 }
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400579
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000580 /*
581 * Allocate receive descriptors. This allocation respects cache
582 * alignment.
583 */
584 if (!fec->rbd_base) {
585 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
586 ARCH_DMA_MINALIGN);
587 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
588 if (!fec->rbd_base) {
589 ret = -ENOMEM;
590 goto err2;
591 }
592 memset(fec->rbd_base, 0, size);
593 /*
594 * Initialize RxBD ring
595 */
596 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
597 ret = -ENOMEM;
598 goto err3;
599 }
600 flush_dcache_range((unsigned)fec->rbd_base,
601 (unsigned)fec->rbd_base + size);
602 }
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400603
Marek Vasuta5990b22012-05-01 11:09:41 +0000604 fec_reg_setup(fec);
Marek Vasut9eb37702011-09-11 18:05:31 +0000605
benoit.thebaudeau@advansf41471e2012-07-19 02:12:58 +0000606 if (fec->xcv_type != SEVENWIRE)
Stefano Babic4294b242010-02-01 14:51:30 +0100607 fec_mii_setspeed(fec);
Marek Vasut9eb37702011-09-11 18:05:31 +0000608
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400609 /*
610 * Set Opcode/Pause Duration Register
611 */
612 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
613 writel(0x2, &fec->eth->x_wmrk);
614 /*
615 * Set multicast address filter
616 */
617 writel(0x00000000, &fec->eth->gaddr1);
618 writel(0x00000000, &fec->eth->gaddr2);
619
620
621 /* clear MIB RAM */
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200622 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
623 writel(0, i);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400624
625 /* FIFO receive start register */
626 writel(0x520, &fec->eth->r_fstart);
627
628 /* size and address of each buffer */
629 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
630 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
631 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
632
Troy Kisky13947f42012-02-07 14:08:47 +0000633#ifndef CONFIG_PHYLIB
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400634 if (fec->xcv_type != SEVENWIRE)
635 miiphy_restart_aneg(dev);
Troy Kisky13947f42012-02-07 14:08:47 +0000636#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400637 fec_open(dev);
638 return 0;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000639
640err3:
641 free(fec->rbd_base);
642err2:
643 free(fec->tbd_base);
644err1:
645 return ret;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400646}
647
648/**
649 * Halt the FEC engine
650 * @param[in] dev Our device to handle
651 */
652static void fec_halt(struct eth_device *dev)
653{
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200654 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400655 int counter = 0xffff;
656
657 /*
658 * issue graceful stop command to the FEC transmitter if necessary
659 */
John Rigbycb17b922010-01-25 23:12:55 -0700660 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400661 &fec->eth->x_cntrl);
662
663 debug("eth_halt: wait for stop regs\n");
664 /*
665 * wait for graceful stop to register
666 */
667 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
John Rigbycb17b922010-01-25 23:12:55 -0700668 udelay(1);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400669
670 /*
671 * Disable SmartDMA tasks
672 */
673 fec_tx_task_disable(fec);
674 fec_rx_task_disable(fec);
675
676 /*
677 * Disable the Ethernet Controller
678 * Note: this will also reset the BD index counter!
679 */
John Rigby740d6ae2010-01-25 23:12:57 -0700680 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
681 &fec->eth->ecntrl);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400682 fec->rbd_index = 0;
683 fec->tbd_index = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400684 debug("eth_halt: done\n");
685}
686
687/**
688 * Transmit one frame
689 * @param[in] dev Our ethernet device to handle
690 * @param[in] packet Pointer to the data to be transmitted
691 * @param[in] length Data count in bytes
692 * @return 0 on success
693 */
Joe Hershberger442dac42012-05-21 14:45:27 +0000694static int fec_send(struct eth_device *dev, void *packet, int length)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400695{
696 unsigned int status;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000697 uint32_t size;
698 uint32_t addr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400699
700 /*
701 * This routine transmits one frame. This routine only accepts
702 * 6-byte Ethernet addresses.
703 */
704 struct fec_priv *fec = (struct fec_priv *)dev->priv;
705
706 /*
707 * Check for valid length of data.
708 */
709 if ((length > 1500) || (length <= 0)) {
Stefano Babic4294b242010-02-01 14:51:30 +0100710 printf("Payload (%d) too large\n", length);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400711 return -1;
712 }
713
714 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000715 * Setup the transmit buffer. We are always using the first buffer for
716 * transmission, the second will be empty and only used to stop the DMA
717 * engine. We also flush the packet to RAM here to avoid cache trouble.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400718 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000719#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Marek Vasutbe7e87e2011-11-08 23:18:10 +0000720 swap_packet((uint32_t *)packet, length);
721#endif
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000722
723 addr = (uint32_t)packet;
724 size = roundup(length, ARCH_DMA_MINALIGN);
725 flush_dcache_range(addr, addr + size);
726
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400727 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000728 writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
729
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400730 /*
731 * update BD's status now
732 * This block:
733 * - is always the last in a chain (means no chain)
734 * - should transmitt the CRC
735 * - might be the last BD in the list, so the address counter should
736 * wrap (-> keep the WRAP flag)
737 */
738 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
739 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
740 writew(status, &fec->tbd_base[fec->tbd_index].status);
741
742 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000743 * Flush data cache. This code flushes both TX descriptors to RAM.
744 * After this code, the descriptors will be safely in RAM and we
745 * can start DMA.
746 */
747 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
748 addr = (uint32_t)fec->tbd_base;
749 flush_dcache_range(addr, addr + size);
750
751 /*
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400752 * Enable SmartDMA transmit task
753 */
754 fec_tx_task_enable(fec);
755
756 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000757 * Wait until frame is sent. On each turn of the wait cycle, we must
758 * invalidate data cache to see what's really in RAM. Also, we need
759 * barrier here.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400760 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000761 invalidate_dcache_range(addr, addr + size);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400762 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
John Rigbycb17b922010-01-25 23:12:55 -0700763 udelay(1);
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000764 invalidate_dcache_range(addr, addr + size);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400765 }
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000766
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400767 debug("fec_send: status 0x%x index %d\n",
768 readw(&fec->tbd_base[fec->tbd_index].status),
769 fec->tbd_index);
770 /* for next transmission use the other buffer */
771 if (fec->tbd_index)
772 fec->tbd_index = 0;
773 else
774 fec->tbd_index = 1;
775
776 return 0;
777}
778
779/**
780 * Pull one frame from the card
781 * @param[in] dev Our ethernet device to handle
782 * @return Length of packet read
783 */
784static int fec_recv(struct eth_device *dev)
785{
786 struct fec_priv *fec = (struct fec_priv *)dev->priv;
787 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
788 unsigned long ievent;
789 int frame_length, len = 0;
790 struct nbuf *frame;
791 uint16_t bd_status;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000792 uint32_t addr, size;
793 int i;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400794 uchar buff[FEC_MAX_PKT_SIZE];
795
796 /*
797 * Check if any critical events have happened
798 */
799 ievent = readl(&fec->eth->ievent);
800 writel(ievent, &fec->eth->ievent);
Marek Vasuteda959f2011-10-24 23:40:03 +0000801 debug("fec_recv: ievent 0x%lx\n", ievent);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400802 if (ievent & FEC_IEVENT_BABR) {
803 fec_halt(dev);
804 fec_init(dev, fec->bd);
805 printf("some error: 0x%08lx\n", ievent);
806 return 0;
807 }
808 if (ievent & FEC_IEVENT_HBERR) {
809 /* Heartbeat error */
810 writel(0x00000001 | readl(&fec->eth->x_cntrl),
811 &fec->eth->x_cntrl);
812 }
813 if (ievent & FEC_IEVENT_GRA) {
814 /* Graceful stop complete */
815 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
816 fec_halt(dev);
817 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
818 &fec->eth->x_cntrl);
819 fec_init(dev, fec->bd);
820 }
821 }
822
823 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000824 * Read the buffer status. Before the status can be read, the data cache
825 * must be invalidated, because the data in RAM might have been changed
826 * by DMA. The descriptors are properly aligned to cachelines so there's
827 * no need to worry they'd overlap.
828 *
829 * WARNING: By invalidating the descriptor here, we also invalidate
830 * the descriptors surrounding this one. Therefore we can NOT change the
831 * contents of this descriptor nor the surrounding ones. The problem is
832 * that in order to mark the descriptor as processed, we need to change
833 * the descriptor. The solution is to mark the whole cache line when all
834 * descriptors in the cache line are processed.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400835 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000836 addr = (uint32_t)rbd;
837 addr &= ~(ARCH_DMA_MINALIGN - 1);
838 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
839 invalidate_dcache_range(addr, addr + size);
840
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400841 bd_status = readw(&rbd->status);
842 debug("fec_recv: status 0x%x\n", bd_status);
843
844 if (!(bd_status & FEC_RBD_EMPTY)) {
845 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
846 ((readw(&rbd->data_length) - 4) > 14)) {
847 /*
848 * Get buffer address and size
849 */
850 frame = (struct nbuf *)readl(&rbd->data_pointer);
851 frame_length = readw(&rbd->data_length) - 4;
852 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000853 * Invalidate data cache over the buffer
854 */
855 addr = (uint32_t)frame;
856 size = roundup(frame_length, ARCH_DMA_MINALIGN);
857 invalidate_dcache_range(addr, addr + size);
858
859 /*
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400860 * Fill the buffer and pass it to upper layers
861 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000862#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Marek Vasutbe7e87e2011-11-08 23:18:10 +0000863 swap_packet((uint32_t *)frame->data, frame_length);
864#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400865 memcpy(buff, frame->data, frame_length);
866 NetReceive(buff, frame_length);
867 len = frame_length;
868 } else {
869 if (bd_status & FEC_RBD_ERR)
870 printf("error frame: 0x%08lx 0x%08x\n",
871 (ulong)rbd->data_pointer,
872 bd_status);
873 }
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000874
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400875 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000876 * Free the current buffer, restart the engine and move forward
877 * to the next buffer. Here we check if the whole cacheline of
878 * descriptors was already processed and if so, we mark it free
879 * as whole.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400880 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000881 size = RXDESC_PER_CACHELINE - 1;
882 if ((fec->rbd_index & size) == size) {
883 i = fec->rbd_index - size;
884 addr = (uint32_t)&fec->rbd_base[i];
885 for (; i <= fec->rbd_index ; i++) {
886 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
887 &fec->rbd_base[i]);
888 }
889 flush_dcache_range(addr,
890 addr + ARCH_DMA_MINALIGN);
891 }
892
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400893 fec_rx_task_enable(fec);
894 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
895 }
896 debug("fec_recv: stop\n");
897
898 return len;
899}
900
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200901static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400902{
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400903 struct eth_device *edev;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200904 struct fec_priv *fec;
Troy Kisky13947f42012-02-07 14:08:47 +0000905 struct mii_dev *bus;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400906 unsigned char ethaddr[6];
Marek Vasute382fb42011-09-11 18:05:37 +0000907 uint32_t start;
908 int ret = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400909
910 /* create and fill edev struct */
911 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
912 if (!edev) {
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200913 puts("fec_mxc: not enough malloc memory for eth_device\n");
Marek Vasute382fb42011-09-11 18:05:37 +0000914 ret = -ENOMEM;
915 goto err1;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400916 }
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200917
918 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
919 if (!fec) {
920 puts("fec_mxc: not enough malloc memory for fec_priv\n");
Marek Vasute382fb42011-09-11 18:05:37 +0000921 ret = -ENOMEM;
922 goto err2;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200923 }
924
Nobuhiro Iwamatsude0b9572010-10-19 14:03:42 +0900925 memset(edev, 0, sizeof(*edev));
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200926 memset(fec, 0, sizeof(*fec));
927
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400928 edev->priv = fec;
929 edev->init = fec_init;
930 edev->send = fec_send;
931 edev->recv = fec_recv;
932 edev->halt = fec_halt;
Heiko Schocherfb57ec92010-04-27 07:43:52 +0200933 edev->write_hwaddr = fec_set_hwaddr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400934
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200935 fec->eth = (struct ethernet_regs *)base_addr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400936 fec->bd = bd;
937
Marek Vasut392b8502011-09-11 18:05:33 +0000938 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400939
940 /* Reset chip. */
John Rigbycb17b922010-01-25 23:12:55 -0700941 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
Marek Vasute382fb42011-09-11 18:05:37 +0000942 start = get_timer(0);
943 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
944 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
945 printf("FEC MXC: Timeout reseting chip\n");
946 goto err3;
947 }
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400948 udelay(10);
Marek Vasute382fb42011-09-11 18:05:37 +0000949 }
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400950
Marek Vasuta5990b22012-05-01 11:09:41 +0000951 fec_reg_setup(fec);
Stefano Babic4294b242010-02-01 14:51:30 +0100952 fec_mii_setspeed(fec);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400953
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200954 if (dev_id == -1) {
955 sprintf(edev->name, "FEC");
956 fec->dev_id = 0;
957 } else {
958 sprintf(edev->name, "FEC%i", dev_id);
959 fec->dev_id = dev_id;
960 }
961 fec->phy_id = phy_id;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400962
Troy Kisky13947f42012-02-07 14:08:47 +0000963 bus = mdio_alloc();
964 if (!bus) {
965 printf("mdio_alloc failed\n");
966 ret = -ENOMEM;
967 goto err3;
968 }
969 bus->read = fec_phy_read;
970 bus->write = fec_phy_write;
971 sprintf(bus->name, edev->name);
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000972#ifdef CONFIG_MX28
Troy Kisky13947f42012-02-07 14:08:47 +0000973 /*
974 * The i.MX28 has two ethernet interfaces, but they are not equal.
975 * Only the first one can access the MDIO bus.
976 */
977 bus->priv = (struct ethernet_regs *)MXS_ENET0_BASE;
978#else
979 bus->priv = fec->eth;
980#endif
981 ret = mdio_register(bus);
982 if (ret) {
983 printf("mdio_register failed\n");
984 free(bus);
985 ret = -ENOMEM;
986 goto err3;
987 }
988 fec->bus = bus;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400989 eth_register(edev);
990
Fabio Estevambe252b62011-12-20 05:46:31 +0000991 if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
992 debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
Stefano Babic4294b242010-02-01 14:51:30 +0100993 memcpy(edev->enetaddr, ethaddr, 6);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400994 }
Troy Kisky13947f42012-02-07 14:08:47 +0000995 /* Configure phy */
996 fec_eth_phy_config(edev);
Marek Vasute382fb42011-09-11 18:05:37 +0000997 return ret;
998
999err3:
1000 free(fec);
1001err2:
1002 free(edev);
1003err1:
1004 return ret;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001005}
1006
Eric Nelson5c1ad3e2012-03-15 18:33:25 +00001007#ifndef CONFIG_FEC_MXC_MULTI
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001008int fecmxc_initialize(bd_t *bd)
1009{
1010 int lout = 1;
1011
1012 debug("eth_init: fec_probe(bd)\n");
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001013 lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
1014
1015 return lout;
1016}
1017#endif
1018
1019int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1020{
1021 int lout = 1;
1022
1023 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1024 lout = fec_probe(bd, dev_id, phy_id, addr);
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001025
1026 return lout;
1027}
Marek Vasut2e5f4422011-09-11 18:05:36 +00001028
Troy Kisky13947f42012-02-07 14:08:47 +00001029#ifndef CONFIG_PHYLIB
Marek Vasut2e5f4422011-09-11 18:05:36 +00001030int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1031{
1032 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1033 fec->mii_postcall = cb;
1034 return 0;
1035}
Troy Kisky13947f42012-02-07 14:08:47 +00001036#endif