blob: 9ae2db033e66b253b1526b38d1128d013ff25cd9 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ilya Yanok0b23fb32009-07-21 19:32:21 +04002/*
3 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
4 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
5 * (C) Copyright 2008 Armadeus Systems nc
6 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
Ilya Yanok0b23fb32009-07-21 19:32:21 +04008 */
9
10#include <common.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070011#include <cpu_func.h>
Jagan Teki60752ca2016-12-06 00:00:49 +010012#include <dm.h>
Simon Glass9fb625c2019-08-01 09:46:51 -060013#include <env.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060014#include <log.h>
Ilya Yanok0b23fb32009-07-21 19:32:21 +040015#include <malloc.h>
Simon Glasscf92e052015-09-02 17:24:58 -060016#include <memalign.h>
Jagan Teki567173a2016-12-06 00:00:50 +010017#include <miiphy.h>
Ilya Yanok0b23fb32009-07-21 19:32:21 +040018#include <net.h>
Jeroen Hofstee84f64c82014-10-08 22:57:40 +020019#include <netdev.h>
Simon Glass90526e92020-05-10 11:39:56 -060020#include <asm/cache.h>
Simon Glassc05ed002020-05-10 11:40:11 -060021#include <linux/delay.h>
Martin Fuzzeyad8c43c2018-10-04 19:59:20 +020022#include <power/regulator.h>
Ilya Yanok0b23fb32009-07-21 19:32:21 +040023
Jagan Teki567173a2016-12-06 00:00:50 +010024#include <asm/io.h>
25#include <linux/errno.h>
26#include <linux/compiler.h>
27
Ilya Yanok0b23fb32009-07-21 19:32:21 +040028#include <asm/arch/clock.h>
29#include <asm/arch/imx-regs.h>
Stefano Babic552a8482017-06-29 10:16:06 +020030#include <asm/mach-imx/sys_proto.h>
Michael Trimarchiefd0b792018-06-17 15:22:39 +020031#include <asm-generic/gpio.h>
32
33#include "fec_mxc.h"
Ye Li6a895d02020-05-03 22:41:15 +080034#include <eth_phy.h>
Ilya Yanok0b23fb32009-07-21 19:32:21 +040035
36DECLARE_GLOBAL_DATA_PTR;
37
Marek Vasutbc1ce152012-08-29 03:49:49 +000038/*
39 * Timeout the transfer after 5 mS. This is usually a bit more, since
40 * the code in the tightloops this timeout is used in adds some overhead.
41 */
42#define FEC_XFER_TIMEOUT 5000
43
Fabio Estevamdb5b7f52014-08-25 13:34:16 -030044/*
45 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
46 * 64-byte alignment in the DMA RX FEC buffer.
47 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
48 * satisfies the alignment on other SoCs (32-bytes)
49 */
50#define FEC_DMA_RX_MINALIGN 64
51
Ilya Yanok0b23fb32009-07-21 19:32:21 +040052#ifndef CONFIG_MII
53#error "CONFIG_MII has to be defined!"
54#endif
55
Eric Nelson5c1ad3e2012-03-15 18:33:25 +000056#ifndef CONFIG_FEC_XCV_TYPE
57#define CONFIG_FEC_XCV_TYPE MII100
Marek Vasut392b8502011-09-11 18:05:33 +000058#endif
59
Marek Vasutbe7e87e2011-11-08 23:18:10 +000060/*
61 * The i.MX28 operates with packets in big endian. We need to swap them before
62 * sending and after receiving.
63 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +000064#ifdef CONFIG_MX28
65#define CONFIG_FEC_MXC_SWAP_PACKET
66#endif
67
68#define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
69
70/* Check various alignment issues at compile time */
71#if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
72#error "ARCH_DMA_MINALIGN must be multiple of 16!"
73#endif
74
75#if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
76 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
77#error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
Marek Vasutbe7e87e2011-11-08 23:18:10 +000078#endif
79
Ilya Yanok0b23fb32009-07-21 19:32:21 +040080#undef DEBUG
81
Eric Nelson5c1ad3e2012-03-15 18:33:25 +000082#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Marek Vasutbe7e87e2011-11-08 23:18:10 +000083static void swap_packet(uint32_t *packet, int length)
84{
85 int i;
86
87 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
88 packet[i] = __swab32(packet[i]);
89}
90#endif
91
Jagan Teki567173a2016-12-06 00:00:50 +010092/* MII-interface related functions */
93static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
94 uint8_t regaddr)
Ilya Yanok0b23fb32009-07-21 19:32:21 +040095{
Ilya Yanok0b23fb32009-07-21 19:32:21 +040096 uint32_t reg; /* convenient holder for the PHY register */
97 uint32_t phy; /* convenient holder for the PHY */
98 uint32_t start;
Troy Kisky13947f42012-02-07 14:08:47 +000099 int val;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400100
101 /*
102 * reading from any PHY's register is done by properly
103 * programming the FEC's MII data register.
104 */
Marek Vasutd133b882011-09-11 18:05:34 +0000105 writel(FEC_IEVENT_MII, &eth->ievent);
Jagan Teki567173a2016-12-06 00:00:50 +0100106 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
107 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400108
109 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
Marek Vasutd133b882011-09-11 18:05:34 +0000110 phy | reg, &eth->mii_data);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400111
Jagan Teki567173a2016-12-06 00:00:50 +0100112 /* wait for the related interrupt */
Graeme Russa60d1e52011-07-15 23:31:37 +0000113 start = get_timer(0);
Marek Vasutd133b882011-09-11 18:05:34 +0000114 while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400115 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
116 printf("Read MDIO failed...\n");
117 return -1;
118 }
119 }
120
Jagan Teki567173a2016-12-06 00:00:50 +0100121 /* clear mii interrupt bit */
Marek Vasutd133b882011-09-11 18:05:34 +0000122 writel(FEC_IEVENT_MII, &eth->ievent);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400123
Jagan Teki567173a2016-12-06 00:00:50 +0100124 /* it's now safe to read the PHY's register */
Troy Kisky13947f42012-02-07 14:08:47 +0000125 val = (unsigned short)readl(&eth->mii_data);
Jagan Teki567173a2016-12-06 00:00:50 +0100126 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
127 regaddr, val);
Troy Kisky13947f42012-02-07 14:08:47 +0000128 return val;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400129}
130
Peng Fan673f6592019-10-25 09:48:02 +0000131#ifndef imx_get_fecclk
132u32 __weak imx_get_fecclk(void)
133{
134 return 0;
135}
136#endif
137
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +0200138static int fec_get_clk_rate(void *udev, int idx)
139{
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +0200140 struct fec_priv *fec;
141 struct udevice *dev;
142 int ret;
143
Peng Fan673f6592019-10-25 09:48:02 +0000144 if (IS_ENABLED(CONFIG_IMX8) ||
145 CONFIG_IS_ENABLED(CLK_CCF)) {
146 dev = udev;
147 if (!dev) {
148 ret = uclass_get_device(UCLASS_ETH, idx, &dev);
149 if (ret < 0) {
150 debug("Can't get FEC udev: %d\n", ret);
151 return ret;
152 }
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +0200153 }
Peng Fan673f6592019-10-25 09:48:02 +0000154
155 fec = dev_get_priv(dev);
156 if (fec)
157 return fec->clk_rate;
158
159 return -EINVAL;
160 } else {
161 return imx_get_fecclk();
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +0200162 }
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +0200163}
164
Troy Kisky575c5cc2012-10-22 16:40:41 +0000165static void fec_mii_setspeed(struct ethernet_regs *eth)
Stefano Babic4294b242010-02-01 14:51:30 +0100166{
167 /*
168 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
169 * and do not drop the Preamble.
Måns Rullgård843a3e52015-12-08 15:38:45 +0000170 *
171 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
172 * MII_SPEED) register that defines the MDIO output hold time. Earlier
173 * versions are RAZ there, so just ignore the difference and write the
174 * register always.
175 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
176 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
177 * output.
178 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
179 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
180 * holdtime cannot result in a value greater than 3.
Stefano Babic4294b242010-02-01 14:51:30 +0100181 */
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +0200182 u32 pclk;
183 u32 speed;
184 u32 hold;
185 int ret;
186
187 ret = fec_get_clk_rate(NULL, 0);
188 if (ret < 0) {
189 printf("Can't find FEC0 clk rate: %d\n", ret);
190 return;
191 }
192 pclk = ret;
193 speed = DIV_ROUND_UP(pclk, 5000000);
194 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
195
Markus Niebel6ba45cc2014-02-05 10:54:11 +0100196#ifdef FEC_QUIRK_ENET_MAC
197 speed--;
198#endif
Måns Rullgård843a3e52015-12-08 15:38:45 +0000199 writel(speed << 1 | hold << 8, &eth->mii_speed);
Troy Kisky575c5cc2012-10-22 16:40:41 +0000200 debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));
Stefano Babic4294b242010-02-01 14:51:30 +0100201}
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400202
Jagan Teki567173a2016-12-06 00:00:50 +0100203static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
204 uint8_t regaddr, uint16_t data)
Troy Kisky13947f42012-02-07 14:08:47 +0000205{
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400206 uint32_t reg; /* convenient holder for the PHY register */
207 uint32_t phy; /* convenient holder for the PHY */
208 uint32_t start;
209
Jagan Teki567173a2016-12-06 00:00:50 +0100210 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
211 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400212
213 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
Marek Vasutd133b882011-09-11 18:05:34 +0000214 FEC_MII_DATA_TA | phy | reg | data, &eth->mii_data);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400215
Jagan Teki567173a2016-12-06 00:00:50 +0100216 /* wait for the MII interrupt */
Graeme Russa60d1e52011-07-15 23:31:37 +0000217 start = get_timer(0);
Marek Vasutd133b882011-09-11 18:05:34 +0000218 while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400219 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
220 printf("Write MDIO failed...\n");
221 return -1;
222 }
223 }
224
Jagan Teki567173a2016-12-06 00:00:50 +0100225 /* clear MII interrupt bit */
Marek Vasutd133b882011-09-11 18:05:34 +0000226 writel(FEC_IEVENT_MII, &eth->ievent);
Jagan Teki567173a2016-12-06 00:00:50 +0100227 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
228 regaddr, data);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400229
230 return 0;
231}
232
Jagan Teki567173a2016-12-06 00:00:50 +0100233static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
234 int regaddr)
Troy Kisky13947f42012-02-07 14:08:47 +0000235{
Jagan Teki567173a2016-12-06 00:00:50 +0100236 return fec_mdio_read(bus->priv, phyaddr, regaddr);
Troy Kisky13947f42012-02-07 14:08:47 +0000237}
238
Jagan Teki567173a2016-12-06 00:00:50 +0100239static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
240 int regaddr, u16 data)
Troy Kisky13947f42012-02-07 14:08:47 +0000241{
Jagan Teki567173a2016-12-06 00:00:50 +0100242 return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
Troy Kisky13947f42012-02-07 14:08:47 +0000243}
244
245#ifndef CONFIG_PHYLIB
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400246static int miiphy_restart_aneg(struct eth_device *dev)
247{
Stefano Babicb774fe92012-02-22 00:24:35 +0000248 int ret = 0;
249#if !defined(CONFIG_FEC_MXC_NO_ANEG)
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200250 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Troy Kisky13947f42012-02-07 14:08:47 +0000251 struct ethernet_regs *eth = fec->bus->priv;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200252
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400253 /*
254 * Wake up from sleep if necessary
255 * Reset PHY, then delay 300ns
256 */
John Rigbycb17b922010-01-25 23:12:55 -0700257#ifdef CONFIG_MX27
Troy Kisky13947f42012-02-07 14:08:47 +0000258 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
John Rigbycb17b922010-01-25 23:12:55 -0700259#endif
Troy Kisky13947f42012-02-07 14:08:47 +0000260 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400261 udelay(1000);
262
Jagan Teki567173a2016-12-06 00:00:50 +0100263 /* Set the auto-negotiation advertisement register bits */
Troy Kisky13947f42012-02-07 14:08:47 +0000264 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
Jagan Teki567173a2016-12-06 00:00:50 +0100265 LPA_100FULL | LPA_100HALF | LPA_10FULL |
266 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
Troy Kisky13947f42012-02-07 14:08:47 +0000267 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
Jagan Teki567173a2016-12-06 00:00:50 +0100268 BMCR_ANENABLE | BMCR_ANRESTART);
Marek Vasut2e5f4422011-09-11 18:05:36 +0000269
270 if (fec->mii_postcall)
271 ret = fec->mii_postcall(fec->phy_id);
272
Stefano Babicb774fe92012-02-22 00:24:35 +0000273#endif
Marek Vasut2e5f4422011-09-11 18:05:36 +0000274 return ret;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400275}
276
Hannes Schmelzer07507012016-06-22 12:07:14 +0200277#ifndef CONFIG_FEC_FIXED_SPEED
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400278static int miiphy_wait_aneg(struct eth_device *dev)
279{
280 uint32_t start;
Troy Kisky13947f42012-02-07 14:08:47 +0000281 int status;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200282 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Troy Kisky13947f42012-02-07 14:08:47 +0000283 struct ethernet_regs *eth = fec->bus->priv;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400284
Jagan Teki567173a2016-12-06 00:00:50 +0100285 /* Wait for AN completion */
Graeme Russa60d1e52011-07-15 23:31:37 +0000286 start = get_timer(0);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400287 do {
288 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
289 printf("%s: Autonegotiation timeout\n", dev->name);
290 return -1;
291 }
292
Troy Kisky13947f42012-02-07 14:08:47 +0000293 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
294 if (status < 0) {
295 printf("%s: Autonegotiation failed. status: %d\n",
Jagan Teki567173a2016-12-06 00:00:50 +0100296 dev->name, status);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400297 return -1;
298 }
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500299 } while (!(status & BMSR_LSTATUS));
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400300
301 return 0;
302}
Hannes Schmelzer07507012016-06-22 12:07:14 +0200303#endif /* CONFIG_FEC_FIXED_SPEED */
Troy Kisky13947f42012-02-07 14:08:47 +0000304#endif
305
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400306static int fec_rx_task_enable(struct fec_priv *fec)
307{
Marek Vasutc0b5a3b2012-08-29 03:49:51 +0000308 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400309 return 0;
310}
311
312static int fec_rx_task_disable(struct fec_priv *fec)
313{
314 return 0;
315}
316
317static int fec_tx_task_enable(struct fec_priv *fec)
318{
Marek Vasutc0b5a3b2012-08-29 03:49:51 +0000319 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400320 return 0;
321}
322
323static int fec_tx_task_disable(struct fec_priv *fec)
324{
325 return 0;
326}
327
328/**
329 * Initialize receive task's buffer descriptors
330 * @param[in] fec all we know about the device yet
331 * @param[in] count receive buffer count to be allocated
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000332 * @param[in] dsize desired size of each receive buffer
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400333 * @return 0 on success
334 *
Marek Vasut79e5f272013-10-12 20:36:25 +0200335 * Init all RX descriptors to default values.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400336 */
Marek Vasut79e5f272013-10-12 20:36:25 +0200337static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400338{
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000339 uint32_t size;
Ye Lif24e4822018-01-10 13:20:44 +0800340 ulong data;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000341 int i;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400342
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400343 /*
Marek Vasut79e5f272013-10-12 20:36:25 +0200344 * Reload the RX descriptors with default values and wipe
345 * the RX buffers.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400346 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000347 size = roundup(dsize, ARCH_DMA_MINALIGN);
348 for (i = 0; i < count; i++) {
Ye Lif24e4822018-01-10 13:20:44 +0800349 data = fec->rbd_base[i].data_pointer;
350 memset((void *)data, 0, dsize);
351 flush_dcache_range(data, data + size);
Marek Vasut79e5f272013-10-12 20:36:25 +0200352
353 fec->rbd_base[i].status = FEC_RBD_EMPTY;
354 fec->rbd_base[i].data_length = 0;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000355 }
356
357 /* Mark the last RBD to close the ring. */
Marek Vasut79e5f272013-10-12 20:36:25 +0200358 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400359 fec->rbd_index = 0;
360
Ye Lif24e4822018-01-10 13:20:44 +0800361 flush_dcache_range((ulong)fec->rbd_base,
362 (ulong)fec->rbd_base + size);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400363}
364
365/**
366 * Initialize transmit task's buffer descriptors
367 * @param[in] fec all we know about the device yet
368 *
369 * Transmit buffers are created externally. We only have to init the BDs here.\n
370 * Note: There is a race condition in the hardware. When only one BD is in
371 * use it must be marked with the WRAP bit to use it for every transmitt.
372 * This bit in combination with the READY bit results into double transmit
373 * of each data buffer. It seems the state machine checks READY earlier then
374 * resetting it after the first transfer.
375 * Using two BDs solves this issue.
376 */
377static void fec_tbd_init(struct fec_priv *fec)
378{
Ye Lif24e4822018-01-10 13:20:44 +0800379 ulong addr = (ulong)fec->tbd_base;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000380 unsigned size = roundup(2 * sizeof(struct fec_bd),
381 ARCH_DMA_MINALIGN);
Marek Vasut79e5f272013-10-12 20:36:25 +0200382
383 memset(fec->tbd_base, 0, size);
384 fec->tbd_base[0].status = 0;
385 fec->tbd_base[1].status = FEC_TBD_WRAP;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400386 fec->tbd_index = 0;
Marek Vasut79e5f272013-10-12 20:36:25 +0200387 flush_dcache_range(addr, addr + size);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400388}
389
390/**
391 * Mark the given read buffer descriptor as free
392 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
Jagan Teki567173a2016-12-06 00:00:50 +0100393 * @param[in] prbd buffer descriptor to mark free again
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400394 */
Jagan Teki567173a2016-12-06 00:00:50 +0100395static void fec_rbd_clean(int last, struct fec_bd *prbd)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400396{
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000397 unsigned short flags = FEC_RBD_EMPTY;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400398 if (last)
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000399 flags |= FEC_RBD_WRAP;
Jagan Teki567173a2016-12-06 00:00:50 +0100400 writew(flags, &prbd->status);
401 writew(0, &prbd->data_length);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400402}
403
Jagan Tekif54183e2016-12-06 00:00:48 +0100404static int fec_get_hwaddr(int dev_id, unsigned char *mac)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400405{
Fabio Estevambe252b62011-12-20 05:46:31 +0000406 imx_get_mac_from_fuse(dev_id, mac);
Joe Hershberger0adb5b72015-04-08 01:41:04 -0500407 return !is_valid_ethaddr(mac);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400408}
409
Jagan Teki60752ca2016-12-06 00:00:49 +0100410#ifdef CONFIG_DM_ETH
411static int fecmxc_set_hwaddr(struct udevice *dev)
412#else
Stefano Babic4294b242010-02-01 14:51:30 +0100413static int fec_set_hwaddr(struct eth_device *dev)
Jagan Teki60752ca2016-12-06 00:00:49 +0100414#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400415{
Jagan Teki60752ca2016-12-06 00:00:49 +0100416#ifdef CONFIG_DM_ETH
417 struct fec_priv *fec = dev_get_priv(dev);
418 struct eth_pdata *pdata = dev_get_platdata(dev);
419 uchar *mac = pdata->enetaddr;
420#else
Stefano Babic4294b242010-02-01 14:51:30 +0100421 uchar *mac = dev->enetaddr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400422 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki60752ca2016-12-06 00:00:49 +0100423#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400424
425 writel(0, &fec->eth->iaddr1);
426 writel(0, &fec->eth->iaddr2);
427 writel(0, &fec->eth->gaddr1);
428 writel(0, &fec->eth->gaddr2);
429
Jagan Teki567173a2016-12-06 00:00:50 +0100430 /* Set physical address */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400431 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
Jagan Teki567173a2016-12-06 00:00:50 +0100432 &fec->eth->paddr1);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400433 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
434
435 return 0;
436}
437
Jagan Teki567173a2016-12-06 00:00:50 +0100438/* Do initial configuration of the FEC registers */
Marek Vasuta5990b22012-05-01 11:09:41 +0000439static void fec_reg_setup(struct fec_priv *fec)
440{
441 uint32_t rcntrl;
442
Jagan Teki567173a2016-12-06 00:00:50 +0100443 /* Set interrupt mask register */
Marek Vasuta5990b22012-05-01 11:09:41 +0000444 writel(0x00000000, &fec->eth->imask);
445
Jagan Teki567173a2016-12-06 00:00:50 +0100446 /* Clear FEC-Lite interrupt event register(IEVENT) */
Marek Vasuta5990b22012-05-01 11:09:41 +0000447 writel(0xffffffff, &fec->eth->ievent);
448
Jagan Teki567173a2016-12-06 00:00:50 +0100449 /* Set FEC-Lite receive control register(R_CNTRL): */
Marek Vasuta5990b22012-05-01 11:09:41 +0000450
451 /* Start with frame length = 1518, common for all modes. */
452 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
benoit.thebaudeau@advans9d2d9242012-07-19 02:12:46 +0000453 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
454 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
455 if (fec->xcv_type == RGMII)
Marek Vasuta5990b22012-05-01 11:09:41 +0000456 rcntrl |= FEC_RCNTRL_RGMII;
457 else if (fec->xcv_type == RMII)
458 rcntrl |= FEC_RCNTRL_RMII;
Marek Vasuta5990b22012-05-01 11:09:41 +0000459
460 writel(rcntrl, &fec->eth->r_cntrl);
461}
462
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400463/**
464 * Start the FEC engine
465 * @param[in] dev Our device to handle
466 */
Jagan Teki60752ca2016-12-06 00:00:49 +0100467#ifdef CONFIG_DM_ETH
468static int fec_open(struct udevice *dev)
469#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400470static int fec_open(struct eth_device *edev)
Jagan Teki60752ca2016-12-06 00:00:49 +0100471#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400472{
Jagan Teki60752ca2016-12-06 00:00:49 +0100473#ifdef CONFIG_DM_ETH
474 struct fec_priv *fec = dev_get_priv(dev);
475#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400476 struct fec_priv *fec = (struct fec_priv *)edev->priv;
Jagan Teki60752ca2016-12-06 00:00:49 +0100477#endif
Troy Kisky28774cb2012-02-07 14:08:46 +0000478 int speed;
Ye Lif24e4822018-01-10 13:20:44 +0800479 ulong addr, size;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000480 int i;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400481
482 debug("fec_open: fec_open(dev)\n");
483 /* full-duplex, heartbeat disabled */
484 writel(1 << 2, &fec->eth->x_cntrl);
485 fec->rbd_index = 0;
486
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000487 /* Invalidate all descriptors */
488 for (i = 0; i < FEC_RBD_NUM - 1; i++)
489 fec_rbd_clean(0, &fec->rbd_base[i]);
490 fec_rbd_clean(1, &fec->rbd_base[i]);
491
492 /* Flush the descriptors into RAM */
493 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
494 ARCH_DMA_MINALIGN);
Ye Lif24e4822018-01-10 13:20:44 +0800495 addr = (ulong)fec->rbd_base;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000496 flush_dcache_range(addr, addr + size);
497
Troy Kisky28774cb2012-02-07 14:08:46 +0000498#ifdef FEC_QUIRK_ENET_MAC
Jason Liu2ef2b952011-12-16 05:17:07 +0000499 /* Enable ENET HW endian SWAP */
500 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
Jagan Teki567173a2016-12-06 00:00:50 +0100501 &fec->eth->ecntrl);
Jason Liu2ef2b952011-12-16 05:17:07 +0000502 /* Enable ENET store and forward mode */
503 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
Jagan Teki567173a2016-12-06 00:00:50 +0100504 &fec->eth->x_wmrk);
Jason Liu2ef2b952011-12-16 05:17:07 +0000505#endif
Jagan Teki567173a2016-12-06 00:00:50 +0100506 /* Enable FEC-Lite controller */
John Rigbycb17b922010-01-25 23:12:55 -0700507 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
Jagan Teki567173a2016-12-06 00:00:50 +0100508 &fec->eth->ecntrl);
509
Philippe Schenkera1a34fa2020-03-11 11:52:58 +0100510#ifdef FEC_ENET_ENABLE_TXC_DELAY
511 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_TXC_DLY,
512 &fec->eth->ecntrl);
513#endif
514
515#ifdef FEC_ENET_ENABLE_RXC_DELAY
516 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RXC_DLY,
517 &fec->eth->ecntrl);
518#endif
519
Fabio Estevam7df51fd2013-09-13 00:36:27 -0300520#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
John Rigby740d6ae2010-01-25 23:12:57 -0700521 udelay(100);
John Rigby740d6ae2010-01-25 23:12:57 -0700522
Jagan Teki567173a2016-12-06 00:00:50 +0100523 /* setup the MII gasket for RMII mode */
John Rigby740d6ae2010-01-25 23:12:57 -0700524 /* disable the gasket */
525 writew(0, &fec->eth->miigsk_enr);
526
527 /* wait for the gasket to be disabled */
528 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
529 udelay(2);
530
531 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
532 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
533
534 /* re-enable the gasket */
535 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
536
537 /* wait until MII gasket is ready */
538 int max_loops = 10;
539 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
540 if (--max_loops <= 0) {
541 printf("WAIT for MII Gasket ready timed out\n");
542 break;
543 }
544 }
545#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400546
Troy Kisky13947f42012-02-07 14:08:47 +0000547#ifdef CONFIG_PHYLIB
Troy Kisky4dc27ee2012-10-22 16:40:45 +0000548 {
Troy Kisky13947f42012-02-07 14:08:47 +0000549 /* Start up the PHY */
Timur Tabi11af8d62012-07-09 08:52:43 +0000550 int ret = phy_startup(fec->phydev);
551
552 if (ret) {
553 printf("Could not initialize PHY %s\n",
554 fec->phydev->dev->name);
555 return ret;
556 }
Troy Kisky13947f42012-02-07 14:08:47 +0000557 speed = fec->phydev->speed;
Troy Kisky13947f42012-02-07 14:08:47 +0000558 }
Hannes Schmelzer07507012016-06-22 12:07:14 +0200559#elif CONFIG_FEC_FIXED_SPEED
560 speed = CONFIG_FEC_FIXED_SPEED;
Troy Kisky13947f42012-02-07 14:08:47 +0000561#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400562 miiphy_wait_aneg(edev);
Troy Kisky28774cb2012-02-07 14:08:46 +0000563 speed = miiphy_speed(edev->name, fec->phy_id);
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200564 miiphy_duplex(edev->name, fec->phy_id);
Troy Kisky13947f42012-02-07 14:08:47 +0000565#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400566
Troy Kisky28774cb2012-02-07 14:08:46 +0000567#ifdef FEC_QUIRK_ENET_MAC
568 {
569 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
Alison Wangbcb6e902013-05-27 22:55:43 +0000570 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
Troy Kisky28774cb2012-02-07 14:08:46 +0000571 if (speed == _1000BASET)
572 ecr |= FEC_ECNTRL_SPEED;
573 else if (speed != _100BASET)
574 rcr |= FEC_RCNTRL_RMII_10T;
575 writel(ecr, &fec->eth->ecntrl);
576 writel(rcr, &fec->eth->r_cntrl);
577 }
578#endif
579 debug("%s:Speed=%i\n", __func__, speed);
580
Jagan Teki567173a2016-12-06 00:00:50 +0100581 /* Enable SmartDMA receive task */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400582 fec_rx_task_enable(fec);
583
584 udelay(100000);
585 return 0;
586}
587
Jagan Teki60752ca2016-12-06 00:00:49 +0100588#ifdef CONFIG_DM_ETH
589static int fecmxc_init(struct udevice *dev)
590#else
Jagan Teki567173a2016-12-06 00:00:50 +0100591static int fec_init(struct eth_device *dev, bd_t *bd)
Jagan Teki60752ca2016-12-06 00:00:49 +0100592#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400593{
Jagan Teki60752ca2016-12-06 00:00:49 +0100594#ifdef CONFIG_DM_ETH
595 struct fec_priv *fec = dev_get_priv(dev);
596#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400597 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki60752ca2016-12-06 00:00:49 +0100598#endif
Ye Lif24e4822018-01-10 13:20:44 +0800599 u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
600 u8 *i;
601 ulong addr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400602
John Rigbye9319f12010-10-13 14:31:08 -0600603 /* Initialize MAC address */
Jagan Teki60752ca2016-12-06 00:00:49 +0100604#ifdef CONFIG_DM_ETH
605 fecmxc_set_hwaddr(dev);
606#else
John Rigbye9319f12010-10-13 14:31:08 -0600607 fec_set_hwaddr(dev);
Jagan Teki60752ca2016-12-06 00:00:49 +0100608#endif
John Rigbye9319f12010-10-13 14:31:08 -0600609
Jagan Teki567173a2016-12-06 00:00:50 +0100610 /* Setup transmit descriptors, there are two in total. */
Marek Vasut79e5f272013-10-12 20:36:25 +0200611 fec_tbd_init(fec);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400612
Marek Vasut79e5f272013-10-12 20:36:25 +0200613 /* Setup receive descriptors. */
614 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400615
Marek Vasuta5990b22012-05-01 11:09:41 +0000616 fec_reg_setup(fec);
Marek Vasut9eb37702011-09-11 18:05:31 +0000617
benoit.thebaudeau@advansf41471e2012-07-19 02:12:58 +0000618 if (fec->xcv_type != SEVENWIRE)
Troy Kisky575c5cc2012-10-22 16:40:41 +0000619 fec_mii_setspeed(fec->bus->priv);
Marek Vasut9eb37702011-09-11 18:05:31 +0000620
Jagan Teki567173a2016-12-06 00:00:50 +0100621 /* Set Opcode/Pause Duration Register */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400622 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
623 writel(0x2, &fec->eth->x_wmrk);
Jagan Teki567173a2016-12-06 00:00:50 +0100624
625 /* Set multicast address filter */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400626 writel(0x00000000, &fec->eth->gaddr1);
627 writel(0x00000000, &fec->eth->gaddr2);
628
Peng Fan238a53c2018-01-10 13:20:43 +0800629 /* Do not access reserved register */
Peng Fanb5d97e12019-04-15 05:18:33 +0000630 if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m()) {
Peng Fanfbecbaa2015-08-12 17:46:51 +0800631 /* clear MIB RAM */
632 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
633 writel(0, i);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400634
Peng Fanfbecbaa2015-08-12 17:46:51 +0800635 /* FIFO receive start register */
636 writel(0x520, &fec->eth->r_fstart);
637 }
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400638
639 /* size and address of each buffer */
640 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
Ye Lif24e4822018-01-10 13:20:44 +0800641
642 addr = (ulong)fec->tbd_base;
643 writel((uint32_t)addr, &fec->eth->etdsr);
644
645 addr = (ulong)fec->rbd_base;
646 writel((uint32_t)addr, &fec->eth->erdsr);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400647
Troy Kisky13947f42012-02-07 14:08:47 +0000648#ifndef CONFIG_PHYLIB
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400649 if (fec->xcv_type != SEVENWIRE)
650 miiphy_restart_aneg(dev);
Troy Kisky13947f42012-02-07 14:08:47 +0000651#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400652 fec_open(dev);
653 return 0;
654}
655
656/**
657 * Halt the FEC engine
658 * @param[in] dev Our device to handle
659 */
Jagan Teki60752ca2016-12-06 00:00:49 +0100660#ifdef CONFIG_DM_ETH
661static void fecmxc_halt(struct udevice *dev)
662#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400663static void fec_halt(struct eth_device *dev)
Jagan Teki60752ca2016-12-06 00:00:49 +0100664#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400665{
Jagan Teki60752ca2016-12-06 00:00:49 +0100666#ifdef CONFIG_DM_ETH
667 struct fec_priv *fec = dev_get_priv(dev);
668#else
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200669 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki60752ca2016-12-06 00:00:49 +0100670#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400671 int counter = 0xffff;
672
Jagan Teki567173a2016-12-06 00:00:50 +0100673 /* issue graceful stop command to the FEC transmitter if necessary */
John Rigbycb17b922010-01-25 23:12:55 -0700674 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
Jagan Teki567173a2016-12-06 00:00:50 +0100675 &fec->eth->x_cntrl);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400676
677 debug("eth_halt: wait for stop regs\n");
Jagan Teki567173a2016-12-06 00:00:50 +0100678 /* wait for graceful stop to register */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400679 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
John Rigbycb17b922010-01-25 23:12:55 -0700680 udelay(1);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400681
Jagan Teki567173a2016-12-06 00:00:50 +0100682 /* Disable SmartDMA tasks */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400683 fec_tx_task_disable(fec);
684 fec_rx_task_disable(fec);
685
686 /*
687 * Disable the Ethernet Controller
688 * Note: this will also reset the BD index counter!
689 */
John Rigby740d6ae2010-01-25 23:12:57 -0700690 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
Jagan Teki567173a2016-12-06 00:00:50 +0100691 &fec->eth->ecntrl);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400692 fec->rbd_index = 0;
693 fec->tbd_index = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400694 debug("eth_halt: done\n");
695}
696
697/**
698 * Transmit one frame
699 * @param[in] dev Our ethernet device to handle
700 * @param[in] packet Pointer to the data to be transmitted
701 * @param[in] length Data count in bytes
702 * @return 0 on success
703 */
Jagan Teki60752ca2016-12-06 00:00:49 +0100704#ifdef CONFIG_DM_ETH
705static int fecmxc_send(struct udevice *dev, void *packet, int length)
706#else
Joe Hershberger442dac42012-05-21 14:45:27 +0000707static int fec_send(struct eth_device *dev, void *packet, int length)
Jagan Teki60752ca2016-12-06 00:00:49 +0100708#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400709{
710 unsigned int status;
Ye Lif24e4822018-01-10 13:20:44 +0800711 u32 size;
712 ulong addr, end;
Marek Vasutbc1ce152012-08-29 03:49:49 +0000713 int timeout = FEC_XFER_TIMEOUT;
714 int ret = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400715
716 /*
717 * This routine transmits one frame. This routine only accepts
718 * 6-byte Ethernet addresses.
719 */
Jagan Teki60752ca2016-12-06 00:00:49 +0100720#ifdef CONFIG_DM_ETH
721 struct fec_priv *fec = dev_get_priv(dev);
722#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400723 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki60752ca2016-12-06 00:00:49 +0100724#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400725
726 /*
727 * Check for valid length of data.
728 */
729 if ((length > 1500) || (length <= 0)) {
Stefano Babic4294b242010-02-01 14:51:30 +0100730 printf("Payload (%d) too large\n", length);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400731 return -1;
732 }
733
734 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000735 * Setup the transmit buffer. We are always using the first buffer for
736 * transmission, the second will be empty and only used to stop the DMA
737 * engine. We also flush the packet to RAM here to avoid cache trouble.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400738 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000739#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Marek Vasutbe7e87e2011-11-08 23:18:10 +0000740 swap_packet((uint32_t *)packet, length);
741#endif
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000742
Ye Lif24e4822018-01-10 13:20:44 +0800743 addr = (ulong)packet;
Marek Vasutefe24d22012-08-26 10:19:21 +0000744 end = roundup(addr + length, ARCH_DMA_MINALIGN);
745 addr &= ~(ARCH_DMA_MINALIGN - 1);
746 flush_dcache_range(addr, end);
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000747
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400748 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
Ye Lif24e4822018-01-10 13:20:44 +0800749 writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000750
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400751 /*
752 * update BD's status now
753 * This block:
754 * - is always the last in a chain (means no chain)
755 * - should transmitt the CRC
756 * - might be the last BD in the list, so the address counter should
757 * wrap (-> keep the WRAP flag)
758 */
759 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
760 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
761 writew(status, &fec->tbd_base[fec->tbd_index].status);
762
763 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000764 * Flush data cache. This code flushes both TX descriptors to RAM.
765 * After this code, the descriptors will be safely in RAM and we
766 * can start DMA.
767 */
768 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
Ye Lif24e4822018-01-10 13:20:44 +0800769 addr = (ulong)fec->tbd_base;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000770 flush_dcache_range(addr, addr + size);
771
772 /*
Marek Vasutab94cd42013-07-12 01:03:04 +0200773 * Below we read the DMA descriptor's last four bytes back from the
774 * DRAM. This is important in order to make sure that all WRITE
775 * operations on the bus that were triggered by previous cache FLUSH
776 * have completed.
777 *
778 * Otherwise, on MX28, it is possible to observe a corruption of the
779 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
780 * for the bus structure of MX28. The scenario is as follows:
781 *
782 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
783 * to DRAM due to flush_dcache_range()
784 * 2) ARM core writes the FEC registers via AHB_ARB2
785 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
786 *
787 * Note that 2) does sometimes finish before 1) due to reordering of
788 * WRITE accesses on the AHB bus, therefore triggering 3) before the
789 * DMA descriptor is fully written into DRAM. This results in occasional
790 * corruption of the DMA descriptor.
791 */
792 readl(addr + size - 4);
793
Jagan Teki567173a2016-12-06 00:00:50 +0100794 /* Enable SmartDMA transmit task */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400795 fec_tx_task_enable(fec);
796
797 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000798 * Wait until frame is sent. On each turn of the wait cycle, we must
799 * invalidate data cache to see what's really in RAM. Also, we need
800 * barrier here.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400801 */
Marek Vasut67449092012-08-29 03:49:50 +0000802 while (--timeout) {
Marek Vasutc0b5a3b2012-08-29 03:49:51 +0000803 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
Marek Vasutbc1ce152012-08-29 03:49:49 +0000804 break;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400805 }
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000806
Fabio Estevamf5992882014-08-25 13:34:17 -0300807 if (!timeout) {
808 ret = -EINVAL;
809 goto out;
810 }
811
812 /*
813 * The TDAR bit is cleared when the descriptors are all out from TX
814 * but on mx6solox we noticed that the READY bit is still not cleared
815 * right after TDAR.
816 * These are two distinct signals, and in IC simulation, we found that
817 * TDAR always gets cleared prior than the READY bit of last BD becomes
818 * cleared.
819 * In mx6solox, we use a later version of FEC IP. It looks like that
820 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
821 * version.
822 *
823 * Fix this by polling the READY bit of BD after the TDAR polling,
824 * which covers the mx6solox case and does not harm the other SoCs.
825 */
826 timeout = FEC_XFER_TIMEOUT;
827 while (--timeout) {
828 invalidate_dcache_range(addr, addr + size);
829 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
830 FEC_TBD_READY))
831 break;
832 }
833
Marek Vasut67449092012-08-29 03:49:50 +0000834 if (!timeout)
835 ret = -EINVAL;
836
Fabio Estevamf5992882014-08-25 13:34:17 -0300837out:
Marek Vasut67449092012-08-29 03:49:50 +0000838 debug("fec_send: status 0x%x index %d ret %i\n",
Jagan Teki567173a2016-12-06 00:00:50 +0100839 readw(&fec->tbd_base[fec->tbd_index].status),
840 fec->tbd_index, ret);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400841 /* for next transmission use the other buffer */
842 if (fec->tbd_index)
843 fec->tbd_index = 0;
844 else
845 fec->tbd_index = 1;
846
Marek Vasutbc1ce152012-08-29 03:49:49 +0000847 return ret;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400848}
849
850/**
851 * Pull one frame from the card
852 * @param[in] dev Our ethernet device to handle
853 * @return Length of packet read
854 */
Jagan Teki60752ca2016-12-06 00:00:49 +0100855#ifdef CONFIG_DM_ETH
856static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
857#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400858static int fec_recv(struct eth_device *dev)
Jagan Teki60752ca2016-12-06 00:00:49 +0100859#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400860{
Jagan Teki60752ca2016-12-06 00:00:49 +0100861#ifdef CONFIG_DM_ETH
862 struct fec_priv *fec = dev_get_priv(dev);
863#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400864 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki60752ca2016-12-06 00:00:49 +0100865#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400866 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
867 unsigned long ievent;
868 int frame_length, len = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400869 uint16_t bd_status;
Ye Lif24e4822018-01-10 13:20:44 +0800870 ulong addr, size, end;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000871 int i;
Ye Li07763ac2018-03-28 20:54:11 +0800872
873#ifdef CONFIG_DM_ETH
874 *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
875 if (*packetp == 0) {
876 printf("%s: error allocating packetp\n", __func__);
877 return -ENOMEM;
878 }
879#else
Fabio Estevamfd37f192013-09-17 23:13:10 -0300880 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
Ye Li07763ac2018-03-28 20:54:11 +0800881#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400882
Jagan Teki567173a2016-12-06 00:00:50 +0100883 /* Check if any critical events have happened */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400884 ievent = readl(&fec->eth->ievent);
885 writel(ievent, &fec->eth->ievent);
Marek Vasuteda959f2011-10-24 23:40:03 +0000886 debug("fec_recv: ievent 0x%lx\n", ievent);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400887 if (ievent & FEC_IEVENT_BABR) {
Jagan Teki60752ca2016-12-06 00:00:49 +0100888#ifdef CONFIG_DM_ETH
889 fecmxc_halt(dev);
890 fecmxc_init(dev);
891#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400892 fec_halt(dev);
893 fec_init(dev, fec->bd);
Jagan Teki60752ca2016-12-06 00:00:49 +0100894#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400895 printf("some error: 0x%08lx\n", ievent);
896 return 0;
897 }
898 if (ievent & FEC_IEVENT_HBERR) {
899 /* Heartbeat error */
900 writel(0x00000001 | readl(&fec->eth->x_cntrl),
Jagan Teki567173a2016-12-06 00:00:50 +0100901 &fec->eth->x_cntrl);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400902 }
903 if (ievent & FEC_IEVENT_GRA) {
904 /* Graceful stop complete */
905 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
Jagan Teki60752ca2016-12-06 00:00:49 +0100906#ifdef CONFIG_DM_ETH
907 fecmxc_halt(dev);
908#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400909 fec_halt(dev);
Jagan Teki60752ca2016-12-06 00:00:49 +0100910#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400911 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
Jagan Teki567173a2016-12-06 00:00:50 +0100912 &fec->eth->x_cntrl);
Jagan Teki60752ca2016-12-06 00:00:49 +0100913#ifdef CONFIG_DM_ETH
914 fecmxc_init(dev);
915#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400916 fec_init(dev, fec->bd);
Jagan Teki60752ca2016-12-06 00:00:49 +0100917#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400918 }
919 }
920
921 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000922 * Read the buffer status. Before the status can be read, the data cache
923 * must be invalidated, because the data in RAM might have been changed
924 * by DMA. The descriptors are properly aligned to cachelines so there's
925 * no need to worry they'd overlap.
926 *
927 * WARNING: By invalidating the descriptor here, we also invalidate
928 * the descriptors surrounding this one. Therefore we can NOT change the
929 * contents of this descriptor nor the surrounding ones. The problem is
930 * that in order to mark the descriptor as processed, we need to change
931 * the descriptor. The solution is to mark the whole cache line when all
932 * descriptors in the cache line are processed.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400933 */
Ye Lif24e4822018-01-10 13:20:44 +0800934 addr = (ulong)rbd;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000935 addr &= ~(ARCH_DMA_MINALIGN - 1);
936 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
937 invalidate_dcache_range(addr, addr + size);
938
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400939 bd_status = readw(&rbd->status);
940 debug("fec_recv: status 0x%x\n", bd_status);
941
942 if (!(bd_status & FEC_RBD_EMPTY)) {
943 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
Jagan Teki567173a2016-12-06 00:00:50 +0100944 ((readw(&rbd->data_length) - 4) > 14)) {
945 /* Get buffer address and size */
Albert ARIBAUD \(3ADEV\)b1895842015-06-19 14:18:27 +0200946 addr = readl(&rbd->data_pointer);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400947 frame_length = readw(&rbd->data_length) - 4;
Jagan Teki567173a2016-12-06 00:00:50 +0100948 /* Invalidate data cache over the buffer */
Marek Vasutefe24d22012-08-26 10:19:21 +0000949 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
950 addr &= ~(ARCH_DMA_MINALIGN - 1);
951 invalidate_dcache_range(addr, end);
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000952
Jagan Teki567173a2016-12-06 00:00:50 +0100953 /* Fill the buffer and pass it to upper layers */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000954#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Albert ARIBAUD \(3ADEV\)b1895842015-06-19 14:18:27 +0200955 swap_packet((uint32_t *)addr, frame_length);
Marek Vasutbe7e87e2011-11-08 23:18:10 +0000956#endif
Ye Li07763ac2018-03-28 20:54:11 +0800957
958#ifdef CONFIG_DM_ETH
959 memcpy(*packetp, (char *)addr, frame_length);
960#else
Albert ARIBAUD \(3ADEV\)b1895842015-06-19 14:18:27 +0200961 memcpy(buff, (char *)addr, frame_length);
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500962 net_process_received_packet(buff, frame_length);
Ye Li07763ac2018-03-28 20:54:11 +0800963#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400964 len = frame_length;
965 } else {
966 if (bd_status & FEC_RBD_ERR)
Ye Lif24e4822018-01-10 13:20:44 +0800967 debug("error frame: 0x%08lx 0x%08x\n",
968 addr, bd_status);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400969 }
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000970
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400971 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000972 * Free the current buffer, restart the engine and move forward
973 * to the next buffer. Here we check if the whole cacheline of
974 * descriptors was already processed and if so, we mark it free
975 * as whole.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400976 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000977 size = RXDESC_PER_CACHELINE - 1;
978 if ((fec->rbd_index & size) == size) {
979 i = fec->rbd_index - size;
Ye Lif24e4822018-01-10 13:20:44 +0800980 addr = (ulong)&fec->rbd_base[i];
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000981 for (; i <= fec->rbd_index ; i++) {
982 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
983 &fec->rbd_base[i]);
984 }
985 flush_dcache_range(addr,
Jagan Teki567173a2016-12-06 00:00:50 +0100986 addr + ARCH_DMA_MINALIGN);
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000987 }
988
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400989 fec_rx_task_enable(fec);
990 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
991 }
992 debug("fec_recv: stop\n");
993
994 return len;
995}
996
Troy Kiskyef8e3a32012-10-22 16:40:44 +0000997static void fec_set_dev_name(char *dest, int dev_id)
998{
999 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
1000}
1001
Marek Vasut79e5f272013-10-12 20:36:25 +02001002static int fec_alloc_descs(struct fec_priv *fec)
1003{
1004 unsigned int size;
1005 int i;
1006 uint8_t *data;
Ye Lif24e4822018-01-10 13:20:44 +08001007 ulong addr;
Marek Vasut79e5f272013-10-12 20:36:25 +02001008
1009 /* Allocate TX descriptors. */
1010 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
1011 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
1012 if (!fec->tbd_base)
1013 goto err_tx;
1014
1015 /* Allocate RX descriptors. */
1016 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
1017 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
1018 if (!fec->rbd_base)
1019 goto err_rx;
1020
1021 memset(fec->rbd_base, 0, size);
1022
1023 /* Allocate RX buffers. */
1024
1025 /* Maximum RX buffer size. */
Fabio Estevamdb5b7f52014-08-25 13:34:16 -03001026 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
Marek Vasut79e5f272013-10-12 20:36:25 +02001027 for (i = 0; i < FEC_RBD_NUM; i++) {
Fabio Estevamdb5b7f52014-08-25 13:34:16 -03001028 data = memalign(FEC_DMA_RX_MINALIGN, size);
Marek Vasut79e5f272013-10-12 20:36:25 +02001029 if (!data) {
1030 printf("%s: error allocating rxbuf %d\n", __func__, i);
1031 goto err_ring;
1032 }
1033
1034 memset(data, 0, size);
1035
Ye Lif24e4822018-01-10 13:20:44 +08001036 addr = (ulong)data;
1037 fec->rbd_base[i].data_pointer = (uint32_t)addr;
Marek Vasut79e5f272013-10-12 20:36:25 +02001038 fec->rbd_base[i].status = FEC_RBD_EMPTY;
1039 fec->rbd_base[i].data_length = 0;
1040 /* Flush the buffer to memory. */
Ye Lif24e4822018-01-10 13:20:44 +08001041 flush_dcache_range(addr, addr + size);
Marek Vasut79e5f272013-10-12 20:36:25 +02001042 }
1043
1044 /* Mark the last RBD to close the ring. */
1045 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
1046
1047 fec->rbd_index = 0;
1048 fec->tbd_index = 0;
1049
1050 return 0;
1051
1052err_ring:
Ye Lif24e4822018-01-10 13:20:44 +08001053 for (; i >= 0; i--) {
1054 addr = fec->rbd_base[i].data_pointer;
1055 free((void *)addr);
1056 }
Marek Vasut79e5f272013-10-12 20:36:25 +02001057 free(fec->rbd_base);
1058err_rx:
1059 free(fec->tbd_base);
1060err_tx:
1061 return -ENOMEM;
1062}
1063
1064static void fec_free_descs(struct fec_priv *fec)
1065{
1066 int i;
Ye Lif24e4822018-01-10 13:20:44 +08001067 ulong addr;
Marek Vasut79e5f272013-10-12 20:36:25 +02001068
Ye Lif24e4822018-01-10 13:20:44 +08001069 for (i = 0; i < FEC_RBD_NUM; i++) {
1070 addr = fec->rbd_base[i].data_pointer;
1071 free((void *)addr);
1072 }
Marek Vasut79e5f272013-10-12 20:36:25 +02001073 free(fec->rbd_base);
1074 free(fec->tbd_base);
1075}
1076
Peng Fan1bcabd72018-03-28 20:54:12 +08001077struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
Jagan Teki60752ca2016-12-06 00:00:49 +01001078{
Peng Fan1bcabd72018-03-28 20:54:12 +08001079 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
Jagan Teki60752ca2016-12-06 00:00:49 +01001080 struct mii_dev *bus;
1081 int ret;
1082
1083 bus = mdio_alloc();
1084 if (!bus) {
1085 printf("mdio_alloc failed\n");
1086 return NULL;
1087 }
1088 bus->read = fec_phy_read;
1089 bus->write = fec_phy_write;
1090 bus->priv = eth;
1091 fec_set_dev_name(bus->name, dev_id);
1092
1093 ret = mdio_register(bus);
1094 if (ret) {
1095 printf("mdio_register failed\n");
1096 free(bus);
1097 return NULL;
1098 }
1099 fec_mii_setspeed(eth);
1100 return bus;
1101}
1102
1103#ifndef CONFIG_DM_ETH
Troy Kiskyfe428b92012-10-22 16:40:46 +00001104#ifdef CONFIG_PHYLIB
1105int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1106 struct mii_dev *bus, struct phy_device *phydev)
1107#else
1108static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1109 struct mii_dev *bus, int phy_id)
1110#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001111{
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001112 struct eth_device *edev;
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001113 struct fec_priv *fec;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001114 unsigned char ethaddr[6];
Andy Duan979a5892017-04-10 19:44:35 +08001115 char mac[16];
Marek Vasute382fb42011-09-11 18:05:37 +00001116 uint32_t start;
1117 int ret = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001118
1119 /* create and fill edev struct */
1120 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
1121 if (!edev) {
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001122 puts("fec_mxc: not enough malloc memory for eth_device\n");
Marek Vasute382fb42011-09-11 18:05:37 +00001123 ret = -ENOMEM;
1124 goto err1;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001125 }
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001126
1127 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
1128 if (!fec) {
1129 puts("fec_mxc: not enough malloc memory for fec_priv\n");
Marek Vasute382fb42011-09-11 18:05:37 +00001130 ret = -ENOMEM;
1131 goto err2;
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001132 }
1133
Nobuhiro Iwamatsude0b9572010-10-19 14:03:42 +09001134 memset(edev, 0, sizeof(*edev));
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001135 memset(fec, 0, sizeof(*fec));
1136
Marek Vasut79e5f272013-10-12 20:36:25 +02001137 ret = fec_alloc_descs(fec);
1138 if (ret)
1139 goto err3;
1140
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001141 edev->priv = fec;
1142 edev->init = fec_init;
1143 edev->send = fec_send;
1144 edev->recv = fec_recv;
1145 edev->halt = fec_halt;
Heiko Schocherfb57ec92010-04-27 07:43:52 +02001146 edev->write_hwaddr = fec_set_hwaddr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001147
Ye Lif24e4822018-01-10 13:20:44 +08001148 fec->eth = (struct ethernet_regs *)(ulong)base_addr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001149 fec->bd = bd;
1150
Marek Vasut392b8502011-09-11 18:05:33 +00001151 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001152
1153 /* Reset chip. */
John Rigbycb17b922010-01-25 23:12:55 -07001154 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
Marek Vasute382fb42011-09-11 18:05:37 +00001155 start = get_timer(0);
1156 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1157 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
Vagrant Cascadian3450a852016-10-23 20:45:19 -07001158 printf("FEC MXC: Timeout resetting chip\n");
Marek Vasut79e5f272013-10-12 20:36:25 +02001159 goto err4;
Marek Vasute382fb42011-09-11 18:05:37 +00001160 }
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001161 udelay(10);
Marek Vasute382fb42011-09-11 18:05:37 +00001162 }
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001163
Marek Vasuta5990b22012-05-01 11:09:41 +00001164 fec_reg_setup(fec);
Troy Kiskyef8e3a32012-10-22 16:40:44 +00001165 fec_set_dev_name(edev->name, dev_id);
1166 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
Troy Kisky13947f42012-02-07 14:08:47 +00001167 fec->bus = bus;
Troy Kiskyfe428b92012-10-22 16:40:46 +00001168 fec_mii_setspeed(bus->priv);
1169#ifdef CONFIG_PHYLIB
1170 fec->phydev = phydev;
1171 phy_connect_dev(phydev, edev);
1172 /* Configure phy */
1173 phy_config(phydev);
1174#else
1175 fec->phy_id = phy_id;
1176#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001177 eth_register(edev);
Andy Duan979a5892017-04-10 19:44:35 +08001178 /* only support one eth device, the index number pointed by dev_id */
1179 edev->index = fec->dev_id;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001180
Andy Duanf01e4e12017-04-10 19:44:34 +08001181 if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
1182 debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
Stefano Babic4294b242010-02-01 14:51:30 +01001183 memcpy(edev->enetaddr, ethaddr, 6);
Andy Duan979a5892017-04-10 19:44:35 +08001184 if (fec->dev_id)
1185 sprintf(mac, "eth%daddr", fec->dev_id);
1186 else
1187 strcpy(mac, "ethaddr");
Simon Glass00caae62017-08-03 12:22:12 -06001188 if (!env_get(mac))
Simon Glassfd1e9592017-08-03 12:22:11 -06001189 eth_env_set_enetaddr(mac, ethaddr);
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001190 }
Marek Vasute382fb42011-09-11 18:05:37 +00001191 return ret;
Marek Vasut79e5f272013-10-12 20:36:25 +02001192err4:
1193 fec_free_descs(fec);
Marek Vasute382fb42011-09-11 18:05:37 +00001194err3:
1195 free(fec);
1196err2:
1197 free(edev);
1198err1:
1199 return ret;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001200}
1201
Troy Kiskyeef24482012-10-22 16:40:42 +00001202int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1203{
Troy Kiskyfe428b92012-10-22 16:40:46 +00001204 uint32_t base_mii;
1205 struct mii_dev *bus = NULL;
1206#ifdef CONFIG_PHYLIB
1207 struct phy_device *phydev = NULL;
1208#endif
1209 int ret;
1210
Peng Fan3b26d522020-05-01 22:08:37 +08001211 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
1212 if (enet_fused((ulong)addr)) {
1213 printf("SoC fuse indicates Ethernet@0x%x is unavailable.\n", addr);
1214 return -ENODEV;
1215 }
1216 }
1217
Peng Fanfbada482018-03-28 20:54:14 +08001218#ifdef CONFIG_FEC_MXC_MDIO_BASE
Troy Kiskyfe428b92012-10-22 16:40:46 +00001219 /*
1220 * The i.MX28 has two ethernet interfaces, but they are not equal.
1221 * Only the first one can access the MDIO bus.
1222 */
Peng Fanfbada482018-03-28 20:54:14 +08001223 base_mii = CONFIG_FEC_MXC_MDIO_BASE;
Troy Kiskyfe428b92012-10-22 16:40:46 +00001224#else
1225 base_mii = addr;
1226#endif
Troy Kiskyeef24482012-10-22 16:40:42 +00001227 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
Troy Kiskyfe428b92012-10-22 16:40:46 +00001228 bus = fec_get_miibus(base_mii, dev_id);
1229 if (!bus)
1230 return -ENOMEM;
1231#ifdef CONFIG_PHYLIB
1232 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1233 if (!phydev) {
Måns Rullgård845a57b2015-12-08 15:38:46 +00001234 mdio_unregister(bus);
Troy Kiskyfe428b92012-10-22 16:40:46 +00001235 free(bus);
1236 return -ENOMEM;
1237 }
1238 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1239#else
1240 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1241#endif
1242 if (ret) {
1243#ifdef CONFIG_PHYLIB
1244 free(phydev);
1245#endif
Måns Rullgård845a57b2015-12-08 15:38:46 +00001246 mdio_unregister(bus);
Troy Kiskyfe428b92012-10-22 16:40:46 +00001247 free(bus);
1248 }
1249 return ret;
Troy Kiskyeef24482012-10-22 16:40:42 +00001250}
1251
Troy Kisky09439c32012-10-22 16:40:40 +00001252#ifdef CONFIG_FEC_MXC_PHYADDR
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001253int fecmxc_initialize(bd_t *bd)
1254{
Troy Kiskyeef24482012-10-22 16:40:42 +00001255 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1256 IMX_FEC_BASE);
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001257}
1258#endif
1259
Troy Kisky13947f42012-02-07 14:08:47 +00001260#ifndef CONFIG_PHYLIB
Marek Vasut2e5f4422011-09-11 18:05:36 +00001261int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1262{
1263 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1264 fec->mii_postcall = cb;
1265 return 0;
1266}
Troy Kisky13947f42012-02-07 14:08:47 +00001267#endif
Jagan Teki60752ca2016-12-06 00:00:49 +01001268
1269#else
1270
Jagan Teki1ed25702016-12-06 00:00:51 +01001271static int fecmxc_read_rom_hwaddr(struct udevice *dev)
1272{
1273 struct fec_priv *priv = dev_get_priv(dev);
1274 struct eth_pdata *pdata = dev_get_platdata(dev);
1275
1276 return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
1277}
1278
Ye Li07763ac2018-03-28 20:54:11 +08001279static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
1280{
1281 if (packet)
1282 free(packet);
1283
1284 return 0;
1285}
1286
Jagan Teki60752ca2016-12-06 00:00:49 +01001287static const struct eth_ops fecmxc_ops = {
1288 .start = fecmxc_init,
1289 .send = fecmxc_send,
1290 .recv = fecmxc_recv,
Ye Li07763ac2018-03-28 20:54:11 +08001291 .free_pkt = fecmxc_free_pkt,
Jagan Teki60752ca2016-12-06 00:00:49 +01001292 .stop = fecmxc_halt,
1293 .write_hwaddr = fecmxc_set_hwaddr,
Jagan Teki1ed25702016-12-06 00:00:51 +01001294 .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
Jagan Teki60752ca2016-12-06 00:00:49 +01001295};
1296
Martyn Welch774ec602018-12-11 11:34:45 +00001297static int device_get_phy_addr(struct udevice *dev)
1298{
1299 struct ofnode_phandle_args phandle_args;
1300 int reg;
1301
1302 if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1303 &phandle_args)) {
1304 debug("Failed to find phy-handle");
1305 return -ENODEV;
1306 }
1307
1308 reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
1309
1310 return reg;
1311}
1312
Jagan Teki60752ca2016-12-06 00:00:49 +01001313static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
1314{
1315 struct phy_device *phydev;
Martyn Welch774ec602018-12-11 11:34:45 +00001316 int addr;
Jagan Teki60752ca2016-12-06 00:00:49 +01001317
Martyn Welch774ec602018-12-11 11:34:45 +00001318 addr = device_get_phy_addr(dev);
Lukasz Majewski178d4f02018-04-15 21:45:54 +02001319#ifdef CONFIG_FEC_MXC_PHYADDR
Hannes Schmelzerb8820052019-02-15 10:30:18 +01001320 addr = CONFIG_FEC_MXC_PHYADDR;
Jagan Teki60752ca2016-12-06 00:00:49 +01001321#endif
1322
Hannes Schmelzerb8820052019-02-15 10:30:18 +01001323 phydev = phy_connect(priv->bus, addr, dev, priv->interface);
Jagan Teki60752ca2016-12-06 00:00:49 +01001324 if (!phydev)
1325 return -ENODEV;
1326
Jagan Teki60752ca2016-12-06 00:00:49 +01001327 priv->phydev = phydev;
1328 phy_config(phydev);
1329
1330 return 0;
1331}
1332
Simon Glassbcee8d62019-12-06 21:41:35 -07001333#if CONFIG_IS_ENABLED(DM_GPIO)
Michael Trimarchiefd0b792018-06-17 15:22:39 +02001334/* FEC GPIO reset */
1335static void fec_gpio_reset(struct fec_priv *priv)
1336{
1337 debug("fec_gpio_reset: fec_gpio_reset(dev)\n");
1338 if (dm_gpio_is_valid(&priv->phy_reset_gpio)) {
1339 dm_gpio_set_value(&priv->phy_reset_gpio, 1);
Martin Fuzzey9b8b9182018-10-04 19:59:18 +02001340 mdelay(priv->reset_delay);
Michael Trimarchiefd0b792018-06-17 15:22:39 +02001341 dm_gpio_set_value(&priv->phy_reset_gpio, 0);
Andrejs Cainikovs31d40452019-03-01 13:27:59 +00001342 if (priv->reset_post_delay)
1343 mdelay(priv->reset_post_delay);
Michael Trimarchiefd0b792018-06-17 15:22:39 +02001344 }
1345}
1346#endif
1347
Jagan Teki60752ca2016-12-06 00:00:49 +01001348static int fecmxc_probe(struct udevice *dev)
1349{
1350 struct eth_pdata *pdata = dev_get_platdata(dev);
1351 struct fec_priv *priv = dev_get_priv(dev);
1352 struct mii_dev *bus = NULL;
Jagan Teki60752ca2016-12-06 00:00:49 +01001353 uint32_t start;
1354 int ret;
1355
Peng Fan3b26d522020-05-01 22:08:37 +08001356 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
1357 if (enet_fused((ulong)priv->eth)) {
1358 printf("SoC fuse indicates Ethernet@0x%lx is unavailable.\n", (ulong)priv->eth);
1359 return -ENODEV;
1360 }
1361 }
1362
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +02001363 if (IS_ENABLED(CONFIG_IMX8)) {
1364 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1365 if (ret < 0) {
1366 debug("Can't get FEC ipg clk: %d\n", ret);
1367 return ret;
1368 }
1369 ret = clk_enable(&priv->ipg_clk);
1370 if (ret < 0) {
1371 debug("Can't enable FEC ipg clk: %d\n", ret);
1372 return ret;
1373 }
1374
1375 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
Peng Fan673f6592019-10-25 09:48:02 +00001376 } else if (CONFIG_IS_ENABLED(CLK_CCF)) {
1377 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1378 if (ret < 0) {
1379 debug("Can't get FEC ipg clk: %d\n", ret);
1380 return ret;
1381 }
1382 ret = clk_enable(&priv->ipg_clk);
1383 if(ret)
1384 return ret;
1385
1386 ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
1387 if (ret < 0) {
1388 debug("Can't get FEC ahb clk: %d\n", ret);
1389 return ret;
1390 }
1391 ret = clk_enable(&priv->ahb_clk);
1392 if (ret)
1393 return ret;
1394
1395 ret = clk_get_by_name(dev, "enet_out", &priv->clk_enet_out);
1396 if (!ret) {
1397 ret = clk_enable(&priv->clk_enet_out);
1398 if (ret)
1399 return ret;
1400 }
1401
1402 ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref);
1403 if (!ret) {
1404 ret = clk_enable(&priv->clk_ref);
1405 if (ret)
1406 return ret;
1407 }
1408
1409 ret = clk_get_by_name(dev, "ptp", &priv->clk_ptp);
1410 if (!ret) {
1411 ret = clk_enable(&priv->clk_ptp);
1412 if (ret)
1413 return ret;
1414 }
1415
1416 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +02001417 }
1418
Jagan Teki60752ca2016-12-06 00:00:49 +01001419 ret = fec_alloc_descs(priv);
1420 if (ret)
1421 return ret;
1422
Martin Fuzzeyad8c43c2018-10-04 19:59:20 +02001423#ifdef CONFIG_DM_REGULATOR
1424 if (priv->phy_supply) {
Adam Ford8f1a5ac2019-01-15 11:26:48 -06001425 ret = regulator_set_enable(priv->phy_supply, true);
Martin Fuzzeyad8c43c2018-10-04 19:59:20 +02001426 if (ret) {
1427 printf("%s: Error enabling phy supply\n", dev->name);
1428 return ret;
1429 }
1430 }
1431#endif
1432
Simon Glassbcee8d62019-12-06 21:41:35 -07001433#if CONFIG_IS_ENABLED(DM_GPIO)
Michael Trimarchiefd0b792018-06-17 15:22:39 +02001434 fec_gpio_reset(priv);
1435#endif
Jagan Teki60752ca2016-12-06 00:00:49 +01001436 /* Reset chip. */
Jagan Teki567173a2016-12-06 00:00:50 +01001437 writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
1438 &priv->eth->ecntrl);
Jagan Teki60752ca2016-12-06 00:00:49 +01001439 start = get_timer(0);
1440 while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
1441 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1442 printf("FEC MXC: Timeout reseting chip\n");
1443 goto err_timeout;
1444 }
1445 udelay(10);
1446 }
1447
1448 fec_reg_setup(priv);
Jagan Teki60752ca2016-12-06 00:00:49 +01001449
Peng Fan8b203862018-03-28 20:54:13 +08001450 priv->dev_id = dev->seq;
Ye Li6a895d02020-05-03 22:41:15 +08001451
1452#ifdef CONFIG_DM_ETH_PHY
1453 bus = eth_phy_get_mdio_bus(dev);
Peng Fanfbada482018-03-28 20:54:14 +08001454#endif
Ye Li6a895d02020-05-03 22:41:15 +08001455
1456 if (!bus) {
1457#ifdef CONFIG_FEC_MXC_MDIO_BASE
1458 bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq);
1459#else
1460 bus = fec_get_miibus((ulong)priv->eth, dev->seq);
1461#endif
1462 }
Lothar Waßmann306dd7d2017-06-27 15:23:16 +02001463 if (!bus) {
1464 ret = -ENOMEM;
1465 goto err_mii;
1466 }
1467
Ye Li6a895d02020-05-03 22:41:15 +08001468#ifdef CONFIG_DM_ETH_PHY
1469 eth_phy_set_mdio_bus(dev, bus);
1470#endif
1471
Lothar Waßmann306dd7d2017-06-27 15:23:16 +02001472 priv->bus = bus;
Lothar Waßmann306dd7d2017-06-27 15:23:16 +02001473 priv->interface = pdata->phy_interface;
Martin Fuzzey0126c642018-10-04 19:59:21 +02001474 switch (priv->interface) {
1475 case PHY_INTERFACE_MODE_MII:
1476 priv->xcv_type = MII100;
1477 break;
1478 case PHY_INTERFACE_MODE_RMII:
1479 priv->xcv_type = RMII;
1480 break;
1481 case PHY_INTERFACE_MODE_RGMII:
1482 case PHY_INTERFACE_MODE_RGMII_ID:
1483 case PHY_INTERFACE_MODE_RGMII_RXID:
1484 case PHY_INTERFACE_MODE_RGMII_TXID:
1485 priv->xcv_type = RGMII;
1486 break;
1487 default:
1488 priv->xcv_type = CONFIG_FEC_XCV_TYPE;
1489 printf("Unsupported interface type %d defaulting to %d\n",
1490 priv->interface, priv->xcv_type);
1491 break;
1492 }
1493
Lothar Waßmann306dd7d2017-06-27 15:23:16 +02001494 ret = fec_phy_init(priv, dev);
1495 if (ret)
1496 goto err_phy;
1497
Jagan Teki60752ca2016-12-06 00:00:49 +01001498 return 0;
1499
Jagan Teki60752ca2016-12-06 00:00:49 +01001500err_phy:
1501 mdio_unregister(bus);
1502 free(bus);
1503err_mii:
Ye Li2087eac2018-03-28 20:54:16 +08001504err_timeout:
Jagan Teki60752ca2016-12-06 00:00:49 +01001505 fec_free_descs(priv);
1506 return ret;
1507}
1508
1509static int fecmxc_remove(struct udevice *dev)
1510{
1511 struct fec_priv *priv = dev_get_priv(dev);
1512
1513 free(priv->phydev);
1514 fec_free_descs(priv);
1515 mdio_unregister(priv->bus);
1516 mdio_free(priv->bus);
1517
Martin Fuzzeyad8c43c2018-10-04 19:59:20 +02001518#ifdef CONFIG_DM_REGULATOR
1519 if (priv->phy_supply)
1520 regulator_set_enable(priv->phy_supply, false);
1521#endif
1522
Jagan Teki60752ca2016-12-06 00:00:49 +01001523 return 0;
1524}
1525
1526static int fecmxc_ofdata_to_platdata(struct udevice *dev)
1527{
Michael Trimarchiefd0b792018-06-17 15:22:39 +02001528 int ret = 0;
Jagan Teki60752ca2016-12-06 00:00:49 +01001529 struct eth_pdata *pdata = dev_get_platdata(dev);
1530 struct fec_priv *priv = dev_get_priv(dev);
1531 const char *phy_mode;
1532
Simon Glassa821c4a2017-05-17 17:18:05 -06001533 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
Jagan Teki60752ca2016-12-06 00:00:49 +01001534 priv->eth = (struct ethernet_regs *)pdata->iobase;
1535
1536 pdata->phy_interface = -1;
Simon Glasse160f7d2017-01-17 16:52:55 -07001537 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1538 NULL);
Jagan Teki60752ca2016-12-06 00:00:49 +01001539 if (phy_mode)
1540 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1541 if (pdata->phy_interface == -1) {
1542 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1543 return -EINVAL;
1544 }
1545
Martin Fuzzeyad8c43c2018-10-04 19:59:20 +02001546#ifdef CONFIG_DM_REGULATOR
1547 device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
1548#endif
1549
Simon Glassbcee8d62019-12-06 21:41:35 -07001550#if CONFIG_IS_ENABLED(DM_GPIO)
Michael Trimarchiefd0b792018-06-17 15:22:39 +02001551 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
Martin Fuzzey331fcab2018-10-04 19:59:19 +02001552 &priv->phy_reset_gpio, GPIOD_IS_OUT);
1553 if (ret < 0)
1554 return 0; /* property is optional, don't return error! */
Jagan Teki60752ca2016-12-06 00:00:49 +01001555
Martin Fuzzey331fcab2018-10-04 19:59:19 +02001556 priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1);
Michael Trimarchiefd0b792018-06-17 15:22:39 +02001557 if (priv->reset_delay > 1000) {
Martin Fuzzey331fcab2018-10-04 19:59:19 +02001558 printf("FEC MXC: phy reset duration should be <= 1000ms\n");
1559 /* property value wrong, use default value */
1560 priv->reset_delay = 1;
Michael Trimarchiefd0b792018-06-17 15:22:39 +02001561 }
Andrejs Cainikovs31d40452019-03-01 13:27:59 +00001562
1563 priv->reset_post_delay = dev_read_u32_default(dev,
1564 "phy-reset-post-delay",
1565 0);
1566 if (priv->reset_post_delay > 1000) {
1567 printf("FEC MXC: phy reset post delay should be <= 1000ms\n");
1568 /* property value wrong, use default value */
1569 priv->reset_post_delay = 0;
1570 }
Michael Trimarchiefd0b792018-06-17 15:22:39 +02001571#endif
1572
Martin Fuzzey331fcab2018-10-04 19:59:19 +02001573 return 0;
Jagan Teki60752ca2016-12-06 00:00:49 +01001574}
1575
1576static const struct udevice_id fecmxc_ids[] = {
Lukasz Majewski7782f4e2019-06-19 17:31:03 +02001577 { .compatible = "fsl,imx28-fec" },
Jagan Teki60752ca2016-12-06 00:00:49 +01001578 { .compatible = "fsl,imx6q-fec" },
Peng Fan979e0fc2018-03-28 20:54:15 +08001579 { .compatible = "fsl,imx6sl-fec" },
1580 { .compatible = "fsl,imx6sx-fec" },
1581 { .compatible = "fsl,imx6ul-fec" },
Lukasz Majewski948239e2018-04-15 21:54:22 +02001582 { .compatible = "fsl,imx53-fec" },
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +02001583 { .compatible = "fsl,imx7d-fec" },
Lukasz Majewski27589e72019-02-13 22:46:38 +01001584 { .compatible = "fsl,mvf600-fec" },
Jagan Teki60752ca2016-12-06 00:00:49 +01001585 { }
1586};
1587
1588U_BOOT_DRIVER(fecmxc_gem) = {
1589 .name = "fecmxc",
1590 .id = UCLASS_ETH,
1591 .of_match = fecmxc_ids,
1592 .ofdata_to_platdata = fecmxc_ofdata_to_platdata,
1593 .probe = fecmxc_probe,
1594 .remove = fecmxc_remove,
1595 .ops = &fecmxc_ops,
1596 .priv_auto_alloc_size = sizeof(struct fec_priv),
1597 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1598};
1599#endif