Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 1 | /* |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 2 | * (C) Copyright 2007-2009 DENX Software Engineering |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #include <common.h> |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 25 | #include <asm/bitops.h> |
| 26 | #include <command.h> |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 27 | #include <asm/io.h> |
John Rigby | 8a49042 | 2008-08-28 13:17:07 -0600 | [diff] [blame] | 28 | #include <asm/processor.h> |
Wolfgang Denk | e343ab8 | 2008-01-13 00:55:47 +0100 | [diff] [blame] | 29 | #include <fdt_support.h> |
Martha Marx | f31c49d | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 30 | #ifdef CONFIG_MISC_INIT_R |
| 31 | #include <i2c.h> |
| 32 | #endif |
Wolfgang Denk | 9b55a25 | 2008-07-11 01:16:00 +0200 | [diff] [blame] | 33 | |
Ralph Kondziella | 70a4da4 | 2009-01-26 12:34:36 -0700 | [diff] [blame] | 34 | DECLARE_GLOBAL_DATA_PTR; |
| 35 | |
Wolfgang Denk | 72601d0 | 2009-05-16 10:47:41 +0200 | [diff] [blame] | 36 | extern int mpc5121_diu_init(void); |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 37 | extern void ide_set_reset(int idereset); |
Wolfgang Denk | 72601d0 | 2009-05-16 10:47:41 +0200 | [diff] [blame] | 38 | |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 39 | /* Clocks in use */ |
| 40 | #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ |
| 41 | CLOCK_SCCR1_LPC_EN | \ |
| 42 | CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ |
| 43 | CLOCK_SCCR1_PSCFIFO_EN | \ |
| 44 | CLOCK_SCCR1_DDR_EN | \ |
Wolfgang Denk | 8d10307 | 2008-01-13 23:37:50 +0100 | [diff] [blame] | 45 | CLOCK_SCCR1_FEC_EN | \ |
Ralph Kondziella | 70a4da4 | 2009-01-26 12:34:36 -0700 | [diff] [blame] | 46 | CLOCK_SCCR1_PATA_EN | \ |
John Rigby | 5f91db7 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 47 | CLOCK_SCCR1_PCI_EN | \ |
Wolfgang Denk | 8d10307 | 2008-01-13 23:37:50 +0100 | [diff] [blame] | 48 | CLOCK_SCCR1_TPR_EN) |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 49 | |
| 50 | #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ |
| 51 | CLOCK_SCCR2_SPDIF_EN | \ |
York Sun | 0e1bad4 | 2008-05-05 10:20:01 -0500 | [diff] [blame] | 52 | CLOCK_SCCR2_DIU_EN | \ |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 53 | CLOCK_SCCR2_I2C_EN) |
| 54 | |
| 55 | #define CSAW_START(start) ((start) & 0xFFFF0000) |
| 56 | #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) |
| 57 | |
| 58 | long int fixed_sdram(void); |
| 59 | |
| 60 | int board_early_init_f (void) |
| 61 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 62 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 63 | u32 lpcaw, spridr; |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 64 | |
| 65 | /* |
| 66 | * Initialize Local Window for the CPLD registers access (CS2 selects |
| 67 | * the CPLD chip) |
| 68 | */ |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 69 | out_be32(&im->sysconf.lpcs2aw, |
| 70 | CSAW_START(CONFIG_SYS_CPLD_BASE) | |
| 71 | CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE) |
| 72 | ); |
| 73 | out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG); |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 74 | |
| 75 | /* |
| 76 | * According to MPC5121e RM, configuring local access windows should |
| 77 | * be followed by a dummy read of the config register that was |
| 78 | * modified last and an isync |
| 79 | */ |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 80 | lpcaw = in_be32(&im->sysconf.lpcs6aw); |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 81 | __asm__ __volatile__ ("isync"); |
| 82 | |
| 83 | /* |
| 84 | * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control |
| 85 | * |
| 86 | * Without this the flash identification routine fails, as it needs to issue |
| 87 | * write commands in order to establish the device ID. |
| 88 | */ |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 89 | |
Martha Marx | f31c49d | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 90 | #ifdef CONFIG_ADS5121_REV2 |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 91 | out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1); |
Martha Marx | f31c49d | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 92 | #else |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 93 | if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) { |
| 94 | out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1); |
Martha Marx | f31c49d | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 95 | } else { |
| 96 | /* running from Backup flash */ |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 97 | out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32); |
Martha Marx | f31c49d | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 98 | } |
| 99 | #endif |
| 100 | /* |
| 101 | * Configure Flash Speed |
| 102 | */ |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 103 | out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG); |
| 104 | |
| 105 | spridr = in_be32(&im->sysconf.spridr); |
| 106 | |
| 107 | if (SVR_MJREV (spridr) >= 2) |
| 108 | out_be32 (&im->lpc.altr, CONFIG_SYS_CS_ALETIMING); |
| 109 | |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 110 | /* |
| 111 | * Enable clocks |
| 112 | */ |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 113 | out_be32 (&im->clk.sccr[0], SCCR1_CLOCKS_EN); |
| 114 | out_be32 (&im->clk.sccr[1], SCCR2_CLOCKS_EN); |
Martha Marx | abfbd0ae | 2009-01-26 10:45:07 -0700 | [diff] [blame] | 115 | #if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE) |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 116 | setbits_be32 (&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN); |
Martha Marx | abfbd0ae | 2009-01-26 10:45:07 -0700 | [diff] [blame] | 117 | #endif |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 118 | |
| 119 | return 0; |
| 120 | } |
| 121 | |
Becky Bruce | 9973e3c | 2008-06-09 16:03:40 -0500 | [diff] [blame] | 122 | phys_size_t initdram (int board_type) |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 123 | { |
| 124 | u32 msize = 0; |
| 125 | |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 126 | msize = fixed_sdram (); |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 127 | |
| 128 | return msize; |
| 129 | } |
| 130 | |
| 131 | /* |
| 132 | * fixed sdram init -- the board doesn't use memory modules that have serial presence |
| 133 | * detect or similar mechanism for discovery of the DRAM settings |
| 134 | */ |
| 135 | long int fixed_sdram (void) |
| 136 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 137 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
| 138 | u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 139 | u32 msize_log2 = __ilog2 (msize); |
| 140 | u32 i; |
| 141 | |
| 142 | /* Initialize IO Control */ |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 143 | out_be32 (&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR); |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 144 | |
| 145 | /* Initialize DDR Local Window */ |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 146 | out_be32 (&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000); |
| 147 | out_be32 (&im->sysconf.ddrlaw.ar, msize_log2 - 1); |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 148 | |
| 149 | /* |
| 150 | * According to MPC5121e RM, configuring local access windows should |
| 151 | * be followed by a dummy read of the config register that was |
| 152 | * modified last and an isync |
Wolfgang Denk | b1b54e3 | 2007-08-02 21:27:46 +0200 | [diff] [blame] | 153 | */ |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 154 | in_be32(&im->sysconf.ddrlaw.ar); |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 155 | __asm__ __volatile__ ("isync"); |
| 156 | |
| 157 | /* Enable DDR */ |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 158 | out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN); |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 159 | |
| 160 | /* Initialize DDR Priority Manager */ |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 161 | out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1); |
| 162 | out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2); |
| 163 | out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG); |
| 164 | out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU); |
| 165 | out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML); |
| 166 | out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU); |
| 167 | out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML); |
| 168 | out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU); |
| 169 | out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML); |
| 170 | out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU); |
| 171 | out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML); |
| 172 | out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU); |
| 173 | out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML); |
| 174 | out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU); |
| 175 | out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL); |
| 176 | out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU); |
| 177 | out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL); |
| 178 | out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU); |
| 179 | out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL); |
| 180 | out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU); |
| 181 | out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL); |
| 182 | out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU); |
| 183 | out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL); |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 184 | |
| 185 | /* Initialize MDDRC */ |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 186 | out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG); |
| 187 | out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0); |
| 188 | out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1); |
| 189 | out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2); |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 190 | |
| 191 | /* Initialize DDR */ |
| 192 | for (i = 0; i < 10; i++) |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 193 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 194 | |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 195 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); |
| 196 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); |
| 197 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); |
| 198 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); |
| 199 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); |
| 200 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); |
| 201 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); |
| 202 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); |
| 203 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); |
| 204 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); |
| 205 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); |
| 206 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); |
| 207 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3); |
| 208 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL); |
| 209 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); |
| 210 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); |
| 211 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); |
| 212 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); |
| 213 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT); |
| 214 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); |
| 215 | out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 216 | |
| 217 | /* Start MDDRC */ |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 218 | out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN); |
| 219 | out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN); |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 220 | |
| 221 | return msize; |
| 222 | } |
| 223 | |
York Sun | 0e1bad4 | 2008-05-05 10:20:01 -0500 | [diff] [blame] | 224 | int misc_init_r(void) |
| 225 | { |
| 226 | u8 tmp_val; |
| 227 | |
| 228 | /* Using this for DIU init before the driver in linux takes over |
| 229 | * Enable the TFP410 Encoder (I2C address 0x38) |
| 230 | */ |
| 231 | |
| 232 | i2c_set_bus_num(2); |
| 233 | tmp_val = 0xBF; |
| 234 | i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); |
| 235 | /* Verify if enabled */ |
| 236 | tmp_val = 0; |
| 237 | i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); |
| 238 | debug("DVI Encoder Read: 0x%02lx\n", tmp_val); |
| 239 | |
| 240 | tmp_val = 0x10; |
| 241 | i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); |
| 242 | /* Verify if enabled */ |
| 243 | tmp_val = 0; |
| 244 | i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); |
| 245 | debug("DVI Encoder Read: 0x%02lx\n", tmp_val); |
| 246 | |
| 247 | #ifdef CONFIG_FSL_DIU_FB |
Wolfgang Denk | 72601d0 | 2009-05-16 10:47:41 +0200 | [diff] [blame] | 248 | # if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)) |
Wolfgang Denk | de26ef9 | 2009-05-16 10:47:38 +0200 | [diff] [blame] | 249 | mpc5121_diu_init(); |
Wolfgang Denk | 72601d0 | 2009-05-16 10:47:41 +0200 | [diff] [blame] | 250 | # endif |
York Sun | 0e1bad4 | 2008-05-05 10:20:01 -0500 | [diff] [blame] | 251 | #endif |
York Sun | 0e1bad4 | 2008-05-05 10:20:01 -0500 | [diff] [blame] | 252 | return 0; |
| 253 | } |
Wolfgang Denk | 72601d0 | 2009-05-16 10:47:41 +0200 | [diff] [blame] | 254 | |
Kenneth Johansson | 6689484 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 255 | static iopin_t ioregs_init[] = { |
| 256 | /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */ |
| 257 | { |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 258 | offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0, |
Kenneth Johansson | 6689484 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 259 | IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
| 260 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) |
| 261 | }, |
| 262 | /* Set highest Slew on 9 PATA pins */ |
| 263 | { |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 264 | offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1, |
Kenneth Johansson | 6689484 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 265 | IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
| 266 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) |
| 267 | }, |
| 268 | /* FUNC1=FEC_COL Sets Next 15 to FEC pads */ |
| 269 | { |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 270 | offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0, |
Kenneth Johansson | 6689484 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 271 | IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
| 272 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) |
| 273 | }, |
| 274 | /* FUNC1=SPDIF_TXCLK */ |
| 275 | { |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 276 | offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0, |
Kenneth Johansson | 6689484 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 277 | IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
| 278 | IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) |
| 279 | }, |
| 280 | /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */ |
| 281 | { |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 282 | offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0, |
Kenneth Johansson | 6689484 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 283 | IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
| 284 | IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) |
| 285 | }, |
| 286 | /* FUNC2=DIU CLK */ |
| 287 | { |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 288 | offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0, |
Kenneth Johansson | 6689484 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 289 | IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
| 290 | IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) |
| 291 | }, |
| 292 | /* FUNC2=DIU_HSYNC */ |
| 293 | { |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 294 | offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0, |
Kenneth Johansson | 6689484 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 295 | IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
| 296 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) |
| 297 | }, |
| 298 | /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */ |
| 299 | { |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 300 | offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0, |
Kenneth Johansson | 6689484 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 301 | IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
| 302 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) |
| 303 | } |
| 304 | }; |
York Sun | 0e1bad4 | 2008-05-05 10:20:01 -0500 | [diff] [blame] | 305 | |
John Rigby | 14d19cd | 2009-01-23 10:33:15 -0700 | [diff] [blame] | 306 | static iopin_t rev2_silicon_pci_ioregs_init[] = { |
| 307 | /* FUNC0=PCI Sets next 54 to PCI pads */ |
| 308 | { |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 309 | offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0, |
John Rigby | 14d19cd | 2009-01-23 10:33:15 -0700 | [diff] [blame] | 310 | IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0) |
| 311 | } |
| 312 | }; |
| 313 | |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 314 | int checkboard (void) |
| 315 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 316 | ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00); |
| 317 | uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02); |
John Rigby | 14d19cd | 2009-01-23 10:33:15 -0700 | [diff] [blame] | 318 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 319 | u32 spridr = in_be32(&im->sysconf.spridr); |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 320 | |
| 321 | printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n", |
Wolfgang Denk | b1b54e3 | 2007-08-02 21:27:46 +0200 | [diff] [blame] | 322 | brd_rev, cpld_rev); |
Kenneth Johansson | 6689484 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 323 | |
Wolfgang Denk | 72601d0 | 2009-05-16 10:47:41 +0200 | [diff] [blame] | 324 | /* initialize function mux & slew rate IO inter alia on IO Pins */ |
| 325 | iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init)); |
| 326 | |
Wolfgang Denk | 843efb1 | 2009-05-16 10:47:43 +0200 | [diff] [blame^] | 327 | if (SVR_MJREV (spridr) >= 2) |
John Rigby | 14d19cd | 2009-01-23 10:33:15 -0700 | [diff] [blame] | 328 | iopin_initialize(rev2_silicon_pci_ioregs_init, 1); |
John Rigby | 51b67d0 | 2007-08-24 18:18:43 -0600 | [diff] [blame] | 329 | |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 330 | return 0; |
| 331 | } |
Grzegorz Bernacki | 281ff9a | 2008-01-08 17:16:15 +0100 | [diff] [blame] | 332 | |
| 333 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
| 334 | void ft_board_setup(void *blob, bd_t *bd) |
| 335 | { |
| 336 | ft_cpu_setup(blob, bd); |
| 337 | fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); |
| 338 | } |
| 339 | #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ |