blob: 46be6a516ae4aff70343d5f32776267fadd0a0e1 [file] [log] [blame]
Rafal Jaworowski8993e542007-07-27 14:43:59 +02001/*
2 * (C) Copyright 2007 DENX Software Engineering
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23
24#include <common.h>
25#include <mpc512x.h>
26#include <asm/bitops.h>
27#include <command.h>
28
29/* Clocks in use */
30#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
31 CLOCK_SCCR1_LPC_EN | \
32 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
33 CLOCK_SCCR1_PSCFIFO_EN | \
34 CLOCK_SCCR1_DDR_EN | \
35 CLOCK_SCCR1_FEC_EN)
36
37#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
38 CLOCK_SCCR2_SPDIF_EN | \
39 CLOCK_SCCR2_I2C_EN)
40
41#define CSAW_START(start) ((start) & 0xFFFF0000)
42#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
43
44long int fixed_sdram(void);
45
46int board_early_init_f (void)
47{
48 volatile immap_t *im = (immap_t *) CFG_IMMR;
49 u32 lpcaw;
50
51 /*
52 * Initialize Local Window for the CPLD registers access (CS2 selects
53 * the CPLD chip)
54 */
55 im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) |
56 CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE);
57 im->lpc.cs_cfg[2] = CFG_CS2_CFG;
58
59 /*
60 * According to MPC5121e RM, configuring local access windows should
61 * be followed by a dummy read of the config register that was
62 * modified last and an isync
63 */
64 lpcaw = im->sysconf.lpcs2aw;
65 __asm__ __volatile__ ("isync");
66
67 /*
68 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
69 *
70 * Without this the flash identification routine fails, as it needs to issue
71 * write commands in order to establish the device ID.
72 */
73 *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
74
75 /*
76 * Enable clocks
77 */
78 im->clk.sccr[0] = SCCR1_CLOCKS_EN;
79 im->clk.sccr[1] = SCCR2_CLOCKS_EN;
80
81 return 0;
82}
83
84long int initdram (int board_type)
85{
86 u32 msize = 0;
87
Rafal Jaworowski8993e542007-07-27 14:43:59 +020088 msize = fixed_sdram ();
Rafal Jaworowski8993e542007-07-27 14:43:59 +020089
90 return msize;
91}
92
93/*
94 * fixed sdram init -- the board doesn't use memory modules that have serial presence
95 * detect or similar mechanism for discovery of the DRAM settings
96 */
97long int fixed_sdram (void)
98{
99 volatile immap_t *im = (immap_t *) CFG_IMMR;
100 u32 msize = CFG_DDR_SIZE * 1024 * 1024;
101 u32 msize_log2 = __ilog2 (msize);
102 u32 i;
103
104 /* Initialize IO Control */
105 im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR;
106
107 /* Initialize DDR Local Window */
108 im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
109 im->sysconf.ddrlaw.ar = msize_log2 - 1;
110
111 /*
112 * According to MPC5121e RM, configuring local access windows should
113 * be followed by a dummy read of the config register that was
114 * modified last and an isync
Wolfgang Denkb1b54e32007-08-02 21:27:46 +0200115 */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200116 i = im->sysconf.ddrlaw.ar;
117 __asm__ __volatile__ ("isync");
118
119 /* Enable DDR */
120 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN;
121
122 /* Initialize DDR Priority Manager */
123 im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1;
124 im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
125 im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
126 im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
127 im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
128 im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
129 im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
130 im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
131 im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
132 im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
133 im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
134 im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
135 im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
136 im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
137 im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
138 im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
139 im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
140 im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
141 im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AU;
142 im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
143 im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
144 im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
145 im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;
146
147 /* Initialize MDDRC */
148 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG;
149 im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0;
150 im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1;
151 im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2;
152
153 /* Initialize DDR */
154 for (i = 0; i < 10; i++)
155 im->mddrc.ddr_command = CFG_MICRON_NOP;
156
157 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
158 im->mddrc.ddr_command = CFG_MICRON_EM2;
159 im->mddrc.ddr_command = CFG_MICRON_EM3;
160 im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
161 im->mddrc.ddr_command = CFG_MICRON_RST_DLL;
162 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
163 im->mddrc.ddr_command = CFG_MICRON_RFSH;
164 im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
165 im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
166 im->mddrc.ddr_command = CFG_MICRON_OCD_EXIT;
167
168 for (i = 0; i < 10; i++)
169 im->mddrc.ddr_command = CFG_MICRON_NOP;
170
171 /* Start MDDRC */
172 im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;
173 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN;
174
175 return msize;
176}
177
178int checkboard (void)
179{
180 ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
181 uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
182
183 printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
Wolfgang Denkb1b54e32007-08-02 21:27:46 +0200184 brd_rev, cpld_rev);
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200185 return 0;
186}
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100187
188#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
189void ft_board_setup(void *blob, bd_t *bd)
190{
191 ft_cpu_setup(blob, bd);
192 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
193}
194#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */