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Haavard Skinnemoend25ce7d2008-05-16 11:10:33 +02001/*
2 * SPI flash internal definitions
3 *
4 * Copyright (C) 2008 Atmel Corporation
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +05305 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
6 *
Jagannadha Sutradharudu Teki0c88a842013-10-10 22:32:55 +05307 * SPDX-License-Identifier: GPL-2.0+
Haavard Skinnemoend25ce7d2008-05-16 11:10:33 +02008 */
9
Jagannadha Sutradharudu Teki469146c2013-10-10 22:14:09 +053010#ifndef _SF_INTERNAL_H_
11#define _SF_INTERNAL_H_
Haavard Skinnemoend25ce7d2008-05-16 11:10:33 +020012
Simon Glassff0960f2014-10-13 23:42:04 -060013#include <linux/types.h>
14#include <linux/compiler.h>
15
16/* Dual SPI flash memories - see SPI_COMM_DUAL_... */
17enum spi_dual_flash {
18 SF_SINGLE_FLASH = 0,
19 SF_DUAL_STACKED_FLASH = 1 << 0,
20 SF_DUAL_PARALLEL_FLASH = 1 << 1,
21};
22
23/* Enum list - Full read commands */
24enum spi_read_cmds {
25 ARRAY_SLOW = 1 << 0,
Jagannadha Sutradharudu Teki6dd6e902014-12-12 19:36:11 +053026 ARRAY_FAST = 1 << 1,
27 DUAL_OUTPUT_FAST = 1 << 2,
28 DUAL_IO_FAST = 1 << 3,
29 QUAD_OUTPUT_FAST = 1 << 4,
30 QUAD_IO_FAST = 1 << 5,
Simon Glassff0960f2014-10-13 23:42:04 -060031};
32
Jagannadha Sutradharudu Teki6dd6e902014-12-12 19:36:11 +053033/* Normal - Extended - Full command set */
Jagan Teki5d69df32015-06-27 00:51:30 +053034#define RD_NORM (ARRAY_SLOW | ARRAY_FAST)
35#define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
36#define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
Simon Glassff0960f2014-10-13 23:42:04 -060037
38/* sf param flags */
39enum {
Marek Vasut0a026552015-08-03 01:28:56 +020040#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
Simon Glassff0960f2014-10-13 23:42:04 -060041 SECT_4K = 1 << 0,
Marek Vasut0a026552015-08-03 01:28:56 +020042#else
43 SECT_4K = 0 << 0,
44#endif
Simon Glassff0960f2014-10-13 23:42:04 -060045 SECT_32K = 1 << 1,
46 E_FSR = 1 << 2,
Jagannadha Sutradharudu Teki54ba6532014-12-12 19:36:14 +053047 SST_BP = 1 << 3,
Simon Glassb6487422014-12-12 19:36:12 +053048 SST_WP = 1 << 4,
Jagannadha Sutradharudu Teki54ba6532014-12-12 19:36:14 +053049 WR_QPP = 1 << 5,
Simon Glassff0960f2014-10-13 23:42:04 -060050};
51
Jagannadha Sutradharudu Teki54ba6532014-12-12 19:36:14 +053052#define SST_WR (SST_BP | SST_WP)
53
Jagannadha Sutradharudu Tekiff063ed2014-01-11 16:50:45 +053054#define SPI_FLASH_3B_ADDR_LEN 3
55#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +053056#define SPI_FLASH_16MB_BOUN 0x1000000
Haavard Skinnemoend25ce7d2008-05-16 11:10:33 +020057
Jagannadha Sutradharudu Tekid08a1ba2013-12-26 13:54:57 +053058/* CFI Manufacture ID's */
59#define SPI_FLASH_CFI_MFR_SPANSION 0x01
60#define SPI_FLASH_CFI_MFR_STMICRO 0x20
Jagannadha Sutradharudu Teki06795122013-12-26 14:13:36 +053061#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2
Jagannadha Sutradharudu Tekid08a1ba2013-12-26 13:54:57 +053062#define SPI_FLASH_CFI_MFR_WINBOND 0xef
63
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +053064/* Erase commands */
65#define CMD_ERASE_4K 0x20
66#define CMD_ERASE_32K 0x52
67#define CMD_ERASE_CHIP 0xc7
68#define CMD_ERASE_64K 0xd8
69
70/* Write commands */
Mike Frysingerb4c87d62012-01-28 16:26:03 -080071#define CMD_WRITE_STATUS 0x01
Mike Frysingerd4aa5002011-04-25 06:58:29 +000072#define CMD_PAGE_PROGRAM 0x02
Mike Frysinger66ecb7c2011-04-25 06:59:53 +000073#define CMD_WRITE_DISABLE 0x04
Jagan Teki5d69df32015-06-27 00:51:30 +053074#define CMD_READ_STATUS 0x05
Jagannadha Sutradharudu Teki3163aaa2014-01-11 15:13:11 +053075#define CMD_QUAD_PAGE_PROGRAM 0x32
Mike Frysingerffdb20b2013-12-03 16:43:27 -070076#define CMD_READ_STATUS1 0x35
Mike Frysingere7b44ed2011-01-10 02:20:13 -050077#define CMD_WRITE_ENABLE 0x06
Jagan Teki5d69df32015-06-27 00:51:30 +053078#define CMD_READ_CONFIG 0x35
79#define CMD_FLAG_STATUS 0x70
Mike Frysinger61630452011-01-10 02:20:12 -050080
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +053081/* Read commands */
82#define CMD_READ_ARRAY_SLOW 0x03
83#define CMD_READ_ARRAY_FAST 0x0b
Jagannadha Sutradharudu Teki4e09cc12014-01-11 15:10:28 +053084#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
85#define CMD_READ_DUAL_IO_FAST 0xbb
Jagannadha Sutradharudu Teki3163aaa2014-01-11 15:13:11 +053086#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
Jagannadha Sutradharudu Tekic4ba0d82013-12-24 15:24:31 +053087#define CMD_READ_QUAD_IO_FAST 0xeb
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +053088#define CMD_READ_ID 0x9f
Jagannadha Sutradharudu Tekie612ddf2013-06-19 15:37:09 +053089
Jagannadha Sutradharudu Tekicf6b11d2013-06-19 15:31:23 +053090/* Bank addr access commands */
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +053091#ifdef CONFIG_SPI_FLASH_BAR
Jagannadha Sutradharudu Teki1dcd6d02013-06-19 15:33:58 +053092# define CMD_BANKADDR_BRWR 0x17
93# define CMD_BANKADDR_BRRD 0x16
94# define CMD_EXTNADDR_WREAR 0xC5
95# define CMD_EXTNADDR_RDEAR 0xC8
96#endif
Jagannadha Sutradharudu Tekicf6b11d2013-06-19 15:31:23 +053097
Mike Frysinger61630452011-01-10 02:20:12 -050098/* Common status */
Jagannadha Sutradharudu Teki2ba863f2014-01-12 21:38:21 +053099#define STATUS_WIP (1 << 0)
Jagannadha Sutradharudu Tekid08a1ba2013-12-26 13:54:57 +0530100#define STATUS_QEB_WINSPAN (1 << 1)
Simon Glassff0960f2014-10-13 23:42:04 -0600101#define STATUS_QEB_MXIC (1 << 6)
Jagannadha Sutradharudu Teki2ba863f2014-01-12 21:38:21 +0530102#define STATUS_PEC (1 << 7)
Mike Frysinger61630452011-01-10 02:20:12 -0500103
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +0530104/* Flash timeout values */
105#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
Jagan Teki5d69df32015-06-27 00:51:30 +0530106#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +0530107#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
108
109/* SST specific */
110#ifdef CONFIG_SPI_FLASH_SST
Jagannadha Sutradharudu Tekice22b922013-10-07 19:34:56 +0530111# define CMD_SST_BP 0x02 /* Byte Program */
Jagan Teki5d69df32015-06-27 00:51:30 +0530112# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +0530113
114int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
115 const void *buf);
Bin Meng74c2cee2014-12-12 19:36:13 +0530116int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
117 const void *buf);
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +0530118#endif
119
Simon Glassff0960f2014-10-13 23:42:04 -0600120/**
121 * struct spi_flash_params - SPI/QSPI flash device params structure
122 *
123 * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
124 * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
125 * @ext_jedec: Device ext_jedec ID
Jagannadha Sutradharudu Tekic650ca72015-04-27 21:04:15 +0530126 * @sector_size: Isn't necessarily a sector size from vendor,
127 * the size listed here is what works with CMD_ERASE_64K
Jagan Teki5d69df32015-06-27 00:51:30 +0530128 * @nr_sectors: No.of sectors on this device
Simon Glassff0960f2014-10-13 23:42:04 -0600129 * @e_rd_cmd: Enum list for read commands
130 * @flags: Important param, for flash specific behaviour
131 */
132struct spi_flash_params {
133 const char *name;
134 u32 jedec;
135 u16 ext_jedec;
136 u32 sector_size;
137 u32 nr_sectors;
138 u8 e_rd_cmd;
139 u16 flags;
140};
141
142extern const struct spi_flash_params spi_flash_params_table[];
143
Haavard Skinnemoend25ce7d2008-05-16 11:10:33 +0200144/* Send a single-byte command to the device and read the response */
145int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
146
147/*
148 * Send a multi-byte command to the device and read the response. Used
149 * for flash array reads, etc.
150 */
151int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
152 size_t cmd_len, void *data, size_t data_len);
153
154/*
155 * Send a multi-byte command to the device followed by (optional)
156 * data. Used for programming the flash array, etc.
157 */
158int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
159 const void *data, size_t data_len);
160
Mike Frysingerd4aa5002011-04-25 06:58:29 +0000161
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +0530162/* Flash erase(sectors) operation, support all possible erase commands */
163int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
Jagannadha Sutradharudu Teki10ca45d2013-10-02 19:34:53 +0530164
Jagannadha Sutradharudu Teki9f4322f2013-12-30 22:16:23 +0530165/* Read the status register */
166int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
167
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +0530168/* Program the status register */
Jagannadha Sutradharudu Teki2ba863f2014-01-12 21:38:21 +0530169int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws);
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +0530170
Jagannadha Sutradharudu Teki9f4322f2013-12-30 22:16:23 +0530171/* Read the config register */
172int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
Jagannadha Sutradharudu Teki06795122013-12-26 14:13:36 +0530173
Jagannadha Sutradharudu Teki9f4322f2013-12-30 22:16:23 +0530174/* Program the config register */
175int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc);
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +0530176
177/* Enable writing on the SPI flash */
Mike Frysinger2744a4e2011-04-23 23:05:55 +0000178static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
179{
180 return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
181}
182
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +0530183/* Disable writing on the SPI flash */
Mike Frysinger66ecb7c2011-04-25 06:59:53 +0000184static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
185{
186 return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
187}
188
189/*
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +0530190 * Send the read status command to the device and wait for the wip
191 * (write-in-progress) bit to clear itself.
Haavard Skinnemoend25ce7d2008-05-16 11:10:33 +0200192 */
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +0530193int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout);
194
Jagannadha Sutradharudu Tekiacc23752013-06-21 19:19:00 +0530195/*
196 * Used for spi_flash write operation
197 * - SPI claim
198 * - spi_flash_cmd_write_enable
199 * - spi_flash_cmd_write
200 * - spi_flash_cmd_wait_ready
201 * - SPI release
202 */
203int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
204 size_t cmd_len, const void *buf, size_t buf_len);
Mike Frysinger61630452011-01-10 02:20:12 -0500205
206/*
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +0530207 * Flash write operation, support all possible write commands.
208 * Write the requested data out breaking it up into multiple write
209 * commands as needed per the write size.
Mike Frysinger61630452011-01-10 02:20:12 -0500210 */
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +0530211int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
212 size_t len, const void *buf);
Mike Frysinger61630452011-01-10 02:20:12 -0500213
Jagannadha Sutradharudu Tekia5e81992013-10-02 19:38:49 +0530214/*
215 * Same as spi_flash_cmd_read() except it also claims/releases the SPI
216 * bus. Used as common part of the ->read() operation.
217 */
218int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
219 size_t cmd_len, void *data, size_t data_len);
220
221/* Flash read operation, support all possible read commands */
222int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
223 size_t len, void *data);
224
Daniel Schwierzeck9fe6d872015-04-27 07:42:04 +0200225#ifdef CONFIG_SPI_FLASH_MTD
226int spi_flash_mtd_register(struct spi_flash *flash);
227void spi_flash_mtd_unregister(void);
228#endif
229
Jagannadha Sutradharudu Teki469146c2013-10-10 22:14:09 +0530230#endif /* _SF_INTERNAL_H_ */