Haavard Skinnemoen | d25ce7d | 2008-05-16 11:10:33 +0200 | [diff] [blame] | 1 | /* |
| 2 | * SPI flash internal definitions |
| 3 | * |
| 4 | * Copyright (C) 2008 Atmel Corporation |
Jagannadha Sutradharudu Teki | a5e8199 | 2013-10-02 19:38:49 +0530 | [diff] [blame] | 5 | * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. |
| 6 | * |
Jagannadha Sutradharudu Teki | 0c88a84 | 2013-10-10 22:32:55 +0530 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
Haavard Skinnemoen | d25ce7d | 2008-05-16 11:10:33 +0200 | [diff] [blame] | 8 | */ |
| 9 | |
Jagannadha Sutradharudu Teki | 469146c | 2013-10-10 22:14:09 +0530 | [diff] [blame] | 10 | #ifndef _SF_INTERNAL_H_ |
| 11 | #define _SF_INTERNAL_H_ |
Haavard Skinnemoen | d25ce7d | 2008-05-16 11:10:33 +0200 | [diff] [blame] | 12 | |
Simon Glass | ff0960f | 2014-10-13 23:42:04 -0600 | [diff] [blame] | 13 | #include <linux/types.h> |
| 14 | #include <linux/compiler.h> |
| 15 | |
| 16 | /* Dual SPI flash memories - see SPI_COMM_DUAL_... */ |
| 17 | enum spi_dual_flash { |
| 18 | SF_SINGLE_FLASH = 0, |
| 19 | SF_DUAL_STACKED_FLASH = 1 << 0, |
| 20 | SF_DUAL_PARALLEL_FLASH = 1 << 1, |
| 21 | }; |
| 22 | |
| 23 | /* Enum list - Full read commands */ |
| 24 | enum spi_read_cmds { |
| 25 | ARRAY_SLOW = 1 << 0, |
Jagannadha Sutradharudu Teki | 6dd6e90 | 2014-12-12 19:36:11 +0530 | [diff] [blame] | 26 | ARRAY_FAST = 1 << 1, |
| 27 | DUAL_OUTPUT_FAST = 1 << 2, |
| 28 | DUAL_IO_FAST = 1 << 3, |
| 29 | QUAD_OUTPUT_FAST = 1 << 4, |
| 30 | QUAD_IO_FAST = 1 << 5, |
Simon Glass | ff0960f | 2014-10-13 23:42:04 -0600 | [diff] [blame] | 31 | }; |
| 32 | |
Jagannadha Sutradharudu Teki | 6dd6e90 | 2014-12-12 19:36:11 +0530 | [diff] [blame] | 33 | /* Normal - Extended - Full command set */ |
| 34 | #define RD_NORM (ARRAY_SLOW | ARRAY_FAST) |
| 35 | #define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST) |
Simon Glass | ff0960f | 2014-10-13 23:42:04 -0600 | [diff] [blame] | 36 | #define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST) |
| 37 | |
| 38 | /* sf param flags */ |
| 39 | enum { |
| 40 | SECT_4K = 1 << 0, |
| 41 | SECT_32K = 1 << 1, |
| 42 | E_FSR = 1 << 2, |
| 43 | WR_QPP = 1 << 3, |
Simon Glass | b648742 | 2014-12-12 19:36:12 +0530 | [diff] [blame^] | 44 | SST_WP = 1 << 4, |
Simon Glass | ff0960f | 2014-10-13 23:42:04 -0600 | [diff] [blame] | 45 | }; |
| 46 | |
Jagannadha Sutradharudu Teki | ff063ed | 2014-01-11 16:50:45 +0530 | [diff] [blame] | 47 | #define SPI_FLASH_3B_ADDR_LEN 3 |
| 48 | #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) |
Jagannadha Sutradharudu Teki | a5e8199 | 2013-10-02 19:38:49 +0530 | [diff] [blame] | 49 | #define SPI_FLASH_16MB_BOUN 0x1000000 |
Haavard Skinnemoen | d25ce7d | 2008-05-16 11:10:33 +0200 | [diff] [blame] | 50 | |
Jagannadha Sutradharudu Teki | d08a1ba | 2013-12-26 13:54:57 +0530 | [diff] [blame] | 51 | /* CFI Manufacture ID's */ |
| 52 | #define SPI_FLASH_CFI_MFR_SPANSION 0x01 |
| 53 | #define SPI_FLASH_CFI_MFR_STMICRO 0x20 |
Jagannadha Sutradharudu Teki | 0679512 | 2013-12-26 14:13:36 +0530 | [diff] [blame] | 54 | #define SPI_FLASH_CFI_MFR_MACRONIX 0xc2 |
Jagannadha Sutradharudu Teki | d08a1ba | 2013-12-26 13:54:57 +0530 | [diff] [blame] | 55 | #define SPI_FLASH_CFI_MFR_WINBOND 0xef |
| 56 | |
Jagannadha Sutradharudu Teki | a5e8199 | 2013-10-02 19:38:49 +0530 | [diff] [blame] | 57 | /* Erase commands */ |
| 58 | #define CMD_ERASE_4K 0x20 |
| 59 | #define CMD_ERASE_32K 0x52 |
| 60 | #define CMD_ERASE_CHIP 0xc7 |
| 61 | #define CMD_ERASE_64K 0xd8 |
| 62 | |
| 63 | /* Write commands */ |
Mike Frysinger | b4c87d6 | 2012-01-28 16:26:03 -0800 | [diff] [blame] | 64 | #define CMD_WRITE_STATUS 0x01 |
Mike Frysinger | d4aa500 | 2011-04-25 06:58:29 +0000 | [diff] [blame] | 65 | #define CMD_PAGE_PROGRAM 0x02 |
Mike Frysinger | 66ecb7c | 2011-04-25 06:59:53 +0000 | [diff] [blame] | 66 | #define CMD_WRITE_DISABLE 0x04 |
Simon Glass | ff0960f | 2014-10-13 23:42:04 -0600 | [diff] [blame] | 67 | #define CMD_READ_STATUS 0x05 |
Jagannadha Sutradharudu Teki | 3163aaa | 2014-01-11 15:13:11 +0530 | [diff] [blame] | 68 | #define CMD_QUAD_PAGE_PROGRAM 0x32 |
Mike Frysinger | ffdb20b | 2013-12-03 16:43:27 -0700 | [diff] [blame] | 69 | #define CMD_READ_STATUS1 0x35 |
Mike Frysinger | e7b44ed | 2011-01-10 02:20:13 -0500 | [diff] [blame] | 70 | #define CMD_WRITE_ENABLE 0x06 |
Simon Glass | ff0960f | 2014-10-13 23:42:04 -0600 | [diff] [blame] | 71 | #define CMD_READ_CONFIG 0x35 |
| 72 | #define CMD_FLAG_STATUS 0x70 |
Mike Frysinger | 6163045 | 2011-01-10 02:20:12 -0500 | [diff] [blame] | 73 | |
Jagannadha Sutradharudu Teki | a5e8199 | 2013-10-02 19:38:49 +0530 | [diff] [blame] | 74 | /* Read commands */ |
| 75 | #define CMD_READ_ARRAY_SLOW 0x03 |
| 76 | #define CMD_READ_ARRAY_FAST 0x0b |
Jagannadha Sutradharudu Teki | 4e09cc1 | 2014-01-11 15:10:28 +0530 | [diff] [blame] | 77 | #define CMD_READ_DUAL_OUTPUT_FAST 0x3b |
| 78 | #define CMD_READ_DUAL_IO_FAST 0xbb |
Jagannadha Sutradharudu Teki | 3163aaa | 2014-01-11 15:13:11 +0530 | [diff] [blame] | 79 | #define CMD_READ_QUAD_OUTPUT_FAST 0x6b |
Jagannadha Sutradharudu Teki | c4ba0d8 | 2013-12-24 15:24:31 +0530 | [diff] [blame] | 80 | #define CMD_READ_QUAD_IO_FAST 0xeb |
Jagannadha Sutradharudu Teki | a5e8199 | 2013-10-02 19:38:49 +0530 | [diff] [blame] | 81 | #define CMD_READ_ID 0x9f |
Jagannadha Sutradharudu Teki | e612ddf | 2013-06-19 15:37:09 +0530 | [diff] [blame] | 82 | |
Jagannadha Sutradharudu Teki | cf6b11d | 2013-06-19 15:31:23 +0530 | [diff] [blame] | 83 | /* Bank addr access commands */ |
Jagannadha Sutradharudu Teki | a5e8199 | 2013-10-02 19:38:49 +0530 | [diff] [blame] | 84 | #ifdef CONFIG_SPI_FLASH_BAR |
Jagannadha Sutradharudu Teki | 1dcd6d0 | 2013-06-19 15:33:58 +0530 | [diff] [blame] | 85 | # define CMD_BANKADDR_BRWR 0x17 |
| 86 | # define CMD_BANKADDR_BRRD 0x16 |
| 87 | # define CMD_EXTNADDR_WREAR 0xC5 |
| 88 | # define CMD_EXTNADDR_RDEAR 0xC8 |
| 89 | #endif |
Jagannadha Sutradharudu Teki | cf6b11d | 2013-06-19 15:31:23 +0530 | [diff] [blame] | 90 | |
Mike Frysinger | 6163045 | 2011-01-10 02:20:12 -0500 | [diff] [blame] | 91 | /* Common status */ |
Jagannadha Sutradharudu Teki | 2ba863f | 2014-01-12 21:38:21 +0530 | [diff] [blame] | 92 | #define STATUS_WIP (1 << 0) |
Jagannadha Sutradharudu Teki | d08a1ba | 2013-12-26 13:54:57 +0530 | [diff] [blame] | 93 | #define STATUS_QEB_WINSPAN (1 << 1) |
Simon Glass | ff0960f | 2014-10-13 23:42:04 -0600 | [diff] [blame] | 94 | #define STATUS_QEB_MXIC (1 << 6) |
Jagannadha Sutradharudu Teki | 2ba863f | 2014-01-12 21:38:21 +0530 | [diff] [blame] | 95 | #define STATUS_PEC (1 << 7) |
Mike Frysinger | 6163045 | 2011-01-10 02:20:12 -0500 | [diff] [blame] | 96 | |
Heiko Schocher | 562f8df | 2014-07-18 06:07:21 +0200 | [diff] [blame] | 97 | #ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN |
| 98 | #define STATUS_SRWD (1 << 7) /* SR write protect */ |
| 99 | #endif |
| 100 | |
Jagannadha Sutradharudu Teki | a5e8199 | 2013-10-02 19:38:49 +0530 | [diff] [blame] | 101 | /* Flash timeout values */ |
| 102 | #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) |
Simon Glass | ff0960f | 2014-10-13 23:42:04 -0600 | [diff] [blame] | 103 | #define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) |
Jagannadha Sutradharudu Teki | a5e8199 | 2013-10-02 19:38:49 +0530 | [diff] [blame] | 104 | #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) |
| 105 | |
| 106 | /* SST specific */ |
| 107 | #ifdef CONFIG_SPI_FLASH_SST |
Jagannadha Sutradharudu Teki | ce22b92 | 2013-10-07 19:34:56 +0530 | [diff] [blame] | 108 | # define CMD_SST_BP 0x02 /* Byte Program */ |
Simon Glass | ff0960f | 2014-10-13 23:42:04 -0600 | [diff] [blame] | 109 | # define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */ |
Jagannadha Sutradharudu Teki | a5e8199 | 2013-10-02 19:38:49 +0530 | [diff] [blame] | 110 | |
| 111 | int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, |
| 112 | const void *buf); |
| 113 | #endif |
| 114 | |
Simon Glass | ff0960f | 2014-10-13 23:42:04 -0600 | [diff] [blame] | 115 | /** |
| 116 | * struct spi_flash_params - SPI/QSPI flash device params structure |
| 117 | * |
| 118 | * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) |
| 119 | * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id]) |
| 120 | * @ext_jedec: Device ext_jedec ID |
| 121 | * @sector_size: Sector size of this device |
| 122 | * @nr_sectors: No.of sectors on this device |
| 123 | * @e_rd_cmd: Enum list for read commands |
| 124 | * @flags: Important param, for flash specific behaviour |
| 125 | */ |
| 126 | struct spi_flash_params { |
| 127 | const char *name; |
| 128 | u32 jedec; |
| 129 | u16 ext_jedec; |
| 130 | u32 sector_size; |
| 131 | u32 nr_sectors; |
| 132 | u8 e_rd_cmd; |
| 133 | u16 flags; |
| 134 | }; |
| 135 | |
| 136 | extern const struct spi_flash_params spi_flash_params_table[]; |
| 137 | |
Haavard Skinnemoen | d25ce7d | 2008-05-16 11:10:33 +0200 | [diff] [blame] | 138 | /* Send a single-byte command to the device and read the response */ |
| 139 | int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); |
| 140 | |
| 141 | /* |
| 142 | * Send a multi-byte command to the device and read the response. Used |
| 143 | * for flash array reads, etc. |
| 144 | */ |
| 145 | int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, |
| 146 | size_t cmd_len, void *data, size_t data_len); |
| 147 | |
| 148 | /* |
| 149 | * Send a multi-byte command to the device followed by (optional) |
| 150 | * data. Used for programming the flash array, etc. |
| 151 | */ |
| 152 | int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, |
| 153 | const void *data, size_t data_len); |
| 154 | |
Mike Frysinger | d4aa500 | 2011-04-25 06:58:29 +0000 | [diff] [blame] | 155 | |
Jagannadha Sutradharudu Teki | a5e8199 | 2013-10-02 19:38:49 +0530 | [diff] [blame] | 156 | /* Flash erase(sectors) operation, support all possible erase commands */ |
| 157 | int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len); |
Jagannadha Sutradharudu Teki | 10ca45d | 2013-10-02 19:34:53 +0530 | [diff] [blame] | 158 | |
Jagannadha Sutradharudu Teki | 9f4322f | 2013-12-30 22:16:23 +0530 | [diff] [blame] | 159 | /* Read the status register */ |
| 160 | int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs); |
| 161 | |
Jagannadha Sutradharudu Teki | a5e8199 | 2013-10-02 19:38:49 +0530 | [diff] [blame] | 162 | /* Program the status register */ |
Jagannadha Sutradharudu Teki | 2ba863f | 2014-01-12 21:38:21 +0530 | [diff] [blame] | 163 | int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws); |
Jagannadha Sutradharudu Teki | a5e8199 | 2013-10-02 19:38:49 +0530 | [diff] [blame] | 164 | |
Jagannadha Sutradharudu Teki | 9f4322f | 2013-12-30 22:16:23 +0530 | [diff] [blame] | 165 | /* Read the config register */ |
| 166 | int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc); |
Jagannadha Sutradharudu Teki | 0679512 | 2013-12-26 14:13:36 +0530 | [diff] [blame] | 167 | |
Jagannadha Sutradharudu Teki | 9f4322f | 2013-12-30 22:16:23 +0530 | [diff] [blame] | 168 | /* Program the config register */ |
| 169 | int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc); |
Jagannadha Sutradharudu Teki | a5e8199 | 2013-10-02 19:38:49 +0530 | [diff] [blame] | 170 | |
| 171 | /* Enable writing on the SPI flash */ |
Mike Frysinger | 2744a4e | 2011-04-23 23:05:55 +0000 | [diff] [blame] | 172 | static inline int spi_flash_cmd_write_enable(struct spi_flash *flash) |
| 173 | { |
| 174 | return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); |
| 175 | } |
| 176 | |
Jagannadha Sutradharudu Teki | a5e8199 | 2013-10-02 19:38:49 +0530 | [diff] [blame] | 177 | /* Disable writing on the SPI flash */ |
Mike Frysinger | 66ecb7c | 2011-04-25 06:59:53 +0000 | [diff] [blame] | 178 | static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) |
| 179 | { |
| 180 | return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); |
| 181 | } |
| 182 | |
| 183 | /* |
Jagannadha Sutradharudu Teki | a5e8199 | 2013-10-02 19:38:49 +0530 | [diff] [blame] | 184 | * Send the read status command to the device and wait for the wip |
| 185 | * (write-in-progress) bit to clear itself. |
Haavard Skinnemoen | d25ce7d | 2008-05-16 11:10:33 +0200 | [diff] [blame] | 186 | */ |
Jagannadha Sutradharudu Teki | a5e8199 | 2013-10-02 19:38:49 +0530 | [diff] [blame] | 187 | int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout); |
| 188 | |
Jagannadha Sutradharudu Teki | acc2375 | 2013-06-21 19:19:00 +0530 | [diff] [blame] | 189 | /* |
| 190 | * Used for spi_flash write operation |
| 191 | * - SPI claim |
| 192 | * - spi_flash_cmd_write_enable |
| 193 | * - spi_flash_cmd_write |
| 194 | * - spi_flash_cmd_wait_ready |
| 195 | * - SPI release |
| 196 | */ |
| 197 | int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, |
| 198 | size_t cmd_len, const void *buf, size_t buf_len); |
Mike Frysinger | 6163045 | 2011-01-10 02:20:12 -0500 | [diff] [blame] | 199 | |
| 200 | /* |
Jagannadha Sutradharudu Teki | a5e8199 | 2013-10-02 19:38:49 +0530 | [diff] [blame] | 201 | * Flash write operation, support all possible write commands. |
| 202 | * Write the requested data out breaking it up into multiple write |
| 203 | * commands as needed per the write size. |
Mike Frysinger | 6163045 | 2011-01-10 02:20:12 -0500 | [diff] [blame] | 204 | */ |
Jagannadha Sutradharudu Teki | a5e8199 | 2013-10-02 19:38:49 +0530 | [diff] [blame] | 205 | int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, |
| 206 | size_t len, const void *buf); |
Mike Frysinger | 6163045 | 2011-01-10 02:20:12 -0500 | [diff] [blame] | 207 | |
Jagannadha Sutradharudu Teki | a5e8199 | 2013-10-02 19:38:49 +0530 | [diff] [blame] | 208 | /* |
| 209 | * Same as spi_flash_cmd_read() except it also claims/releases the SPI |
| 210 | * bus. Used as common part of the ->read() operation. |
| 211 | */ |
| 212 | int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, |
| 213 | size_t cmd_len, void *data, size_t data_len); |
| 214 | |
| 215 | /* Flash read operation, support all possible read commands */ |
| 216 | int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, |
| 217 | size_t len, void *data); |
| 218 | |
Jagannadha Sutradharudu Teki | 469146c | 2013-10-10 22:14:09 +0530 | [diff] [blame] | 219 | #endif /* _SF_INTERNAL_H_ */ |