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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sascha Hauercdace062008-03-26 20:40:49 +01002/*
Marek Vasutdb841402011-09-22 09:22:12 +00003 * i2c driver for Freescale i.MX series
Sascha Hauercdace062008-03-26 20:40:49 +01004 *
5 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
Marek Vasutdb841402011-09-22 09:22:12 +00006 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
7 *
8 * Based on i2c-imx.c from linux kernel:
9 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
10 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
11 * Copyright (C) 2007 RightHand Technologies, Inc.
12 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
13 *
Sascha Hauercdace062008-03-26 20:40:49 +010014 */
15
16#include <common.h>
Liu Hui-R64343127cec12011-01-03 22:27:39 +000017#include <asm/arch/clock.h>
Stefano Babic86271112011-03-14 15:43:56 +010018#include <asm/arch/imx-regs.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090019#include <linux/errno.h>
Stefano Babic552a8482017-06-29 10:16:06 +020020#include <asm/mach-imx/mxc_i2c.h>
Troy Kisky24cd7382012-07-19 08:18:03 +000021#include <asm/io.h>
Marek Vasutbf0783d2011-10-26 00:05:44 +000022#include <i2c.h>
Troy Kisky7aa57a02012-07-19 08:18:09 +000023#include <watchdog.h>
Peng Fan71204e92015-05-15 07:29:12 +080024#include <dm.h>
Peng Fane1bed802016-03-11 16:47:50 +080025#include <dm/pinctrl.h>
Peng Fan71204e92015-05-15 07:29:12 +080026#include <fdtdec.h>
Sascha Hauercdace062008-03-26 20:40:49 +010027
York Sundec18612014-02-10 14:02:52 -080028DECLARE_GLOBAL_DATA_PTR;
29
Peng Fan71204e92015-05-15 07:29:12 +080030#define I2C_QUIRK_FLAG (1 << 0)
31
32#define IMX_I2C_REGSHIFT 2
33#define VF610_I2C_REGSHIFT 0
Yuan Yao9d10c2d2016-06-08 18:24:51 +080034
35#define I2C_EARLY_INIT_INDEX 0
36#ifdef CONFIG_SYS_I2C_IFDR_DIV
37#define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV
38#else
39#define I2C_IFDR_DIV_CONSERVATIVE 0x7e
40#endif
41
Peng Fan71204e92015-05-15 07:29:12 +080042/* Register index */
43#define IADR 0
44#define IFDR 1
45#define I2CR 2
46#define I2SR 3
47#define I2DR 4
Sascha Hauercdace062008-03-26 20:40:49 +010048
Sascha Hauercdace062008-03-26 20:40:49 +010049#define I2CR_IIEN (1 << 6)
50#define I2CR_MSTA (1 << 5)
51#define I2CR_MTX (1 << 4)
52#define I2CR_TX_NO_AK (1 << 3)
53#define I2CR_RSTA (1 << 2)
54
55#define I2SR_ICF (1 << 7)
56#define I2SR_IBB (1 << 5)
Troy Kiskyd5383a62012-07-19 08:18:15 +000057#define I2SR_IAL (1 << 4)
Sascha Hauercdace062008-03-26 20:40:49 +010058#define I2SR_IIF (1 << 1)
59#define I2SR_RX_NO_AK (1 << 0)
60
Alison Wang30ea41a2013-06-17 15:30:39 +080061#ifdef I2C_QUIRK_REG
62#define I2CR_IEN (0 << 7)
63#define I2CR_IDIS (1 << 7)
64#define I2SR_IIF_CLEAR (1 << 1)
65#else
66#define I2CR_IEN (1 << 7)
67#define I2CR_IDIS (0 << 7)
68#define I2SR_IIF_CLEAR (0 << 1)
69#endif
70
Alison Wang30ea41a2013-06-17 15:30:39 +080071#ifdef I2C_QUIRK_REG
72static u16 i2c_clk_div[60][2] = {
73 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
74 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
75 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
76 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
77 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
78 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
79 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
80 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
81 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
82 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
83 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
84 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
85 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
86 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
87 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
88};
89#else
Marek Vasutdb841402011-09-22 09:22:12 +000090static u16 i2c_clk_div[50][2] = {
91 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
92 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
93 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
94 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
95 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
96 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
97 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
98 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
99 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
100 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
101 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
102 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
103 { 3072, 0x1E }, { 3840, 0x1F }
104};
Alison Wang30ea41a2013-06-17 15:30:39 +0800105#endif
Sascha Hauercdace062008-03-26 20:40:49 +0100106
tremfac96402013-09-21 18:13:35 +0200107#ifndef CONFIG_SYS_MXC_I2C1_SPEED
108#define CONFIG_SYS_MXC_I2C1_SPEED 100000
109#endif
110#ifndef CONFIG_SYS_MXC_I2C2_SPEED
111#define CONFIG_SYS_MXC_I2C2_SPEED 100000
112#endif
113#ifndef CONFIG_SYS_MXC_I2C3_SPEED
114#define CONFIG_SYS_MXC_I2C3_SPEED 100000
115#endif
York Sunf8cb1012015-03-20 10:20:40 -0700116#ifndef CONFIG_SYS_MXC_I2C4_SPEED
117#define CONFIG_SYS_MXC_I2C4_SPEED 100000
118#endif
tremfac96402013-09-21 18:13:35 +0200119
120#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
121#define CONFIG_SYS_MXC_I2C1_SLAVE 0
122#endif
123#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
124#define CONFIG_SYS_MXC_I2C2_SLAVE 0
125#endif
126#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
127#define CONFIG_SYS_MXC_I2C3_SLAVE 0
128#endif
York Sunf8cb1012015-03-20 10:20:40 -0700129#ifndef CONFIG_SYS_MXC_I2C4_SLAVE
130#define CONFIG_SYS_MXC_I2C4_SLAVE 0
131#endif
tremfac96402013-09-21 18:13:35 +0200132
Marek Vasutdb841402011-09-22 09:22:12 +0000133/*
134 * Calculate and set proper clock divider
135 */
Peng Fan71204e92015-05-15 07:29:12 +0800136static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
Stefano Babic1d549ad2011-01-20 07:50:44 +0000137{
Marek Vasutdb841402011-09-22 09:22:12 +0000138 unsigned int i2c_clk_rate;
139 unsigned int div;
Marek Vasutbf0783d2011-10-26 00:05:44 +0000140 u8 clk_div;
Sascha Hauercdace062008-03-26 20:40:49 +0100141
Liu Hui-R64343127cec12011-01-03 22:27:39 +0000142#if defined(CONFIG_MX31)
Stefano Babic1d549ad2011-01-20 07:50:44 +0000143 struct clock_control_regs *sc_regs =
144 (struct clock_control_regs *)CCM_BASE;
Marek Vasutdb841402011-09-22 09:22:12 +0000145
Guennadi Liakhovetskie7de18a2009-02-13 09:23:36 +0100146 /* start the required I2C clock */
Troy Kiskyde6f6042012-04-24 17:33:25 +0000147 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
Stefano Babic1d549ad2011-01-20 07:50:44 +0000148 &sc_regs->cgr0);
Liu Hui-R64343127cec12011-01-03 22:27:39 +0000149#endif
Guennadi Liakhovetskie7de18a2009-02-13 09:23:36 +0100150
Marek Vasutdb841402011-09-22 09:22:12 +0000151 /* Divider value calculation */
Matthias Weissere7bed5c2012-09-24 02:46:53 +0000152 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
Marek Vasutdb841402011-09-22 09:22:12 +0000153 div = (i2c_clk_rate + rate - 1) / rate;
154 if (div < i2c_clk_div[0][0])
Marek Vasutb567b8f2011-09-27 06:34:11 +0000155 clk_div = 0;
Marek Vasutdb841402011-09-22 09:22:12 +0000156 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
Marek Vasutb567b8f2011-09-27 06:34:11 +0000157 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
Marek Vasutdb841402011-09-22 09:22:12 +0000158 else
Marek Vasutb567b8f2011-09-27 06:34:11 +0000159 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
Marek Vasutdb841402011-09-22 09:22:12 +0000160 ;
Sascha Hauercdace062008-03-26 20:40:49 +0100161
Marek Vasutdb841402011-09-22 09:22:12 +0000162 /* Store divider value */
Marek Vasutbf0783d2011-10-26 00:05:44 +0000163 return clk_div;
Marek Vasutdb841402011-09-22 09:22:12 +0000164}
Sascha Hauercdace062008-03-26 20:40:49 +0100165
Marek Vasutdb841402011-09-22 09:22:12 +0000166/*
Troy Kiskye4ff5252012-07-19 08:18:18 +0000167 * Set I2C Bus speed
Marek Vasutdb841402011-09-22 09:22:12 +0000168 */
Peng Fan71204e92015-05-15 07:29:12 +0800169static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
Marek Vasutdb841402011-09-22 09:22:12 +0000170{
Peng Fan71204e92015-05-15 07:29:12 +0800171 ulong base = i2c_bus->base;
172 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
173 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
Marek Vasutbf0783d2011-10-26 00:05:44 +0000174 u8 idx = i2c_clk_div[clk_idx][1];
Peng Fan71204e92015-05-15 07:29:12 +0800175 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
Marek Vasutbf0783d2011-10-26 00:05:44 +0000176
Heiko Schochere6c8b712015-05-18 10:58:12 +0200177 if (!base)
Simon Glass7c843192017-09-17 16:54:53 -0600178 return -EINVAL;
Heiko Schochere6c8b712015-05-18 10:58:12 +0200179
Marek Vasutbf0783d2011-10-26 00:05:44 +0000180 /* Store divider value */
Peng Fan71204e92015-05-15 07:29:12 +0800181 writeb(idx, base + (IFDR << reg_shift));
Marek Vasutbf0783d2011-10-26 00:05:44 +0000182
Troy Kisky83a1a192012-07-19 08:18:12 +0000183 /* Reset module */
Peng Fan71204e92015-05-15 07:29:12 +0800184 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
185 writeb(0, base + (I2SR << reg_shift));
Marek Vasutb567b8f2011-09-27 06:34:11 +0000186 return 0;
187}
188
Troy Kisky7aa57a02012-07-19 08:18:09 +0000189#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
190#define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
191#define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
192
Peng Fan71204e92015-05-15 07:29:12 +0800193static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
Stefano Babic81687212011-01-20 07:51:31 +0000194{
Troy Kisky7aa57a02012-07-19 08:18:09 +0000195 unsigned sr;
196 ulong elapsed;
Peng Fan71204e92015-05-15 07:29:12 +0800197 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
198 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
199 ulong base = i2c_bus->base;
Troy Kisky7aa57a02012-07-19 08:18:09 +0000200 ulong start_time = get_timer(0);
201 for (;;) {
Peng Fan71204e92015-05-15 07:29:12 +0800202 sr = readb(base + (I2SR << reg_shift));
Troy Kiskyd5383a62012-07-19 08:18:15 +0000203 if (sr & I2SR_IAL) {
Peng Fan71204e92015-05-15 07:29:12 +0800204 if (quirk)
205 writeb(sr | I2SR_IAL, base +
206 (I2SR << reg_shift));
207 else
208 writeb(sr & ~I2SR_IAL, base +
209 (I2SR << reg_shift));
Troy Kiskyd5383a62012-07-19 08:18:15 +0000210 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
Peng Fan71204e92015-05-15 07:29:12 +0800211 __func__, sr, readb(base + (I2CR << reg_shift)),
212 state);
Troy Kiskyd5383a62012-07-19 08:18:15 +0000213 return -ERESTART;
214 }
Troy Kisky7aa57a02012-07-19 08:18:09 +0000215 if ((sr & (state >> 8)) == (unsigned char)state)
216 return sr;
217 WATCHDOG_RESET();
218 elapsed = get_timer(start_time);
219 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
220 break;
Stefano Babic81687212011-01-20 07:51:31 +0000221 }
Troy Kisky7aa57a02012-07-19 08:18:09 +0000222 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
Peng Fan71204e92015-05-15 07:29:12 +0800223 sr, readb(base + (I2CR << reg_shift)), state);
Troy Kiskycea60b02012-07-19 08:18:04 +0000224 return -ETIMEDOUT;
Stefano Babic81687212011-01-20 07:51:31 +0000225}
226
Peng Fan71204e92015-05-15 07:29:12 +0800227static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
Sascha Hauercdace062008-03-26 20:40:49 +0100228{
Troy Kiskycea60b02012-07-19 08:18:04 +0000229 int ret;
Peng Fan71204e92015-05-15 07:29:12 +0800230 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
231 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
232 ulong base = i2c_bus->base;
Sascha Hauercdace062008-03-26 20:40:49 +0100233
Peng Fan71204e92015-05-15 07:29:12 +0800234 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
235 writeb(byte, base + (I2DR << reg_shift));
236
237 ret = wait_for_sr_state(i2c_bus, ST_IIF);
Troy Kiskycea60b02012-07-19 08:18:04 +0000238 if (ret < 0)
239 return ret;
Troy Kiskycea60b02012-07-19 08:18:04 +0000240 if (ret & I2SR_RX_NO_AK)
Simon Glass7c843192017-09-17 16:54:53 -0600241 return -EREMOTEIO;
Troy Kiskycea60b02012-07-19 08:18:04 +0000242 return 0;
Marek Vasutdb841402011-09-22 09:22:12 +0000243}
244
245/*
Peng Fan71204e92015-05-15 07:29:12 +0800246 * Stub implementations for outer i2c slave operations.
247 */
248void __i2c_force_reset_slave(void)
249{
250}
251void i2c_force_reset_slave(void)
252 __attribute__((weak, alias("__i2c_force_reset_slave")));
253
254/*
Troy Kisky90a5b702012-07-19 08:18:13 +0000255 * Stop I2C transaction
Marek Vasutdb841402011-09-22 09:22:12 +0000256 */
Peng Fan71204e92015-05-15 07:29:12 +0800257static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
Sascha Hauercdace062008-03-26 20:40:49 +0100258{
Troy Kisky7aa57a02012-07-19 08:18:09 +0000259 int ret;
Peng Fan71204e92015-05-15 07:29:12 +0800260 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
261 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
262 ulong base = i2c_bus->base;
263 unsigned int temp = readb(base + (I2CR << reg_shift));
Sascha Hauercdace062008-03-26 20:40:49 +0100264
Troy Kisky1c076db2012-07-19 08:18:02 +0000265 temp &= ~(I2CR_MSTA | I2CR_MTX);
Peng Fan71204e92015-05-15 07:29:12 +0800266 writeb(temp, base + (I2CR << reg_shift));
267 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
Troy Kisky7aa57a02012-07-19 08:18:09 +0000268 if (ret < 0)
269 printf("%s:trigger stop failed\n", __func__);
Sascha Hauercdace062008-03-26 20:40:49 +0100270}
271
Marek Vasutdb841402011-09-22 09:22:12 +0000272/*
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000273 * Send start signal, chip address and
274 * write register address
Marek Vasutdb841402011-09-22 09:22:12 +0000275 */
Peng Fan71204e92015-05-15 07:29:12 +0800276static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
277 u32 addr, int alen)
Sascha Hauercdace062008-03-26 20:40:49 +0100278{
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000279 unsigned int temp;
280 int ret;
Peng Fan71204e92015-05-15 07:29:12 +0800281 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
282 ulong base = i2c_bus->base;
283 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
284
285 /* Reset i2c slave */
286 i2c_force_reset_slave();
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000287
288 /* Enable I2C controller */
Peng Fan71204e92015-05-15 07:29:12 +0800289 if (quirk)
290 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
291 else
292 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
293
294 if (ret) {
295 writeb(I2CR_IEN, base + (I2CR << reg_shift));
Troy Kisky90a5b702012-07-19 08:18:13 +0000296 /* Wait for controller to be stable */
297 udelay(50);
298 }
Peng Fan71204e92015-05-15 07:29:12 +0800299
300 if (readb(base + (IADR << reg_shift)) == (chip << 1))
301 writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
302 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
303 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
Troy Kisky90a5b702012-07-19 08:18:13 +0000304 if (ret < 0)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000305 return ret;
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000306
307 /* Start I2C transaction */
Peng Fan71204e92015-05-15 07:29:12 +0800308 temp = readb(base + (I2CR << reg_shift));
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000309 temp |= I2CR_MSTA;
Peng Fan71204e92015-05-15 07:29:12 +0800310 writeb(temp, base + (I2CR << reg_shift));
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000311
Peng Fan71204e92015-05-15 07:29:12 +0800312 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000313 if (ret < 0)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000314 return ret;
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000315
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000316 temp |= I2CR_MTX | I2CR_TX_NO_AK;
Peng Fan71204e92015-05-15 07:29:12 +0800317 writeb(temp, base + (I2CR << reg_shift));
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000318
Nandor Han2feec4e2017-11-08 15:35:09 +0000319 if (alen >= 0) {
320 /* write slave address */
321 ret = tx_byte(i2c_bus, chip << 1);
Troy Kiskycea60b02012-07-19 08:18:04 +0000322 if (ret < 0)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000323 return ret;
Nandor Han2feec4e2017-11-08 15:35:09 +0000324
325 while (alen--) {
326 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
327 if (ret < 0)
328 return ret;
329 }
Stefano Babic81687212011-01-20 07:51:31 +0000330 }
Nandor Han2feec4e2017-11-08 15:35:09 +0000331
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000332 return 0;
Troy Kiskya7f1a002012-07-19 08:18:16 +0000333}
334
Peng Fan71204e92015-05-15 07:29:12 +0800335#ifndef CONFIG_DM_I2C
336int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
337{
338 if (i2c_bus && i2c_bus->idle_bus_fn)
339 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
340 return 0;
341}
342#else
343/*
Peng Fane1bed802016-03-11 16:47:50 +0800344 * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
345 * "
346 * scl-gpios: specify the gpio related to SCL pin
347 * sda-gpios: specify the gpio related to SDA pin
348 * add pinctrl to configure i2c pins to gpio function for i2c
349 * bus recovery, call it "gpio" state
350 * "
351 *
352 * The i2c_idle_bus is an implementation following Linux Kernel.
Peng Fan71204e92015-05-15 07:29:12 +0800353 */
Peng Fan71204e92015-05-15 07:29:12 +0800354int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
Peng Fane1bed802016-03-11 16:47:50 +0800355{
356 struct udevice *bus = i2c_bus->bus;
357 struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
358 struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
359 int sda, scl;
360 int i, ret = 0;
361 ulong elapsed, start_time;
362
363 if (pinctrl_select_state(bus, "gpio")) {
364 dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
365 /*
366 * GPIO pinctrl for i2c force idle is not a must,
367 * but it is strongly recommended to be used.
368 * Because it can help you to recover from bad
369 * i2c bus state. Do not return failure, because
370 * it is not a must.
371 */
372 return 0;
373 }
374
375 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
376 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
377 scl = dm_gpio_get_value(scl_gpio);
378 sda = dm_gpio_get_value(sda_gpio);
379
380 if ((sda & scl) == 1)
381 goto exit; /* Bus is idle already */
382
383 /* Send high and low on the SCL line */
384 for (i = 0; i < 9; i++) {
385 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
386 dm_gpio_set_value(scl_gpio, 0);
387 udelay(50);
388 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
389 udelay(50);
390 }
391 start_time = get_timer(0);
392 for (;;) {
393 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
394 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
395 scl = dm_gpio_get_value(scl_gpio);
396 sda = dm_gpio_get_value(sda_gpio);
397 if ((sda & scl) == 1)
398 break;
399 WATCHDOG_RESET();
400 elapsed = get_timer(start_time);
401 if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
402 ret = -EBUSY;
403 printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
404 break;
405 }
406 }
407
408exit:
409 pinctrl_select_state(bus, "default");
410 return ret;
411}
Peng Fan71204e92015-05-15 07:29:12 +0800412#endif
413
414static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
415 u32 addr, int alen)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000416{
417 int retry;
418 int ret;
Peng Fan71204e92015-05-15 07:29:12 +0800419 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
420 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
Heiko Schochere6c8b712015-05-18 10:58:12 +0200421
422 if (!i2c_bus->base)
Simon Glass7c843192017-09-17 16:54:53 -0600423 return -EINVAL;
Heiko Schochere6c8b712015-05-18 10:58:12 +0200424
Troy Kiskya7f1a002012-07-19 08:18:16 +0000425 for (retry = 0; retry < 3; retry++) {
Peng Fan71204e92015-05-15 07:29:12 +0800426 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
Troy Kiskya7f1a002012-07-19 08:18:16 +0000427 if (ret >= 0)
428 return 0;
Peng Fan71204e92015-05-15 07:29:12 +0800429 i2c_imx_stop(i2c_bus);
Simon Glass7c843192017-09-17 16:54:53 -0600430 if (ret == -EREMOTEIO)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000431 return ret;
432
433 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
434 retry);
435 if (ret != -ERESTART)
Alison Wang30ea41a2013-06-17 15:30:39 +0800436 /* Disable controller */
Peng Fan71204e92015-05-15 07:29:12 +0800437 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
Troy Kiskya7f1a002012-07-19 08:18:16 +0000438 udelay(100);
Peng Fan71204e92015-05-15 07:29:12 +0800439 if (i2c_idle_bus(i2c_bus) < 0)
Troy Kisky96c19bd2012-07-19 08:18:19 +0000440 break;
Troy Kiskya7f1a002012-07-19 08:18:16 +0000441 }
Peng Fan71204e92015-05-15 07:29:12 +0800442 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
Marek Vasutdb841402011-09-22 09:22:12 +0000443 return ret;
Sascha Hauercdace062008-03-26 20:40:49 +0100444}
445
Peng Fan71204e92015-05-15 07:29:12 +0800446
447static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
448 int len)
449{
450 int i, ret = 0;
451
452 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
453 debug("write_data: ");
454 /* use rc for counter */
455 for (i = 0; i < len; ++i)
456 debug(" 0x%02x", buf[i]);
457 debug("\n");
458
459 for (i = 0; i < len; i++) {
460 ret = tx_byte(i2c_bus, buf[i]);
461 if (ret < 0) {
462 debug("i2c_write_data(): rc=%d\n", ret);
463 break;
464 }
465 }
466
467 return ret;
468}
469
470static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
471 int len)
Marek Vasutdb841402011-09-22 09:22:12 +0000472{
Marek Vasutdb841402011-09-22 09:22:12 +0000473 int ret;
474 unsigned int temp;
475 int i;
Peng Fan71204e92015-05-15 07:29:12 +0800476 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
477 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
478 ulong base = i2c_bus->base;
Marek Vasutdb841402011-09-22 09:22:12 +0000479
Peng Fan71204e92015-05-15 07:29:12 +0800480 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
Marek Vasutdb841402011-09-22 09:22:12 +0000481
482 /* setup bus to read data */
Peng Fan71204e92015-05-15 07:29:12 +0800483 temp = readb(base + (I2CR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000484 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
485 if (len == 1)
486 temp |= I2CR_TX_NO_AK;
Peng Fan71204e92015-05-15 07:29:12 +0800487 writeb(temp, base + (I2CR << reg_shift));
488 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
489 /* dummy read to clear ICF */
490 readb(base + (I2DR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000491
492 /* read data */
493 for (i = 0; i < len; i++) {
Peng Fan71204e92015-05-15 07:29:12 +0800494 ret = wait_for_sr_state(i2c_bus, ST_IIF);
Troy Kisky7aa57a02012-07-19 08:18:09 +0000495 if (ret < 0) {
Peng Fan71204e92015-05-15 07:29:12 +0800496 debug("i2c_read_data(): ret=%d\n", ret);
497 i2c_imx_stop(i2c_bus);
Marek Vasutdb841402011-09-22 09:22:12 +0000498 return ret;
Troy Kiskyc4330d22012-07-19 08:18:07 +0000499 }
Marek Vasutdb841402011-09-22 09:22:12 +0000500
501 /*
502 * It must generate STOP before read I2DR to prevent
503 * controller from generating another clock cycle
504 */
505 if (i == (len - 1)) {
Peng Fan71204e92015-05-15 07:29:12 +0800506 i2c_imx_stop(i2c_bus);
Marek Vasutdb841402011-09-22 09:22:12 +0000507 } else if (i == (len - 2)) {
Peng Fan71204e92015-05-15 07:29:12 +0800508 temp = readb(base + (I2CR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000509 temp |= I2CR_TX_NO_AK;
Peng Fan71204e92015-05-15 07:29:12 +0800510 writeb(temp, base + (I2CR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000511 }
Peng Fan71204e92015-05-15 07:29:12 +0800512 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
513 buf[i] = readb(base + (I2DR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000514 }
Peng Fan71204e92015-05-15 07:29:12 +0800515
516 /* reuse ret for counter*/
517 for (ret = 0; ret < len; ++ret)
518 debug(" 0x%02x", buf[ret]);
519 debug("\n");
520
521 i2c_imx_stop(i2c_bus);
Troy Kisky7aa57a02012-07-19 08:18:09 +0000522 return 0;
Marek Vasutdb841402011-09-22 09:22:12 +0000523}
524
Peng Fan71204e92015-05-15 07:29:12 +0800525#ifndef CONFIG_DM_I2C
526/*
527 * Read data from I2C device
528 */
529static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
530 int alen, u8 *buf, int len)
531{
532 int ret = 0;
533 u32 temp;
534 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
535 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
536 ulong base = i2c_bus->base;
537
538 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
539 if (ret < 0)
540 return ret;
541
Nandor Han2feec4e2017-11-08 15:35:09 +0000542 if (alen >= 0) {
543 temp = readb(base + (I2CR << reg_shift));
544 temp |= I2CR_RSTA;
545 writeb(temp, base + (I2CR << reg_shift));
546 }
Peng Fan71204e92015-05-15 07:29:12 +0800547
548 ret = tx_byte(i2c_bus, (chip << 1) | 1);
549 if (ret < 0) {
550 i2c_imx_stop(i2c_bus);
551 return ret;
552 }
553
554 ret = i2c_read_data(i2c_bus, chip, buf, len);
555
556 i2c_imx_stop(i2c_bus);
557 return ret;
558}
559
Marek Vasutdb841402011-09-22 09:22:12 +0000560/*
561 * Write data to I2C device
562 */
Peng Fan71204e92015-05-15 07:29:12 +0800563static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
564 int alen, const u8 *buf, int len)
Sascha Hauercdace062008-03-26 20:40:49 +0100565{
Peng Fan71204e92015-05-15 07:29:12 +0800566 int ret = 0;
Sascha Hauercdace062008-03-26 20:40:49 +0100567
Peng Fan71204e92015-05-15 07:29:12 +0800568 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
Troy Kiskycea60b02012-07-19 08:18:04 +0000569 if (ret < 0)
Marek Vasutdb841402011-09-22 09:22:12 +0000570 return ret;
Sascha Hauercdace062008-03-26 20:40:49 +0100571
Peng Fan71204e92015-05-15 07:29:12 +0800572 ret = i2c_write_data(i2c_bus, chip, buf, len);
573
574 i2c_imx_stop(i2c_bus);
575
Marek Vasutdb841402011-09-22 09:22:12 +0000576 return ret;
Sascha Hauercdace062008-03-26 20:40:49 +0100577}
Troy Kiskycfbb88d2012-07-19 08:18:08 +0000578
Heiko Schochere6c8b712015-05-18 10:58:12 +0200579#if !defined(I2C2_BASE_ADDR)
580#define I2C2_BASE_ADDR 0
Heiko Schocher21a26942015-05-18 10:56:24 +0200581#endif
Heiko Schochere6c8b712015-05-18 10:58:12 +0200582
583#if !defined(I2C3_BASE_ADDR)
584#define I2C3_BASE_ADDR 0
585#endif
586
587#if !defined(I2C4_BASE_ADDR)
588#define I2C4_BASE_ADDR 0
589#endif
590
Sriram Dashfa452192018-02-06 11:26:31 +0530591#if !defined(I2C5_BASE_ADDR)
592#define I2C5_BASE_ADDR 0
593#endif
594
595#if !defined(I2C6_BASE_ADDR)
596#define I2C6_BASE_ADDR 0
597#endif
598
599#if !defined(I2C7_BASE_ADDR)
600#define I2C7_BASE_ADDR 0
601#endif
602
603#if !defined(I2C8_BASE_ADDR)
604#define I2C8_BASE_ADDR 0
605#endif
606
Heiko Schochere6c8b712015-05-18 10:58:12 +0200607static struct mxc_i2c_bus mxc_i2c_buses[] = {
York Sun73fb5832017-03-27 11:41:03 -0700608#if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
Mingkai Hu9f3183d2015-10-26 19:47:50 +0800609 defined(CONFIG_FSL_LAYERSCAPE)
Peng Fan71204e92015-05-15 07:29:12 +0800610 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
611 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
612 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
613 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
Sriram Dashfa452192018-02-06 11:26:31 +0530614 { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
615 { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
616 { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
617 { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
Troy Kiskye4ff5252012-07-19 08:18:18 +0000618#else
Heiko Schochere6c8b712015-05-18 10:58:12 +0200619 { 0, I2C1_BASE_ADDR, 0 },
620 { 1, I2C2_BASE_ADDR, 0 },
621 { 2, I2C3_BASE_ADDR, 0 },
622 { 3, I2C4_BASE_ADDR, 0 },
Sriram Dashfa452192018-02-06 11:26:31 +0530623 { 4, I2C5_BASE_ADDR, 0 },
624 { 5, I2C6_BASE_ADDR, 0 },
625 { 6, I2C7_BASE_ADDR, 0 },
626 { 7, I2C8_BASE_ADDR, 0 },
Troy Kiskye4ff5252012-07-19 08:18:18 +0000627#endif
tremfac96402013-09-21 18:13:35 +0200628};
629
Peng Fan71204e92015-05-15 07:29:12 +0800630struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
tremfac96402013-09-21 18:13:35 +0200631{
Peng Fan71204e92015-05-15 07:29:12 +0800632 return &mxc_i2c_buses[adap->hwadapnr];
Troy Kisky96c19bd2012-07-19 08:18:19 +0000633}
634
tremfac96402013-09-21 18:13:35 +0200635static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
636 uint addr, int alen, uint8_t *buffer,
637 int len)
Troy Kisky98153262012-07-19 08:18:20 +0000638{
tremfac96402013-09-21 18:13:35 +0200639 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
Troy Kisky98153262012-07-19 08:18:20 +0000640}
641
tremfac96402013-09-21 18:13:35 +0200642static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
643 uint addr, int alen, uint8_t *buffer,
644 int len)
Troy Kisky98153262012-07-19 08:18:20 +0000645{
tremfac96402013-09-21 18:13:35 +0200646 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000647}
648
Troy Kiskycfbb88d2012-07-19 08:18:08 +0000649/*
650 * Test if a chip at a given address responds (probe the chip)
651 */
tremfac96402013-09-21 18:13:35 +0200652static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
Troy Kiskycfbb88d2012-07-19 08:18:08 +0000653{
tremfac96402013-09-21 18:13:35 +0200654 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000655}
656
Peng Fan71204e92015-05-15 07:29:12 +0800657int __enable_i2c_clk(unsigned char enable, unsigned i2c_num)
Troy Kiskye4ff5252012-07-19 08:18:18 +0000658{
Peng Fan71204e92015-05-15 07:29:12 +0800659 return 1;
660}
661int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
662 __attribute__((weak, alias("__enable_i2c_clk")));
663
664void bus_i2c_init(int index, int speed, int unused,
665 int (*idle_bus_fn)(void *p), void *idle_bus_data)
666{
667 int ret;
668
669 if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
670 debug("Error i2c index\n");
Troy Kiskye4ff5252012-07-19 08:18:18 +0000671 return;
Troy Kiskye4ff5252012-07-19 08:18:18 +0000672 }
Peng Fan71204e92015-05-15 07:29:12 +0800673
Gong Qianyuaee3fdd2015-12-18 17:38:01 +0800674 /*
675 * Warning: Be careful to allow the assignment to a static
676 * variable here. This function could be called while U-Boot is
677 * still running in flash memory. So such assignment is equal
678 * to write data to flash without erasing.
679 */
680 if (idle_bus_fn)
681 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
682 if (idle_bus_data)
683 mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
Peng Fan71204e92015-05-15 07:29:12 +0800684
685 ret = enable_i2c_clk(1, index);
686 if (ret < 0) {
687 debug("I2C-%d clk fail to enable.\n", index);
688 return;
689 }
690
691 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000692}
693
694/*
Yuan Yao9d10c2d2016-06-08 18:24:51 +0800695 * Early init I2C for prepare read the clk through I2C.
696 */
697void i2c_early_init_f(void)
698{
699 ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
700 bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
701 & I2C_QUIRK_FLAG ? true : false;
702 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
703
704 /* Set I2C divider value */
705 writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
706 /* Reset module */
707 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
708 writeb(0, base + (I2SR << reg_shift));
709 /* Enable I2C */
710 writeb(I2CR_IEN, base + (I2CR << reg_shift));
711}
712
713/*
Troy Kiskye4ff5252012-07-19 08:18:18 +0000714 * Init I2C Bus
715 */
tremfac96402013-09-21 18:13:35 +0200716static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
Troy Kiskye4ff5252012-07-19 08:18:18 +0000717{
Peng Fan71204e92015-05-15 07:29:12 +0800718 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000719}
720
721/*
722 * Set I2C Speed
723 */
Peng Fan71204e92015-05-15 07:29:12 +0800724static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
Troy Kiskye4ff5252012-07-19 08:18:18 +0000725{
tremfac96402013-09-21 18:13:35 +0200726 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000727}
728
729/*
tremfac96402013-09-21 18:13:35 +0200730 * Register mxc i2c adapters
Troy Kiskye4ff5252012-07-19 08:18:18 +0000731 */
Albert ARIBAUD \\(3ADEV\\)03544c62015-09-21 22:43:38 +0200732#ifdef CONFIG_SYS_I2C_MXC_I2C1
tremfac96402013-09-21 18:13:35 +0200733U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
734 mxc_i2c_read, mxc_i2c_write,
735 mxc_i2c_set_bus_speed,
736 CONFIG_SYS_MXC_I2C1_SPEED,
737 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
Albert ARIBAUD \\(3ADEV\\)03544c62015-09-21 22:43:38 +0200738#endif
739
740#ifdef CONFIG_SYS_I2C_MXC_I2C2
tremfac96402013-09-21 18:13:35 +0200741U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
742 mxc_i2c_read, mxc_i2c_write,
743 mxc_i2c_set_bus_speed,
744 CONFIG_SYS_MXC_I2C2_SPEED,
745 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
Albert ARIBAUD \\(3ADEV\\)03544c62015-09-21 22:43:38 +0200746#endif
747
York Sunf8cb1012015-03-20 10:20:40 -0700748#ifdef CONFIG_SYS_I2C_MXC_I2C3
tremfac96402013-09-21 18:13:35 +0200749U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
750 mxc_i2c_read, mxc_i2c_write,
751 mxc_i2c_set_bus_speed,
752 CONFIG_SYS_MXC_I2C3_SPEED,
753 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
754#endif
Peng Fan71204e92015-05-15 07:29:12 +0800755
York Sunf8cb1012015-03-20 10:20:40 -0700756#ifdef CONFIG_SYS_I2C_MXC_I2C4
757U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
758 mxc_i2c_read, mxc_i2c_write,
759 mxc_i2c_set_bus_speed,
760 CONFIG_SYS_MXC_I2C4_SPEED,
761 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
762#endif
Peng Fan71204e92015-05-15 07:29:12 +0800763
Sriram Dashfa452192018-02-06 11:26:31 +0530764#ifdef CONFIG_SYS_I2C_MXC_I2C5
765U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe,
766 mxc_i2c_read, mxc_i2c_write,
767 mxc_i2c_set_bus_speed,
768 CONFIG_SYS_MXC_I2C5_SPEED,
769 CONFIG_SYS_MXC_I2C5_SLAVE, 4)
770#endif
771
772#ifdef CONFIG_SYS_I2C_MXC_I2C6
773U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe,
774 mxc_i2c_read, mxc_i2c_write,
775 mxc_i2c_set_bus_speed,
776 CONFIG_SYS_MXC_I2C6_SPEED,
777 CONFIG_SYS_MXC_I2C6_SLAVE, 5)
778#endif
779
780#ifdef CONFIG_SYS_I2C_MXC_I2C7
781U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe,
782 mxc_i2c_read, mxc_i2c_write,
783 mxc_i2c_set_bus_speed,
784 CONFIG_SYS_MXC_I2C7_SPEED,
785 CONFIG_SYS_MXC_I2C7_SLAVE, 6)
786#endif
787
788#ifdef CONFIG_SYS_I2C_MXC_I2C8
789U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe,
790 mxc_i2c_read, mxc_i2c_write,
791 mxc_i2c_set_bus_speed,
792 CONFIG_SYS_MXC_I2C8_SPEED,
793 CONFIG_SYS_MXC_I2C8_SLAVE, 7)
794#endif
795
Peng Fan71204e92015-05-15 07:29:12 +0800796#else
797
798static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
799{
800 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
801
802 return bus_i2c_set_bus_speed(i2c_bus, speed);
803}
804
805static int mxc_i2c_probe(struct udevice *bus)
806{
807 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
Peng Fane1bed802016-03-11 16:47:50 +0800808 const void *fdt = gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -0700809 int node = dev_of_offset(bus);
Peng Fan71204e92015-05-15 07:29:12 +0800810 fdt_addr_t addr;
Peng Fane1bed802016-03-11 16:47:50 +0800811 int ret, ret2;
Peng Fan71204e92015-05-15 07:29:12 +0800812
813 i2c_bus->driver_data = dev_get_driver_data(bus);
814
Simon Glassa821c4a2017-05-17 17:18:05 -0600815 addr = devfdt_get_addr(bus);
Peng Fan71204e92015-05-15 07:29:12 +0800816 if (addr == FDT_ADDR_T_NONE)
Simon Glass7c843192017-09-17 16:54:53 -0600817 return -EINVAL;
Peng Fan71204e92015-05-15 07:29:12 +0800818
819 i2c_bus->base = addr;
820 i2c_bus->index = bus->seq;
Peng Fane1bed802016-03-11 16:47:50 +0800821 i2c_bus->bus = bus;
Peng Fan71204e92015-05-15 07:29:12 +0800822
823 /* Enable clk */
824 ret = enable_i2c_clk(1, bus->seq);
825 if (ret < 0)
826 return ret;
827
Peng Fane1bed802016-03-11 16:47:50 +0800828 /*
829 * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
830 * Use gpio to force bus idle when necessary.
831 */
Simon Glassb02e4042016-10-02 17:59:28 -0600832 ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
Peng Fane1bed802016-03-11 16:47:50 +0800833 if (ret < 0) {
Jagan Teki2da24fe2016-12-06 00:00:59 +0100834 debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n", bus->seq, i2c_bus->base);
Peng Fane1bed802016-03-11 16:47:50 +0800835 } else {
Simon Glass150c5af2017-05-30 21:47:09 -0600836 ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
837 "scl-gpios", 0, &i2c_bus->scl_gpio,
838 GPIOD_IS_OUT);
839 ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
840 "sda-gpios", 0, &i2c_bus->sda_gpio,
841 GPIOD_IS_OUT);
Peng Fanfb012872017-12-29 15:06:08 +0800842 if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
843 !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
844 ret || ret2) {
Peng Fane1bed802016-03-11 16:47:50 +0800845 dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base);
Simon Glass7c843192017-09-17 16:54:53 -0600846 return -EINVAL;
Peng Fane1bed802016-03-11 16:47:50 +0800847 }
848 }
849
Peng Fan71204e92015-05-15 07:29:12 +0800850 ret = i2c_idle_bus(i2c_bus);
851 if (ret < 0) {
852 /* Disable clk */
853 enable_i2c_clk(0, bus->seq);
854 return ret;
855 }
856
857 /*
858 * Pinmux settings are in board file now, until pinmux is supported,
859 * we can set pinmux here in probe function.
860 */
861
862 debug("i2c : controller bus %d at %lu , speed %d: ",
863 bus->seq, i2c_bus->base,
864 i2c_bus->speed);
865
866 return 0;
867}
868
869static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
870 u32 chip_flags)
871{
872 int ret;
873 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
874
875 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
876 if (ret < 0) {
877 debug("%s failed, ret = %d\n", __func__, ret);
878 return ret;
879 }
880
881 i2c_imx_stop(i2c_bus);
882
883 return 0;
884}
885
886static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
887{
888 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
889 int ret = 0;
890 ulong base = i2c_bus->base;
891 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
892 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
893
894 /*
895 * Here the 3rd parameter addr and the 4th one alen are set to 0,
896 * because here we only want to send out chip address. The register
897 * address is wrapped in msg.
898 */
899 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, 0);
900 if (ret < 0) {
901 debug("i2c_init_transfer error: %d\n", ret);
902 return ret;
903 }
904
905 for (; nmsgs > 0; nmsgs--, msg++) {
906 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
907 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
908 if (msg->flags & I2C_M_RD)
909 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
910 msg->len);
911 else {
912 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
913 msg->len);
914 if (ret)
915 break;
916 if (next_is_read) {
917 /* Reuse ret */
918 ret = readb(base + (I2CR << reg_shift));
919 ret |= I2CR_RSTA;
920 writeb(ret, base + (I2CR << reg_shift));
921
922 ret = tx_byte(i2c_bus, (msg->addr << 1) | 1);
923 if (ret < 0) {
924 i2c_imx_stop(i2c_bus);
925 break;
926 }
927 }
928 }
929 }
930
931 if (ret)
932 debug("i2c_write: error sending\n");
933
934 i2c_imx_stop(i2c_bus);
935
936 return ret;
937}
938
939static const struct dm_i2c_ops mxc_i2c_ops = {
940 .xfer = mxc_i2c_xfer,
941 .probe_chip = mxc_i2c_probe_chip,
942 .set_bus_speed = mxc_i2c_set_bus_speed,
943};
944
945static const struct udevice_id mxc_i2c_ids[] = {
946 { .compatible = "fsl,imx21-i2c", },
947 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
948 {}
949};
950
951U_BOOT_DRIVER(i2c_mxc) = {
952 .name = "i2c_mxc",
953 .id = UCLASS_I2C,
954 .of_match = mxc_i2c_ids,
955 .probe = mxc_i2c_probe,
956 .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus),
957 .ops = &mxc_i2c_ops,
958};
959#endif