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Sascha Hauercdace062008-03-26 20:40:49 +01001/*
Marek Vasutdb841402011-09-22 09:22:12 +00002 * i2c driver for Freescale i.MX series
Sascha Hauercdace062008-03-26 20:40:49 +01003 *
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
Marek Vasutdb841402011-09-22 09:22:12 +00005 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
6 *
7 * Based on i2c-imx.c from linux kernel:
8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
10 * Copyright (C) 2007 RightHand Technologies, Inc.
11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
12 *
Sascha Hauercdace062008-03-26 20:40:49 +010013 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020014 * SPDX-License-Identifier: GPL-2.0+
Sascha Hauercdace062008-03-26 20:40:49 +010015 */
16
17#include <common.h>
Liu Hui-R64343127cec12011-01-03 22:27:39 +000018#include <asm/arch/clock.h>
Stefano Babic86271112011-03-14 15:43:56 +010019#include <asm/arch/imx-regs.h>
Troy Kiskycea60b02012-07-19 08:18:04 +000020#include <asm/errno.h>
Peng Fan71204e92015-05-15 07:29:12 +080021#include <asm/imx-common/mxc_i2c.h>
Troy Kisky24cd7382012-07-19 08:18:03 +000022#include <asm/io.h>
Marek Vasutbf0783d2011-10-26 00:05:44 +000023#include <i2c.h>
Troy Kisky7aa57a02012-07-19 08:18:09 +000024#include <watchdog.h>
Peng Fan71204e92015-05-15 07:29:12 +080025#include <dm.h>
26#include <fdtdec.h>
Sascha Hauercdace062008-03-26 20:40:49 +010027
York Sundec18612014-02-10 14:02:52 -080028DECLARE_GLOBAL_DATA_PTR;
29
Peng Fan71204e92015-05-15 07:29:12 +080030#define I2C_QUIRK_FLAG (1 << 0)
31
32#define IMX_I2C_REGSHIFT 2
33#define VF610_I2C_REGSHIFT 0
34/* Register index */
35#define IADR 0
36#define IFDR 1
37#define I2CR 2
38#define I2SR 3
39#define I2DR 4
Sascha Hauercdace062008-03-26 20:40:49 +010040
Sascha Hauercdace062008-03-26 20:40:49 +010041#define I2CR_IIEN (1 << 6)
42#define I2CR_MSTA (1 << 5)
43#define I2CR_MTX (1 << 4)
44#define I2CR_TX_NO_AK (1 << 3)
45#define I2CR_RSTA (1 << 2)
46
47#define I2SR_ICF (1 << 7)
48#define I2SR_IBB (1 << 5)
Troy Kiskyd5383a62012-07-19 08:18:15 +000049#define I2SR_IAL (1 << 4)
Sascha Hauercdace062008-03-26 20:40:49 +010050#define I2SR_IIF (1 << 1)
51#define I2SR_RX_NO_AK (1 << 0)
52
Alison Wang30ea41a2013-06-17 15:30:39 +080053#ifdef I2C_QUIRK_REG
54#define I2CR_IEN (0 << 7)
55#define I2CR_IDIS (1 << 7)
56#define I2SR_IIF_CLEAR (1 << 1)
57#else
58#define I2CR_IEN (1 << 7)
59#define I2CR_IDIS (0 << 7)
60#define I2SR_IIF_CLEAR (0 << 1)
61#endif
62
Troy Kiskye4ff5252012-07-19 08:18:18 +000063#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
Troy Kiskyde6f6042012-04-24 17:33:25 +000064#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
Sascha Hauercdace062008-03-26 20:40:49 +010065#endif
66
Alison Wang30ea41a2013-06-17 15:30:39 +080067#ifdef I2C_QUIRK_REG
68static u16 i2c_clk_div[60][2] = {
69 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
70 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
71 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
72 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
73 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
74 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
75 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
76 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
77 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
78 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
79 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
80 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
81 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
82 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
83 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
84};
85#else
Marek Vasutdb841402011-09-22 09:22:12 +000086static u16 i2c_clk_div[50][2] = {
87 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
88 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
89 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
90 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
91 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
92 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
93 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
94 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
95 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
96 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
97 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
98 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
99 { 3072, 0x1E }, { 3840, 0x1F }
100};
Alison Wang30ea41a2013-06-17 15:30:39 +0800101#endif
Sascha Hauercdace062008-03-26 20:40:49 +0100102
tremfac96402013-09-21 18:13:35 +0200103#ifndef CONFIG_SYS_MXC_I2C1_SPEED
104#define CONFIG_SYS_MXC_I2C1_SPEED 100000
105#endif
106#ifndef CONFIG_SYS_MXC_I2C2_SPEED
107#define CONFIG_SYS_MXC_I2C2_SPEED 100000
108#endif
109#ifndef CONFIG_SYS_MXC_I2C3_SPEED
110#define CONFIG_SYS_MXC_I2C3_SPEED 100000
111#endif
York Sunf8cb1012015-03-20 10:20:40 -0700112#ifndef CONFIG_SYS_MXC_I2C4_SPEED
113#define CONFIG_SYS_MXC_I2C4_SPEED 100000
114#endif
tremfac96402013-09-21 18:13:35 +0200115
116#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
117#define CONFIG_SYS_MXC_I2C1_SLAVE 0
118#endif
119#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
120#define CONFIG_SYS_MXC_I2C2_SLAVE 0
121#endif
122#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
123#define CONFIG_SYS_MXC_I2C3_SLAVE 0
124#endif
York Sunf8cb1012015-03-20 10:20:40 -0700125#ifndef CONFIG_SYS_MXC_I2C4_SLAVE
126#define CONFIG_SYS_MXC_I2C4_SLAVE 0
127#endif
tremfac96402013-09-21 18:13:35 +0200128
Marek Vasutdb841402011-09-22 09:22:12 +0000129/*
130 * Calculate and set proper clock divider
131 */
Peng Fan71204e92015-05-15 07:29:12 +0800132static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
Stefano Babic1d549ad2011-01-20 07:50:44 +0000133{
Marek Vasutdb841402011-09-22 09:22:12 +0000134 unsigned int i2c_clk_rate;
135 unsigned int div;
Marek Vasutbf0783d2011-10-26 00:05:44 +0000136 u8 clk_div;
Sascha Hauercdace062008-03-26 20:40:49 +0100137
Liu Hui-R64343127cec12011-01-03 22:27:39 +0000138#if defined(CONFIG_MX31)
Stefano Babic1d549ad2011-01-20 07:50:44 +0000139 struct clock_control_regs *sc_regs =
140 (struct clock_control_regs *)CCM_BASE;
Marek Vasutdb841402011-09-22 09:22:12 +0000141
Guennadi Liakhovetskie7de18a2009-02-13 09:23:36 +0100142 /* start the required I2C clock */
Troy Kiskyde6f6042012-04-24 17:33:25 +0000143 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
Stefano Babic1d549ad2011-01-20 07:50:44 +0000144 &sc_regs->cgr0);
Liu Hui-R64343127cec12011-01-03 22:27:39 +0000145#endif
Guennadi Liakhovetskie7de18a2009-02-13 09:23:36 +0100146
Marek Vasutdb841402011-09-22 09:22:12 +0000147 /* Divider value calculation */
Matthias Weissere7bed5c2012-09-24 02:46:53 +0000148 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
Marek Vasutdb841402011-09-22 09:22:12 +0000149 div = (i2c_clk_rate + rate - 1) / rate;
150 if (div < i2c_clk_div[0][0])
Marek Vasutb567b8f2011-09-27 06:34:11 +0000151 clk_div = 0;
Marek Vasutdb841402011-09-22 09:22:12 +0000152 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
Marek Vasutb567b8f2011-09-27 06:34:11 +0000153 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
Marek Vasutdb841402011-09-22 09:22:12 +0000154 else
Marek Vasutb567b8f2011-09-27 06:34:11 +0000155 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
Marek Vasutdb841402011-09-22 09:22:12 +0000156 ;
Sascha Hauercdace062008-03-26 20:40:49 +0100157
Marek Vasutdb841402011-09-22 09:22:12 +0000158 /* Store divider value */
Marek Vasutbf0783d2011-10-26 00:05:44 +0000159 return clk_div;
Marek Vasutdb841402011-09-22 09:22:12 +0000160}
Sascha Hauercdace062008-03-26 20:40:49 +0100161
Marek Vasutdb841402011-09-22 09:22:12 +0000162/*
Troy Kiskye4ff5252012-07-19 08:18:18 +0000163 * Set I2C Bus speed
Marek Vasutdb841402011-09-22 09:22:12 +0000164 */
Peng Fan71204e92015-05-15 07:29:12 +0800165static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
Marek Vasutdb841402011-09-22 09:22:12 +0000166{
Peng Fan71204e92015-05-15 07:29:12 +0800167 ulong base = i2c_bus->base;
168 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
169 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
Marek Vasutbf0783d2011-10-26 00:05:44 +0000170 u8 idx = i2c_clk_div[clk_idx][1];
Peng Fan71204e92015-05-15 07:29:12 +0800171 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
Marek Vasutbf0783d2011-10-26 00:05:44 +0000172
173 /* Store divider value */
Peng Fan71204e92015-05-15 07:29:12 +0800174 writeb(idx, base + (IFDR << reg_shift));
Marek Vasutbf0783d2011-10-26 00:05:44 +0000175
Troy Kisky83a1a192012-07-19 08:18:12 +0000176 /* Reset module */
Peng Fan71204e92015-05-15 07:29:12 +0800177 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
178 writeb(0, base + (I2SR << reg_shift));
Marek Vasutb567b8f2011-09-27 06:34:11 +0000179 return 0;
180}
181
Troy Kisky7aa57a02012-07-19 08:18:09 +0000182#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
183#define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
184#define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
185
Peng Fan71204e92015-05-15 07:29:12 +0800186static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
Stefano Babic81687212011-01-20 07:51:31 +0000187{
Troy Kisky7aa57a02012-07-19 08:18:09 +0000188 unsigned sr;
189 ulong elapsed;
Peng Fan71204e92015-05-15 07:29:12 +0800190 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
191 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
192 ulong base = i2c_bus->base;
Troy Kisky7aa57a02012-07-19 08:18:09 +0000193 ulong start_time = get_timer(0);
194 for (;;) {
Peng Fan71204e92015-05-15 07:29:12 +0800195 sr = readb(base + (I2SR << reg_shift));
Troy Kiskyd5383a62012-07-19 08:18:15 +0000196 if (sr & I2SR_IAL) {
Peng Fan71204e92015-05-15 07:29:12 +0800197 if (quirk)
198 writeb(sr | I2SR_IAL, base +
199 (I2SR << reg_shift));
200 else
201 writeb(sr & ~I2SR_IAL, base +
202 (I2SR << reg_shift));
Troy Kiskyd5383a62012-07-19 08:18:15 +0000203 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
Peng Fan71204e92015-05-15 07:29:12 +0800204 __func__, sr, readb(base + (I2CR << reg_shift)),
205 state);
Troy Kiskyd5383a62012-07-19 08:18:15 +0000206 return -ERESTART;
207 }
Troy Kisky7aa57a02012-07-19 08:18:09 +0000208 if ((sr & (state >> 8)) == (unsigned char)state)
209 return sr;
210 WATCHDOG_RESET();
211 elapsed = get_timer(start_time);
212 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
213 break;
Stefano Babic81687212011-01-20 07:51:31 +0000214 }
Troy Kisky7aa57a02012-07-19 08:18:09 +0000215 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
Peng Fan71204e92015-05-15 07:29:12 +0800216 sr, readb(base + (I2CR << reg_shift)), state);
Troy Kiskycea60b02012-07-19 08:18:04 +0000217 return -ETIMEDOUT;
Stefano Babic81687212011-01-20 07:51:31 +0000218}
219
Peng Fan71204e92015-05-15 07:29:12 +0800220static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
Sascha Hauercdace062008-03-26 20:40:49 +0100221{
Troy Kiskycea60b02012-07-19 08:18:04 +0000222 int ret;
Peng Fan71204e92015-05-15 07:29:12 +0800223 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
224 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
225 ulong base = i2c_bus->base;
Sascha Hauercdace062008-03-26 20:40:49 +0100226
Peng Fan71204e92015-05-15 07:29:12 +0800227 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
228 writeb(byte, base + (I2DR << reg_shift));
229
230 ret = wait_for_sr_state(i2c_bus, ST_IIF);
Troy Kiskycea60b02012-07-19 08:18:04 +0000231 if (ret < 0)
232 return ret;
Troy Kiskycea60b02012-07-19 08:18:04 +0000233 if (ret & I2SR_RX_NO_AK)
234 return -ENODEV;
235 return 0;
Marek Vasutdb841402011-09-22 09:22:12 +0000236}
237
238/*
Peng Fan71204e92015-05-15 07:29:12 +0800239 * Stub implementations for outer i2c slave operations.
240 */
241void __i2c_force_reset_slave(void)
242{
243}
244void i2c_force_reset_slave(void)
245 __attribute__((weak, alias("__i2c_force_reset_slave")));
246
247/*
Troy Kisky90a5b702012-07-19 08:18:13 +0000248 * Stop I2C transaction
Marek Vasutdb841402011-09-22 09:22:12 +0000249 */
Peng Fan71204e92015-05-15 07:29:12 +0800250static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
Sascha Hauercdace062008-03-26 20:40:49 +0100251{
Troy Kisky7aa57a02012-07-19 08:18:09 +0000252 int ret;
Peng Fan71204e92015-05-15 07:29:12 +0800253 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
254 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
255 ulong base = i2c_bus->base;
256 unsigned int temp = readb(base + (I2CR << reg_shift));
Sascha Hauercdace062008-03-26 20:40:49 +0100257
Troy Kisky1c076db2012-07-19 08:18:02 +0000258 temp &= ~(I2CR_MSTA | I2CR_MTX);
Peng Fan71204e92015-05-15 07:29:12 +0800259 writeb(temp, base + (I2CR << reg_shift));
260 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
Troy Kisky7aa57a02012-07-19 08:18:09 +0000261 if (ret < 0)
262 printf("%s:trigger stop failed\n", __func__);
Sascha Hauercdace062008-03-26 20:40:49 +0100263}
264
Marek Vasutdb841402011-09-22 09:22:12 +0000265/*
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000266 * Send start signal, chip address and
267 * write register address
Marek Vasutdb841402011-09-22 09:22:12 +0000268 */
Peng Fan71204e92015-05-15 07:29:12 +0800269static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
270 u32 addr, int alen)
Sascha Hauercdace062008-03-26 20:40:49 +0100271{
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000272 unsigned int temp;
273 int ret;
Peng Fan71204e92015-05-15 07:29:12 +0800274 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
275 ulong base = i2c_bus->base;
276 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
277
278 /* Reset i2c slave */
279 i2c_force_reset_slave();
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000280
281 /* Enable I2C controller */
Peng Fan71204e92015-05-15 07:29:12 +0800282 if (quirk)
283 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
284 else
285 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
286
287 if (ret) {
288 writeb(I2CR_IEN, base + (I2CR << reg_shift));
Troy Kisky90a5b702012-07-19 08:18:13 +0000289 /* Wait for controller to be stable */
290 udelay(50);
291 }
Peng Fan71204e92015-05-15 07:29:12 +0800292
293 if (readb(base + (IADR << reg_shift)) == (chip << 1))
294 writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
295 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
296 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
Troy Kisky90a5b702012-07-19 08:18:13 +0000297 if (ret < 0)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000298 return ret;
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000299
300 /* Start I2C transaction */
Peng Fan71204e92015-05-15 07:29:12 +0800301 temp = readb(base + (I2CR << reg_shift));
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000302 temp |= I2CR_MSTA;
Peng Fan71204e92015-05-15 07:29:12 +0800303 writeb(temp, base + (I2CR << reg_shift));
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000304
Peng Fan71204e92015-05-15 07:29:12 +0800305 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000306 if (ret < 0)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000307 return ret;
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000308
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000309 temp |= I2CR_MTX | I2CR_TX_NO_AK;
Peng Fan71204e92015-05-15 07:29:12 +0800310 writeb(temp, base + (I2CR << reg_shift));
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000311
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000312 /* write slave address */
Peng Fan71204e92015-05-15 07:29:12 +0800313 ret = tx_byte(i2c_bus, chip << 1);
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000314 if (ret < 0)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000315 return ret;
Marek Vasutdb841402011-09-22 09:22:12 +0000316
Marek Vasutbf0783d2011-10-26 00:05:44 +0000317 while (alen--) {
Peng Fan71204e92015-05-15 07:29:12 +0800318 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
Troy Kiskycea60b02012-07-19 08:18:04 +0000319 if (ret < 0)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000320 return ret;
Stefano Babic81687212011-01-20 07:51:31 +0000321 }
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000322 return 0;
Troy Kiskya7f1a002012-07-19 08:18:16 +0000323}
324
Peng Fan71204e92015-05-15 07:29:12 +0800325#ifndef CONFIG_DM_I2C
326int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
327{
328 if (i2c_bus && i2c_bus->idle_bus_fn)
329 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
330 return 0;
331}
332#else
333/*
334 * Since pinmux is not supported, implement a weak function here.
335 * You can implement your i2c_bus_idle in board file. When pinctrl
336 * is supported, this can be removed.
337 */
338int __i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
339{
340 return 0;
341}
Troy Kisky96c19bd2012-07-19 08:18:19 +0000342
Peng Fan71204e92015-05-15 07:29:12 +0800343int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
344 __attribute__((weak, alias("__i2c_idle_bus")));
345#endif
346
347static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
348 u32 addr, int alen)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000349{
350 int retry;
351 int ret;
Peng Fan71204e92015-05-15 07:29:12 +0800352 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
353 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
Troy Kiskya7f1a002012-07-19 08:18:16 +0000354 for (retry = 0; retry < 3; retry++) {
Peng Fan71204e92015-05-15 07:29:12 +0800355 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
Troy Kiskya7f1a002012-07-19 08:18:16 +0000356 if (ret >= 0)
357 return 0;
Peng Fan71204e92015-05-15 07:29:12 +0800358 i2c_imx_stop(i2c_bus);
Troy Kiskya7f1a002012-07-19 08:18:16 +0000359 if (ret == -ENODEV)
360 return ret;
361
362 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
363 retry);
364 if (ret != -ERESTART)
Alison Wang30ea41a2013-06-17 15:30:39 +0800365 /* Disable controller */
Peng Fan71204e92015-05-15 07:29:12 +0800366 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
Troy Kiskya7f1a002012-07-19 08:18:16 +0000367 udelay(100);
Peng Fan71204e92015-05-15 07:29:12 +0800368 if (i2c_idle_bus(i2c_bus) < 0)
Troy Kisky96c19bd2012-07-19 08:18:19 +0000369 break;
Troy Kiskya7f1a002012-07-19 08:18:16 +0000370 }
Peng Fan71204e92015-05-15 07:29:12 +0800371 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
Marek Vasutdb841402011-09-22 09:22:12 +0000372 return ret;
Sascha Hauercdace062008-03-26 20:40:49 +0100373}
374
Peng Fan71204e92015-05-15 07:29:12 +0800375
376static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
377 int len)
378{
379 int i, ret = 0;
380
381 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
382 debug("write_data: ");
383 /* use rc for counter */
384 for (i = 0; i < len; ++i)
385 debug(" 0x%02x", buf[i]);
386 debug("\n");
387
388 for (i = 0; i < len; i++) {
389 ret = tx_byte(i2c_bus, buf[i]);
390 if (ret < 0) {
391 debug("i2c_write_data(): rc=%d\n", ret);
392 break;
393 }
394 }
395
396 return ret;
397}
398
399static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
400 int len)
Marek Vasutdb841402011-09-22 09:22:12 +0000401{
Marek Vasutdb841402011-09-22 09:22:12 +0000402 int ret;
403 unsigned int temp;
404 int i;
Peng Fan71204e92015-05-15 07:29:12 +0800405 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
406 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
407 ulong base = i2c_bus->base;
Marek Vasutdb841402011-09-22 09:22:12 +0000408
Peng Fan71204e92015-05-15 07:29:12 +0800409 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
Marek Vasutdb841402011-09-22 09:22:12 +0000410
411 /* setup bus to read data */
Peng Fan71204e92015-05-15 07:29:12 +0800412 temp = readb(base + (I2CR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000413 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
414 if (len == 1)
415 temp |= I2CR_TX_NO_AK;
Peng Fan71204e92015-05-15 07:29:12 +0800416 writeb(temp, base + (I2CR << reg_shift));
417 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
418 /* dummy read to clear ICF */
419 readb(base + (I2DR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000420
421 /* read data */
422 for (i = 0; i < len; i++) {
Peng Fan71204e92015-05-15 07:29:12 +0800423 ret = wait_for_sr_state(i2c_bus, ST_IIF);
Troy Kisky7aa57a02012-07-19 08:18:09 +0000424 if (ret < 0) {
Peng Fan71204e92015-05-15 07:29:12 +0800425 debug("i2c_read_data(): ret=%d\n", ret);
426 i2c_imx_stop(i2c_bus);
Marek Vasutdb841402011-09-22 09:22:12 +0000427 return ret;
Troy Kiskyc4330d22012-07-19 08:18:07 +0000428 }
Marek Vasutdb841402011-09-22 09:22:12 +0000429
430 /*
431 * It must generate STOP before read I2DR to prevent
432 * controller from generating another clock cycle
433 */
434 if (i == (len - 1)) {
Peng Fan71204e92015-05-15 07:29:12 +0800435 i2c_imx_stop(i2c_bus);
Marek Vasutdb841402011-09-22 09:22:12 +0000436 } else if (i == (len - 2)) {
Peng Fan71204e92015-05-15 07:29:12 +0800437 temp = readb(base + (I2CR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000438 temp |= I2CR_TX_NO_AK;
Peng Fan71204e92015-05-15 07:29:12 +0800439 writeb(temp, base + (I2CR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000440 }
Peng Fan71204e92015-05-15 07:29:12 +0800441 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
442 buf[i] = readb(base + (I2DR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000443 }
Peng Fan71204e92015-05-15 07:29:12 +0800444
445 /* reuse ret for counter*/
446 for (ret = 0; ret < len; ++ret)
447 debug(" 0x%02x", buf[ret]);
448 debug("\n");
449
450 i2c_imx_stop(i2c_bus);
Troy Kisky7aa57a02012-07-19 08:18:09 +0000451 return 0;
Marek Vasutdb841402011-09-22 09:22:12 +0000452}
453
Peng Fan71204e92015-05-15 07:29:12 +0800454#ifndef CONFIG_DM_I2C
455/*
456 * Read data from I2C device
457 */
458static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
459 int alen, u8 *buf, int len)
460{
461 int ret = 0;
462 u32 temp;
463 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
464 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
465 ulong base = i2c_bus->base;
466
467 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
468 if (ret < 0)
469 return ret;
470
471 temp = readb(base + (I2CR << reg_shift));
472 temp |= I2CR_RSTA;
473 writeb(temp, base + (I2CR << reg_shift));
474
475 ret = tx_byte(i2c_bus, (chip << 1) | 1);
476 if (ret < 0) {
477 i2c_imx_stop(i2c_bus);
478 return ret;
479 }
480
481 ret = i2c_read_data(i2c_bus, chip, buf, len);
482
483 i2c_imx_stop(i2c_bus);
484 return ret;
485}
486
Marek Vasutdb841402011-09-22 09:22:12 +0000487/*
488 * Write data to I2C device
489 */
Peng Fan71204e92015-05-15 07:29:12 +0800490static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
491 int alen, const u8 *buf, int len)
Sascha Hauercdace062008-03-26 20:40:49 +0100492{
Peng Fan71204e92015-05-15 07:29:12 +0800493 int ret = 0;
Sascha Hauercdace062008-03-26 20:40:49 +0100494
Peng Fan71204e92015-05-15 07:29:12 +0800495 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
Troy Kiskycea60b02012-07-19 08:18:04 +0000496 if (ret < 0)
Marek Vasutdb841402011-09-22 09:22:12 +0000497 return ret;
Sascha Hauercdace062008-03-26 20:40:49 +0100498
Peng Fan71204e92015-05-15 07:29:12 +0800499 ret = i2c_write_data(i2c_bus, chip, buf, len);
500
501 i2c_imx_stop(i2c_bus);
502
Marek Vasutdb841402011-09-22 09:22:12 +0000503 return ret;
Sascha Hauercdace062008-03-26 20:40:49 +0100504}
Troy Kiskycfbb88d2012-07-19 08:18:08 +0000505
Peng Fan71204e92015-05-15 07:29:12 +0800506static struct mxc_i2c_bus mxc_i2c_buses[] = {
tremfac96402013-09-21 18:13:35 +0200507#if defined(CONFIG_MX25)
Peng Fan71204e92015-05-15 07:29:12 +0800508 { 0, IMX_I2C_BASE },
509 { 1, IMX_I2C2_BASE },
510 { 2, IMX_I2C3_BASE },
tremfac96402013-09-21 18:13:35 +0200511#elif defined(CONFIG_MX27)
Peng Fan71204e92015-05-15 07:29:12 +0800512 { 0, IMX_I2C1_BASE },
513 { 1, IMX_I2C2_BASE },
tremfac96402013-09-21 18:13:35 +0200514#elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
515 defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
Peng Fan71204e92015-05-15 07:29:12 +0800516 defined(CONFIG_MX6)
517 { 0, I2C1_BASE_ADDR },
518 { 1, I2C2_BASE_ADDR },
519 { 2, I2C3_BASE_ADDR },
520#elif defined(CONFIG_LS102XA)
521 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
522 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
523 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
tremfac96402013-09-21 18:13:35 +0200524#elif defined(CONFIG_VF610)
Peng Fan71204e92015-05-15 07:29:12 +0800525 { 0, I2C0_BASE_ADDR, I2C_QUIRK_FLAG },
York Sun2f78eae2014-06-23 15:15:54 -0700526#elif defined(CONFIG_FSL_LSCH3)
Peng Fan71204e92015-05-15 07:29:12 +0800527 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
528 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
529 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
530 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
Troy Kiskye4ff5252012-07-19 08:18:18 +0000531#else
tremfac96402013-09-21 18:13:35 +0200532#error "architecture not supported"
Troy Kiskye4ff5252012-07-19 08:18:18 +0000533#endif
Peng Fan71204e92015-05-15 07:29:12 +0800534 { }
tremfac96402013-09-21 18:13:35 +0200535};
536
Peng Fan71204e92015-05-15 07:29:12 +0800537struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
tremfac96402013-09-21 18:13:35 +0200538{
Peng Fan71204e92015-05-15 07:29:12 +0800539 return &mxc_i2c_buses[adap->hwadapnr];
Troy Kisky96c19bd2012-07-19 08:18:19 +0000540}
541
tremfac96402013-09-21 18:13:35 +0200542static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
543 uint addr, int alen, uint8_t *buffer,
544 int len)
Troy Kisky98153262012-07-19 08:18:20 +0000545{
tremfac96402013-09-21 18:13:35 +0200546 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
Troy Kisky98153262012-07-19 08:18:20 +0000547}
548
tremfac96402013-09-21 18:13:35 +0200549static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
550 uint addr, int alen, uint8_t *buffer,
551 int len)
Troy Kisky98153262012-07-19 08:18:20 +0000552{
tremfac96402013-09-21 18:13:35 +0200553 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000554}
555
Troy Kiskycfbb88d2012-07-19 08:18:08 +0000556/*
557 * Test if a chip at a given address responds (probe the chip)
558 */
tremfac96402013-09-21 18:13:35 +0200559static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
Troy Kiskycfbb88d2012-07-19 08:18:08 +0000560{
tremfac96402013-09-21 18:13:35 +0200561 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000562}
563
Peng Fan71204e92015-05-15 07:29:12 +0800564int __enable_i2c_clk(unsigned char enable, unsigned i2c_num)
Troy Kiskye4ff5252012-07-19 08:18:18 +0000565{
Peng Fan71204e92015-05-15 07:29:12 +0800566 return 1;
567}
568int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
569 __attribute__((weak, alias("__enable_i2c_clk")));
570
571void bus_i2c_init(int index, int speed, int unused,
572 int (*idle_bus_fn)(void *p), void *idle_bus_data)
573{
574 int ret;
575
576 if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
577 debug("Error i2c index\n");
Troy Kiskye4ff5252012-07-19 08:18:18 +0000578 return;
Troy Kiskye4ff5252012-07-19 08:18:18 +0000579 }
Peng Fan71204e92015-05-15 07:29:12 +0800580
581 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
582 mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
583
584 ret = enable_i2c_clk(1, index);
585 if (ret < 0) {
586 debug("I2C-%d clk fail to enable.\n", index);
587 return;
588 }
589
590 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000591}
592
593/*
594 * Init I2C Bus
595 */
tremfac96402013-09-21 18:13:35 +0200596static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
Troy Kiskye4ff5252012-07-19 08:18:18 +0000597{
Peng Fan71204e92015-05-15 07:29:12 +0800598 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000599}
600
601/*
602 * Set I2C Speed
603 */
Peng Fan71204e92015-05-15 07:29:12 +0800604static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
Troy Kiskye4ff5252012-07-19 08:18:18 +0000605{
tremfac96402013-09-21 18:13:35 +0200606 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000607}
608
609/*
tremfac96402013-09-21 18:13:35 +0200610 * Register mxc i2c adapters
Troy Kiskye4ff5252012-07-19 08:18:18 +0000611 */
tremfac96402013-09-21 18:13:35 +0200612U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
613 mxc_i2c_read, mxc_i2c_write,
614 mxc_i2c_set_bus_speed,
615 CONFIG_SYS_MXC_I2C1_SPEED,
616 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
617U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
618 mxc_i2c_read, mxc_i2c_write,
619 mxc_i2c_set_bus_speed,
620 CONFIG_SYS_MXC_I2C2_SPEED,
621 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
York Sunf8cb1012015-03-20 10:20:40 -0700622#ifdef CONFIG_SYS_I2C_MXC_I2C3
tremfac96402013-09-21 18:13:35 +0200623U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
624 mxc_i2c_read, mxc_i2c_write,
625 mxc_i2c_set_bus_speed,
626 CONFIG_SYS_MXC_I2C3_SPEED,
627 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
628#endif
Peng Fan71204e92015-05-15 07:29:12 +0800629
York Sunf8cb1012015-03-20 10:20:40 -0700630#ifdef CONFIG_SYS_I2C_MXC_I2C4
631U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
632 mxc_i2c_read, mxc_i2c_write,
633 mxc_i2c_set_bus_speed,
634 CONFIG_SYS_MXC_I2C4_SPEED,
635 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
636#endif
Peng Fan71204e92015-05-15 07:29:12 +0800637
638#else
639
640static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
641{
642 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
643
644 return bus_i2c_set_bus_speed(i2c_bus, speed);
645}
646
647static int mxc_i2c_probe(struct udevice *bus)
648{
649 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
650 fdt_addr_t addr;
651 int ret;
652
653 i2c_bus->driver_data = dev_get_driver_data(bus);
654
655 addr = dev_get_addr(bus);
656 if (addr == FDT_ADDR_T_NONE)
657 return -ENODEV;
658
659 i2c_bus->base = addr;
660 i2c_bus->index = bus->seq;
661
662 /* Enable clk */
663 ret = enable_i2c_clk(1, bus->seq);
664 if (ret < 0)
665 return ret;
666
667 ret = i2c_idle_bus(i2c_bus);
668 if (ret < 0) {
669 /* Disable clk */
670 enable_i2c_clk(0, bus->seq);
671 return ret;
672 }
673
674 /*
675 * Pinmux settings are in board file now, until pinmux is supported,
676 * we can set pinmux here in probe function.
677 */
678
679 debug("i2c : controller bus %d at %lu , speed %d: ",
680 bus->seq, i2c_bus->base,
681 i2c_bus->speed);
682
683 return 0;
684}
685
686static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
687 u32 chip_flags)
688{
689 int ret;
690 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
691
692 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
693 if (ret < 0) {
694 debug("%s failed, ret = %d\n", __func__, ret);
695 return ret;
696 }
697
698 i2c_imx_stop(i2c_bus);
699
700 return 0;
701}
702
703static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
704{
705 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
706 int ret = 0;
707 ulong base = i2c_bus->base;
708 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
709 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
710
711 /*
712 * Here the 3rd parameter addr and the 4th one alen are set to 0,
713 * because here we only want to send out chip address. The register
714 * address is wrapped in msg.
715 */
716 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, 0);
717 if (ret < 0) {
718 debug("i2c_init_transfer error: %d\n", ret);
719 return ret;
720 }
721
722 for (; nmsgs > 0; nmsgs--, msg++) {
723 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
724 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
725 if (msg->flags & I2C_M_RD)
726 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
727 msg->len);
728 else {
729 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
730 msg->len);
731 if (ret)
732 break;
733 if (next_is_read) {
734 /* Reuse ret */
735 ret = readb(base + (I2CR << reg_shift));
736 ret |= I2CR_RSTA;
737 writeb(ret, base + (I2CR << reg_shift));
738
739 ret = tx_byte(i2c_bus, (msg->addr << 1) | 1);
740 if (ret < 0) {
741 i2c_imx_stop(i2c_bus);
742 break;
743 }
744 }
745 }
746 }
747
748 if (ret)
749 debug("i2c_write: error sending\n");
750
751 i2c_imx_stop(i2c_bus);
752
753 return ret;
754}
755
756static const struct dm_i2c_ops mxc_i2c_ops = {
757 .xfer = mxc_i2c_xfer,
758 .probe_chip = mxc_i2c_probe_chip,
759 .set_bus_speed = mxc_i2c_set_bus_speed,
760};
761
762static const struct udevice_id mxc_i2c_ids[] = {
763 { .compatible = "fsl,imx21-i2c", },
764 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
765 {}
766};
767
768U_BOOT_DRIVER(i2c_mxc) = {
769 .name = "i2c_mxc",
770 .id = UCLASS_I2C,
771 .of_match = mxc_i2c_ids,
772 .probe = mxc_i2c_probe,
773 .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus),
774 .ops = &mxc_i2c_ops,
775};
776#endif