wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 2 | * (C) Copyright 2000-2007 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 25 | * CPU specific code |
| 26 | * |
| 27 | * written or collected and sometimes rewritten by |
| 28 | * Magnus Damm <damm@bitsmart.com> |
| 29 | * |
| 30 | * minor modifications by |
| 31 | * Wolfgang Denk <wd@denx.de> |
| 32 | */ |
| 33 | |
| 34 | #include <common.h> |
| 35 | #include <watchdog.h> |
| 36 | #include <command.h> |
| 37 | #include <asm/cache.h> |
Stefan Roese | b36df56 | 2010-09-09 19:18:00 +0200 | [diff] [blame] | 38 | #include <asm/ppc4xx.h> |
Ben Warren | 25a8590 | 2008-10-27 23:53:17 -0700 | [diff] [blame] | 39 | #include <netdev.h> |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 40 | |
Wolfgang Denk | d87080b | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 41 | DECLARE_GLOBAL_DATA_PTR; |
Wolfgang Denk | d87080b | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 42 | |
Stefan Roese | f344386 | 2006-10-07 11:30:52 +0200 | [diff] [blame] | 43 | void board_reset(void); |
Stefan Roese | f344386 | 2006-10-07 11:30:52 +0200 | [diff] [blame] | 44 | |
Adam Graham | c9c11d7 | 2008-10-08 10:13:19 -0700 | [diff] [blame] | 45 | /* |
| 46 | * To provide an interface to detect CPU number for boards that support |
| 47 | * more then one CPU, we implement the "weak" default functions here. |
| 48 | * |
| 49 | * Returns CPU number |
| 50 | */ |
| 51 | int __get_cpu_num(void) |
| 52 | { |
| 53 | return NA_OR_UNKNOWN_CPU; |
| 54 | } |
| 55 | int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num"))); |
| 56 | |
Stefan Roese | 20b3c4b | 2009-07-06 11:44:33 +0200 | [diff] [blame] | 57 | #if defined(CONFIG_PCI) |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 58 | #if defined(CONFIG_405GP) || \ |
| 59 | defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
| 60 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 61 | |
| 62 | #define PCI_ASYNC |
| 63 | |
Stefan Roese | c7f69c3 | 2007-11-09 12:18:54 +0100 | [diff] [blame] | 64 | static int pci_async_enabled(void) |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 65 | { |
| 66 | #if defined(CONFIG_405GP) |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 67 | return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN); |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 68 | #endif |
| 69 | |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 70 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
Stefan Roese | 2801b2d | 2008-03-11 15:05:50 +0100 | [diff] [blame] | 71 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
| 72 | defined(CONFIG_460EX) || defined(CONFIG_460GT) |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 73 | unsigned long val; |
| 74 | |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 75 | mfsdr(SDR0_SDSTP1, val); |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 76 | return (val & SDR0_SDSTP1_PAME_MASK); |
| 77 | #endif |
| 78 | } |
| 79 | #endif |
Stefan Roese | 20b3c4b | 2009-07-06 11:44:33 +0200 | [diff] [blame] | 80 | #endif /* CONFIG_PCI */ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 81 | |
Stefan Roese | 99bcad1 | 2012-09-19 14:33:52 +0200 | [diff] [blame] | 82 | #if defined(CONFIG_PCI) && \ |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 83 | !defined(CONFIG_405) && !defined(CONFIG_405EX) |
Stefan Roese | a760b02 | 2009-11-12 16:41:09 +0100 | [diff] [blame] | 84 | int pci_arbiter_enabled(void) |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 85 | { |
| 86 | #if defined(CONFIG_405GP) |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 87 | return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN); |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 88 | #endif |
| 89 | |
| 90 | #if defined(CONFIG_405EP) |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 91 | return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN); |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 92 | #endif |
| 93 | |
| 94 | #if defined(CONFIG_440GP) |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 95 | return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK); |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 96 | #endif |
| 97 | |
Stefan Roese | 7372ca6 | 2007-02-02 12:44:22 +0100 | [diff] [blame] | 98 | #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 99 | unsigned long val; |
| 100 | |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 101 | mfsdr(SDR0_XCR0, val); |
| 102 | return (val & SDR0_XCR0_PAE_MASK); |
Stefan Roese | 7372ca6 | 2007-02-02 12:44:22 +0100 | [diff] [blame] | 103 | #endif |
| 104 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
Stefan Roese | 2801b2d | 2008-03-11 15:05:50 +0100 | [diff] [blame] | 105 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
| 106 | defined(CONFIG_460EX) || defined(CONFIG_460GT) |
Stefan Roese | 7372ca6 | 2007-02-02 12:44:22 +0100 | [diff] [blame] | 107 | unsigned long val; |
| 108 | |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 109 | mfsdr(SDR0_PCI0, val); |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 110 | return (val & SDR0_PCI0_PAE_MASK); |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 111 | #endif |
| 112 | } |
| 113 | #endif |
| 114 | |
Stefan Roese | c7f69c3 | 2007-11-09 12:18:54 +0100 | [diff] [blame] | 115 | #if defined(CONFIG_405EP) |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 116 | #define I2C_BOOTROM |
| 117 | |
Stefan Roese | c7f69c3 | 2007-11-09 12:18:54 +0100 | [diff] [blame] | 118 | static int i2c_bootrom_enabled(void) |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 119 | { |
| 120 | #if defined(CONFIG_405EP) |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 121 | return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP); |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 122 | #else |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 123 | unsigned long val; |
| 124 | |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 125 | mfsdr(SDR0_SDCS0, val); |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 126 | return (val & SDR0_SDCS_SDD); |
| 127 | #endif |
| 128 | } |
Stefan Roese | 90e6f41 | 2007-04-18 12:05:59 +0200 | [diff] [blame] | 129 | #endif |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 130 | |
| 131 | #if defined(CONFIG_440GX) |
| 132 | #define SDR0_PINSTP_SHIFT 29 |
| 133 | static char *bootstrap_str[] = { |
| 134 | "EBC (16 bits)", |
| 135 | "EBC (8 bits)", |
| 136 | "EBC (32 bits)", |
| 137 | "EBC (8 bits)", |
| 138 | "PCI", |
| 139 | "I2C (Addr 0x54)", |
| 140 | "Reserved", |
| 141 | "I2C (Addr 0x50)", |
| 142 | }; |
BenoƮt Monin | e3cbe1f | 2007-06-04 08:36:05 +0200 | [diff] [blame] | 143 | static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' }; |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 144 | #endif |
| 145 | |
| 146 | #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) |
| 147 | #define SDR0_PINSTP_SHIFT 30 |
| 148 | static char *bootstrap_str[] = { |
| 149 | "EBC (8 bits)", |
| 150 | "PCI", |
| 151 | "I2C (Addr 0x54)", |
| 152 | "I2C (Addr 0x50)", |
| 153 | }; |
BenoƮt Monin | e3cbe1f | 2007-06-04 08:36:05 +0200 | [diff] [blame] | 154 | static char bootstrap_char[] = { 'A', 'B', 'C', 'D'}; |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 155 | #endif |
| 156 | |
| 157 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
| 158 | #define SDR0_PINSTP_SHIFT 29 |
| 159 | static char *bootstrap_str[] = { |
| 160 | "EBC (8 bits)", |
| 161 | "PCI", |
| 162 | "NAND (8 bits)", |
| 163 | "EBC (16 bits)", |
| 164 | "EBC (16 bits)", |
| 165 | "I2C (Addr 0x54)", |
| 166 | "PCI", |
| 167 | "I2C (Addr 0x52)", |
| 168 | }; |
BenoƮt Monin | e3cbe1f | 2007-06-04 08:36:05 +0200 | [diff] [blame] | 169 | static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 170 | #endif |
| 171 | |
| 172 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
| 173 | #define SDR0_PINSTP_SHIFT 29 |
| 174 | static char *bootstrap_str[] = { |
| 175 | "EBC (8 bits)", |
| 176 | "EBC (16 bits)", |
| 177 | "EBC (16 bits)", |
| 178 | "NAND (8 bits)", |
| 179 | "PCI", |
| 180 | "I2C (Addr 0x54)", |
| 181 | "PCI", |
| 182 | "I2C (Addr 0x52)", |
| 183 | }; |
BenoƮt Monin | e3cbe1f | 2007-06-04 08:36:05 +0200 | [diff] [blame] | 184 | static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 185 | #endif |
| 186 | |
Stefan Roese | 2801b2d | 2008-03-11 15:05:50 +0100 | [diff] [blame] | 187 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
| 188 | #define SDR0_PINSTP_SHIFT 29 |
| 189 | static char *bootstrap_str[] = { |
| 190 | "EBC (8 bits)", |
| 191 | "EBC (16 bits)", |
| 192 | "PCI", |
| 193 | "PCI", |
| 194 | "EBC (16 bits)", |
| 195 | "NAND (8 bits)", |
| 196 | "I2C (Addr 0x54)", /* A8 */ |
| 197 | "I2C (Addr 0x52)", /* A4 */ |
| 198 | }; |
Felix Radensky | d98964a | 2010-01-19 17:37:13 +0200 | [diff] [blame] | 199 | static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; |
Stefan Roese | 2801b2d | 2008-03-11 15:05:50 +0100 | [diff] [blame] | 200 | #endif |
| 201 | |
Feng Kan | 7d30793 | 2008-07-08 22:47:31 -0700 | [diff] [blame] | 202 | #if defined(CONFIG_460SX) |
| 203 | #define SDR0_PINSTP_SHIFT 29 |
| 204 | static char *bootstrap_str[] = { |
| 205 | "EBC (8 bits)", |
| 206 | "EBC (16 bits)", |
| 207 | "EBC (32 bits)", |
| 208 | "NAND (8 bits)", |
| 209 | "I2C (Addr 0x54)", /* A8 */ |
| 210 | "I2C (Addr 0x52)", /* A4 */ |
| 211 | }; |
| 212 | static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' }; |
| 213 | #endif |
| 214 | |
Stefan Roese | 90e6f41 | 2007-04-18 12:05:59 +0200 | [diff] [blame] | 215 | #if defined(CONFIG_405EZ) |
| 216 | #define SDR0_PINSTP_SHIFT 28 |
| 217 | static char *bootstrap_str[] = { |
| 218 | "EBC (8 bits)", |
| 219 | "SPI (fast)", |
| 220 | "NAND (512 page, 4 addr cycle)", |
| 221 | "I2C (Addr 0x50)", |
| 222 | "EBC (32 bits)", |
| 223 | "I2C (Addr 0x50)", |
| 224 | "NAND (2K page, 5 addr cycle)", |
| 225 | "I2C (Addr 0x50)", |
| 226 | "EBC (16 bits)", |
| 227 | "Reserved", |
| 228 | "NAND (2K page, 4 addr cycle)", |
| 229 | "I2C (Addr 0x50)", |
| 230 | "NAND (512 page, 3 addr cycle)", |
| 231 | "I2C (Addr 0x50)", |
| 232 | "SPI (slow)", |
| 233 | "I2C (Addr 0x50)", |
| 234 | }; |
BenoƮt Monin | e3cbe1f | 2007-06-04 08:36:05 +0200 | [diff] [blame] | 235 | static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \ |
| 236 | 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' }; |
Stefan Roese | 90e6f41 | 2007-04-18 12:05:59 +0200 | [diff] [blame] | 237 | #endif |
| 238 | |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 239 | #if defined(CONFIG_405EX) |
| 240 | #define SDR0_PINSTP_SHIFT 29 |
| 241 | static char *bootstrap_str[] = { |
| 242 | "EBC (8 bits)", |
| 243 | "EBC (16 bits)", |
| 244 | "EBC (16 bits)", |
| 245 | "NAND (8 bits)", |
| 246 | "NAND (8 bits)", |
| 247 | "I2C (Addr 0x54)", |
| 248 | "EBC (8 bits)", |
| 249 | "I2C (Addr 0x52)", |
| 250 | }; |
| 251 | static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; |
| 252 | #endif |
Tirumala Marri | 1b8fec1 | 2010-09-28 14:15:14 -0700 | [diff] [blame] | 253 | #if defined(CONFIG_APM821XX) |
| 254 | #define SDR0_PINSTP_SHIFT 29 |
| 255 | static char *bootstrap_str[] = { |
| 256 | "RESERVED", |
| 257 | "RESERVED", |
| 258 | "RESERVED", |
| 259 | "NAND (8 bits)", |
| 260 | "NOR (8 bits)", |
| 261 | "NOR (8 bits) w/PLL Bypassed", |
| 262 | "I2C (Addr 0x54)", |
| 263 | "I2C (Addr 0x52)", |
| 264 | }; |
| 265 | static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; |
| 266 | #endif |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 267 | |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 268 | #if defined(SDR0_PINSTP_SHIFT) |
| 269 | static int bootstrap_option(void) |
| 270 | { |
| 271 | unsigned long val; |
| 272 | |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 273 | mfsdr(SDR0_PINSTP, val); |
Stefan Roese | 90e6f41 | 2007-04-18 12:05:59 +0200 | [diff] [blame] | 274 | return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT); |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 275 | } |
| 276 | #endif /* SDR0_PINSTP_SHIFT */ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 277 | |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 278 | |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 279 | #if defined(CONFIG_440GP) |
Stefan Roese | c7f69c3 | 2007-11-09 12:18:54 +0100 | [diff] [blame] | 280 | static int do_chip_reset (unsigned long sys0, unsigned long sys1) |
| 281 | { |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 282 | /* Changes to CPC0_SYS0 and CPC0_SYS1 require chip |
Stefan Roese | c7f69c3 | 2007-11-09 12:18:54 +0100 | [diff] [blame] | 283 | * reset. |
| 284 | */ |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 285 | mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */ |
| 286 | mtdcr (CPC0_SYS0, sys0); |
| 287 | mtdcr (CPC0_SYS1, sys1); |
| 288 | mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */ |
Matthias Fuchs | 58ea142 | 2009-07-22 17:27:56 +0200 | [diff] [blame] | 289 | mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */ |
Stefan Roese | c7f69c3 | 2007-11-09 12:18:54 +0100 | [diff] [blame] | 290 | |
| 291 | return 1; |
| 292 | } |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 293 | #endif /* CONFIG_440GP */ |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 294 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 295 | |
| 296 | int checkcpu (void) |
| 297 | { |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 298 | #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */ |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 299 | uint pvr = get_pvr(); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 300 | ulong clock = gd->cpu_clk; |
| 301 | char buf[32]; |
Stefan Roese | 89bcc48 | 2009-07-29 08:45:27 +0200 | [diff] [blame] | 302 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
| 303 | u32 reg; |
| 304 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 305 | |
Wolfgang Denk | ba999c5 | 2006-10-20 17:54:33 +0200 | [diff] [blame] | 306 | char addstr[64] = ""; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 307 | sys_info_t sys_info; |
Adam Graham | c9c11d7 | 2008-10-08 10:13:19 -0700 | [diff] [blame] | 308 | int cpu_num; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 309 | |
Adam Graham | c9c11d7 | 2008-10-08 10:13:19 -0700 | [diff] [blame] | 310 | cpu_num = get_cpu_num(); |
| 311 | if (cpu_num >= 0) |
| 312 | printf("CPU%d: ", cpu_num); |
| 313 | else |
| 314 | puts("CPU: "); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 315 | |
| 316 | get_sys_info(&sys_info); |
| 317 | |
Ricardo Ribalda Delgado | d865fd0 | 2008-07-17 11:44:12 +0200 | [diff] [blame] | 318 | #if defined(CONFIG_XILINX_440) |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 319 | puts("IBM PowerPC "); |
Ricardo Ribalda Delgado | d865fd0 | 2008-07-17 11:44:12 +0200 | [diff] [blame] | 320 | #else |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 321 | puts("AMCC PowerPC "); |
Stefan Roese | 2801b2d | 2008-03-11 15:05:50 +0100 | [diff] [blame] | 322 | #endif |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 323 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 324 | switch (pvr) { |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 325 | |
| 326 | #if !defined(CONFIG_440) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 327 | case PVR_405GP_RB: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 328 | puts("405GP Rev. B"); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 329 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 330 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 331 | case PVR_405GP_RC: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 332 | puts("405GP Rev. C"); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 333 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 334 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 335 | case PVR_405GP_RD: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 336 | puts("405GP Rev. D"); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 337 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 338 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 339 | #ifdef CONFIG_405GP |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 340 | case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */ |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 341 | puts("405GP Rev. E"); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 342 | break; |
| 343 | #endif |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 344 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 345 | case PVR_405CR_RA: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 346 | puts("405CR Rev. A"); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 347 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 348 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 349 | case PVR_405CR_RB: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 350 | puts("405CR Rev. B"); |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 351 | break; |
| 352 | |
| 353 | #ifdef CONFIG_405CR |
| 354 | case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */ |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 355 | puts("405CR Rev. C"); |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 356 | break; |
| 357 | #endif |
| 358 | |
| 359 | case PVR_405GPR_RB: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 360 | puts("405GPr Rev. B"); |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 361 | break; |
| 362 | |
stroese | b867d70 | 2003-05-23 11:18:02 +0000 | [diff] [blame] | 363 | case PVR_405EP_RB: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 364 | puts("405EP Rev. B"); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 365 | break; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 366 | |
Stefan Roese | e01bd21 | 2007-03-21 13:38:59 +0100 | [diff] [blame] | 367 | case PVR_405EZ_RA: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 368 | puts("405EZ Rev. A"); |
Stefan Roese | e01bd21 | 2007-03-21 13:38:59 +0100 | [diff] [blame] | 369 | break; |
| 370 | |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 371 | case PVR_405EX1_RA: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 372 | puts("405EX Rev. A"); |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 373 | strcpy(addstr, "Security support"); |
| 374 | break; |
| 375 | |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 376 | case PVR_405EXR2_RA: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 377 | puts("405EXr Rev. A"); |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 378 | strcpy(addstr, "No Security support"); |
| 379 | break; |
| 380 | |
Stefan Roese | 70fab19 | 2008-05-13 20:22:01 +0200 | [diff] [blame] | 381 | case PVR_405EX1_RC: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 382 | puts("405EX Rev. C"); |
Stefan Roese | 70fab19 | 2008-05-13 20:22:01 +0200 | [diff] [blame] | 383 | strcpy(addstr, "Security support"); |
| 384 | break; |
| 385 | |
| 386 | case PVR_405EX2_RC: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 387 | puts("405EX Rev. C"); |
Stefan Roese | 70fab19 | 2008-05-13 20:22:01 +0200 | [diff] [blame] | 388 | strcpy(addstr, "No Security support"); |
| 389 | break; |
| 390 | |
| 391 | case PVR_405EXR1_RC: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 392 | puts("405EXr Rev. C"); |
Stefan Roese | 70fab19 | 2008-05-13 20:22:01 +0200 | [diff] [blame] | 393 | strcpy(addstr, "Security support"); |
| 394 | break; |
| 395 | |
| 396 | case PVR_405EXR2_RC: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 397 | puts("405EXr Rev. C"); |
Stefan Roese | 70fab19 | 2008-05-13 20:22:01 +0200 | [diff] [blame] | 398 | strcpy(addstr, "No Security support"); |
| 399 | break; |
| 400 | |
Stefan Roese | 56f1481 | 2009-10-06 07:21:08 +0200 | [diff] [blame] | 401 | case PVR_405EX1_RD: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 402 | puts("405EX Rev. D"); |
Stefan Roese | 56f1481 | 2009-10-06 07:21:08 +0200 | [diff] [blame] | 403 | strcpy(addstr, "Security support"); |
| 404 | break; |
| 405 | |
| 406 | case PVR_405EX2_RD: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 407 | puts("405EX Rev. D"); |
Stefan Roese | 56f1481 | 2009-10-06 07:21:08 +0200 | [diff] [blame] | 408 | strcpy(addstr, "No Security support"); |
| 409 | break; |
| 410 | |
| 411 | case PVR_405EXR1_RD: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 412 | puts("405EXr Rev. D"); |
Stefan Roese | 56f1481 | 2009-10-06 07:21:08 +0200 | [diff] [blame] | 413 | strcpy(addstr, "Security support"); |
| 414 | break; |
| 415 | |
| 416 | case PVR_405EXR2_RD: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 417 | puts("405EXr Rev. D"); |
Stefan Roese | 56f1481 | 2009-10-06 07:21:08 +0200 | [diff] [blame] | 418 | strcpy(addstr, "No Security support"); |
| 419 | break; |
| 420 | |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 421 | #else /* CONFIG_440 */ |
| 422 | |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 423 | #if defined(CONFIG_440GP) |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 424 | case PVR_440GP_RB: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 425 | puts("440GP Rev. B"); |
wdenk | 4d81677 | 2003-09-03 14:03:26 +0000 | [diff] [blame] | 426 | /* See errata 1.12: CHIP_4 */ |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 427 | if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) || |
| 428 | (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){ |
wdenk | 4d81677 | 2003-09-03 14:03:26 +0000 | [diff] [blame] | 429 | puts ( "\n\t CPC0_SYSx DCRs corrupted. " |
| 430 | "Resetting chip ...\n"); |
| 431 | udelay( 1000 * 1000 ); /* Give time for serial buf to clear */ |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 432 | do_chip_reset ( mfdcr(CPC0_STRP0), |
| 433 | mfdcr(CPC0_STRP1) ); |
wdenk | 4d81677 | 2003-09-03 14:03:26 +0000 | [diff] [blame] | 434 | } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 435 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 436 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 437 | case PVR_440GP_RC: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 438 | puts("440GP Rev. C"); |
wdenk | ba56f62 | 2004-02-06 23:19:44 +0000 | [diff] [blame] | 439 | break; |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 440 | #endif /* CONFIG_440GP */ |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 441 | |
wdenk | ba56f62 | 2004-02-06 23:19:44 +0000 | [diff] [blame] | 442 | case PVR_440GX_RA: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 443 | puts("440GX Rev. A"); |
wdenk | ba56f62 | 2004-02-06 23:19:44 +0000 | [diff] [blame] | 444 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 445 | |
wdenk | ba56f62 | 2004-02-06 23:19:44 +0000 | [diff] [blame] | 446 | case PVR_440GX_RB: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 447 | puts("440GX Rev. B"); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 448 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 449 | |
stroese | 0a7c539 | 2005-04-07 05:33:41 +0000 | [diff] [blame] | 450 | case PVR_440GX_RC: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 451 | puts("440GX Rev. C"); |
stroese | 0a7c539 | 2005-04-07 05:33:41 +0000 | [diff] [blame] | 452 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 453 | |
Stefan Roese | 57275b6 | 2005-11-01 10:08:03 +0100 | [diff] [blame] | 454 | case PVR_440GX_RF: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 455 | puts("440GX Rev. F"); |
Stefan Roese | 57275b6 | 2005-11-01 10:08:03 +0100 | [diff] [blame] | 456 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 457 | |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 458 | case PVR_440EP_RA: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 459 | puts("440EP Rev. A"); |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 460 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 461 | |
Stefan Roese | 9a8d82f | 2005-10-04 15:00:30 +0200 | [diff] [blame] | 462 | #ifdef CONFIG_440EP |
| 463 | case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */ |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 464 | puts("440EP Rev. B"); |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 465 | break; |
Stefan Roese | 512f8d5 | 2006-05-10 14:10:41 +0200 | [diff] [blame] | 466 | |
| 467 | case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */ |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 468 | puts("440EP Rev. C"); |
Stefan Roese | 512f8d5 | 2006-05-10 14:10:41 +0200 | [diff] [blame] | 469 | break; |
Stefan Roese | 9a8d82f | 2005-10-04 15:00:30 +0200 | [diff] [blame] | 470 | #endif /* CONFIG_440EP */ |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 471 | |
Stefan Roese | 9a8d82f | 2005-10-04 15:00:30 +0200 | [diff] [blame] | 472 | #ifdef CONFIG_440GR |
| 473 | case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */ |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 474 | puts("440GR Rev. A"); |
Stefan Roese | 9a8d82f | 2005-10-04 15:00:30 +0200 | [diff] [blame] | 475 | break; |
Stefan Roese | 512f8d5 | 2006-05-10 14:10:41 +0200 | [diff] [blame] | 476 | |
Stefan Roese | 5770a1e | 2006-05-18 19:21:53 +0200 | [diff] [blame] | 477 | case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */ |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 478 | puts("440GR Rev. B"); |
Stefan Roese | 512f8d5 | 2006-05-10 14:10:41 +0200 | [diff] [blame] | 479 | break; |
Stefan Roese | 9a8d82f | 2005-10-04 15:00:30 +0200 | [diff] [blame] | 480 | #endif /* CONFIG_440GR */ |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 481 | |
Stefan Roese | 2902fad | 2007-01-31 16:56:10 +0100 | [diff] [blame] | 482 | #ifdef CONFIG_440EPX |
| 483 | case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 484 | puts("440EPx Rev. A"); |
Stefan Roese | edf0b54 | 2006-10-18 15:59:35 +0200 | [diff] [blame] | 485 | strcpy(addstr, "Security/Kasumi support"); |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 486 | break; |
| 487 | |
Stefan Roese | 2902fad | 2007-01-31 16:56:10 +0100 | [diff] [blame] | 488 | case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 489 | puts("440EPx Rev. A"); |
Stefan Roese | edf0b54 | 2006-10-18 15:59:35 +0200 | [diff] [blame] | 490 | strcpy(addstr, "No Security/Kasumi support"); |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 491 | break; |
Stefan Roese | 2902fad | 2007-01-31 16:56:10 +0100 | [diff] [blame] | 492 | #endif /* CONFIG_440EPX */ |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 493 | |
Stefan Roese | 2902fad | 2007-01-31 16:56:10 +0100 | [diff] [blame] | 494 | #ifdef CONFIG_440GRX |
| 495 | case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 496 | puts("440GRx Rev. A"); |
Stefan Roese | edf0b54 | 2006-10-18 15:59:35 +0200 | [diff] [blame] | 497 | strcpy(addstr, "Security/Kasumi support"); |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 498 | break; |
| 499 | |
Stefan Roese | 2902fad | 2007-01-31 16:56:10 +0100 | [diff] [blame] | 500 | case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 501 | puts("440GRx Rev. A"); |
Stefan Roese | edf0b54 | 2006-10-18 15:59:35 +0200 | [diff] [blame] | 502 | strcpy(addstr, "No Security/Kasumi support"); |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 503 | break; |
Stefan Roese | 2902fad | 2007-01-31 16:56:10 +0100 | [diff] [blame] | 504 | #endif /* CONFIG_440GRX */ |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 505 | |
Stefan Roese | 9598177 | 2007-01-13 08:01:03 +0100 | [diff] [blame] | 506 | case PVR_440SP_6_RAB: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 507 | puts("440SP Rev. A/B"); |
Stefan Roese | 9598177 | 2007-01-13 08:01:03 +0100 | [diff] [blame] | 508 | strcpy(addstr, "RAID 6 support"); |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 509 | break; |
| 510 | |
Stefan Roese | 9598177 | 2007-01-13 08:01:03 +0100 | [diff] [blame] | 511 | case PVR_440SP_RAB: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 512 | puts("440SP Rev. A/B"); |
Stefan Roese | 9598177 | 2007-01-13 08:01:03 +0100 | [diff] [blame] | 513 | strcpy(addstr, "No RAID 6 support"); |
| 514 | break; |
| 515 | |
| 516 | case PVR_440SP_6_RC: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 517 | puts("440SP Rev. C"); |
Stefan Roese | 9598177 | 2007-01-13 08:01:03 +0100 | [diff] [blame] | 518 | strcpy(addstr, "RAID 6 support"); |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 519 | break; |
| 520 | |
Stefan Roese | e732fae | 2006-11-28 16:09:24 +0100 | [diff] [blame] | 521 | case PVR_440SP_RC: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 522 | puts("440SP Rev. C"); |
Stefan Roese | 9598177 | 2007-01-13 08:01:03 +0100 | [diff] [blame] | 523 | strcpy(addstr, "No RAID 6 support"); |
| 524 | break; |
| 525 | |
| 526 | case PVR_440SPe_6_RA: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 527 | puts("440SPe Rev. A"); |
Stefan Roese | 9598177 | 2007-01-13 08:01:03 +0100 | [diff] [blame] | 528 | strcpy(addstr, "RAID 6 support"); |
Stefan Roese | e732fae | 2006-11-28 16:09:24 +0100 | [diff] [blame] | 529 | break; |
| 530 | |
Marian Balakowicz | 6c5879f | 2006-06-30 16:30:46 +0200 | [diff] [blame] | 531 | case PVR_440SPe_RA: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 532 | puts("440SPe Rev. A"); |
Stefan Roese | 9598177 | 2007-01-13 08:01:03 +0100 | [diff] [blame] | 533 | strcpy(addstr, "No RAID 6 support"); |
| 534 | break; |
| 535 | |
| 536 | case PVR_440SPe_6_RB: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 537 | puts("440SPe Rev. B"); |
Stefan Roese | 9598177 | 2007-01-13 08:01:03 +0100 | [diff] [blame] | 538 | strcpy(addstr, "RAID 6 support"); |
Marian Balakowicz | 6c5879f | 2006-06-30 16:30:46 +0200 | [diff] [blame] | 539 | break; |
Marian Balakowicz | fe84b48 | 2006-07-03 23:42:36 +0200 | [diff] [blame] | 540 | |
Marian Balakowicz | 6c5879f | 2006-06-30 16:30:46 +0200 | [diff] [blame] | 541 | case PVR_440SPe_RB: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 542 | puts("440SPe Rev. B"); |
Stefan Roese | 9598177 | 2007-01-13 08:01:03 +0100 | [diff] [blame] | 543 | strcpy(addstr, "No RAID 6 support"); |
Marian Balakowicz | 6c5879f | 2006-06-30 16:30:46 +0200 | [diff] [blame] | 544 | break; |
Marian Balakowicz | fe84b48 | 2006-07-03 23:42:36 +0200 | [diff] [blame] | 545 | |
Stefan Roese | 89bcc48 | 2009-07-29 08:45:27 +0200 | [diff] [blame] | 546 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
Stefan Roese | 2801b2d | 2008-03-11 15:05:50 +0100 | [diff] [blame] | 547 | case PVR_460EX_RA: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 548 | puts("460EX Rev. A"); |
Stefan Roese | 2801b2d | 2008-03-11 15:05:50 +0100 | [diff] [blame] | 549 | strcpy(addstr, "No Security/Kasumi support"); |
| 550 | break; |
| 551 | |
| 552 | case PVR_460EX_SE_RA: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 553 | puts("460EX Rev. A"); |
Stefan Roese | 2801b2d | 2008-03-11 15:05:50 +0100 | [diff] [blame] | 554 | strcpy(addstr, "Security/Kasumi support"); |
| 555 | break; |
| 556 | |
Stefan Roese | 89bcc48 | 2009-07-29 08:45:27 +0200 | [diff] [blame] | 557 | case PVR_460EX_RB: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 558 | puts("460EX Rev. B"); |
Stefan Roese | 89bcc48 | 2009-07-29 08:45:27 +0200 | [diff] [blame] | 559 | mfsdr(SDR0_ECID3, reg); |
| 560 | if (reg & 0x00100000) |
| 561 | strcpy(addstr, "No Security/Kasumi support"); |
| 562 | else |
| 563 | strcpy(addstr, "Security/Kasumi support"); |
| 564 | break; |
| 565 | |
Stefan Roese | 2801b2d | 2008-03-11 15:05:50 +0100 | [diff] [blame] | 566 | case PVR_460GT_RA: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 567 | puts("460GT Rev. A"); |
Stefan Roese | 2801b2d | 2008-03-11 15:05:50 +0100 | [diff] [blame] | 568 | strcpy(addstr, "No Security/Kasumi support"); |
| 569 | break; |
| 570 | |
| 571 | case PVR_460GT_SE_RA: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 572 | puts("460GT Rev. A"); |
Stefan Roese | 2801b2d | 2008-03-11 15:05:50 +0100 | [diff] [blame] | 573 | strcpy(addstr, "Security/Kasumi support"); |
| 574 | break; |
| 575 | |
Stefan Roese | 89bcc48 | 2009-07-29 08:45:27 +0200 | [diff] [blame] | 576 | case PVR_460GT_RB: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 577 | puts("460GT Rev. B"); |
Stefan Roese | 89bcc48 | 2009-07-29 08:45:27 +0200 | [diff] [blame] | 578 | mfsdr(SDR0_ECID3, reg); |
| 579 | if (reg & 0x00100000) |
| 580 | strcpy(addstr, "No Security/Kasumi support"); |
| 581 | else |
| 582 | strcpy(addstr, "Security/Kasumi support"); |
| 583 | break; |
| 584 | #endif |
| 585 | |
Feng Kan | 7d30793 | 2008-07-08 22:47:31 -0700 | [diff] [blame] | 586 | case PVR_460SX_RA: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 587 | puts("460SX Rev. A"); |
Feng Kan | 7d30793 | 2008-07-08 22:47:31 -0700 | [diff] [blame] | 588 | strcpy(addstr, "Security support"); |
| 589 | break; |
| 590 | |
| 591 | case PVR_460SX_RA_V1: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 592 | puts("460SX Rev. A"); |
Feng Kan | 7d30793 | 2008-07-08 22:47:31 -0700 | [diff] [blame] | 593 | strcpy(addstr, "No Security support"); |
| 594 | break; |
| 595 | |
| 596 | case PVR_460GX_RA: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 597 | puts("460GX Rev. A"); |
Feng Kan | 7d30793 | 2008-07-08 22:47:31 -0700 | [diff] [blame] | 598 | strcpy(addstr, "Security support"); |
| 599 | break; |
| 600 | |
| 601 | case PVR_460GX_RA_V1: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 602 | puts("460GX Rev. A"); |
Feng Kan | 7d30793 | 2008-07-08 22:47:31 -0700 | [diff] [blame] | 603 | strcpy(addstr, "No Security support"); |
| 604 | break; |
| 605 | |
Tirumala Marri | 1b8fec1 | 2010-09-28 14:15:14 -0700 | [diff] [blame] | 606 | case PVR_APM821XX_RA: |
| 607 | puts("APM821XX Rev. A"); |
| 608 | strcpy(addstr, "Security support"); |
| 609 | break; |
| 610 | |
Ricardo Ribalda Delgado | d865fd0 | 2008-07-17 11:44:12 +0200 | [diff] [blame] | 611 | case PVR_VIRTEX5: |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 612 | puts("440x5 VIRTEX5"); |
Ricardo Ribalda Delgado | d865fd0 | 2008-07-17 11:44:12 +0200 | [diff] [blame] | 613 | break; |
Stefan Roese | e02d449 | 2010-09-03 13:27:02 +0200 | [diff] [blame] | 614 | #endif /* CONFIG_440 */ |
Ricardo Ribalda Delgado | d865fd0 | 2008-07-17 11:44:12 +0200 | [diff] [blame] | 615 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 616 | default: |
Stefan Roese | 17f50f22 | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 617 | printf (" UNKNOWN (PVR=%08x)", pvr); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 618 | break; |
| 619 | } |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 620 | |
Stefan Roese | 08c6a26 | 2009-10-19 14:44:11 +0200 | [diff] [blame] | 621 | printf (" at %s MHz (PLB=%lu OPB=%lu EBC=%lu", |
| 622 | strmhz(buf, clock), |
Stefan Roese | e01bd21 | 2007-03-21 13:38:59 +0100 | [diff] [blame] | 623 | sys_info.freqPLB / 1000000, |
| 624 | get_OPB_freq() / 1000000, |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 625 | sys_info.freqEBC / 1000000); |
Stefan Roese | 08c6a26 | 2009-10-19 14:44:11 +0200 | [diff] [blame] | 626 | #if defined(CONFIG_PCI) && \ |
| 627 | (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ |
| 628 | defined(CONFIG_440GR) || defined(CONFIG_440GRX)) |
| 629 | printf(" PCI=%lu MHz", sys_info.freqPCI / 1000000); |
| 630 | #endif |
| 631 | printf(")\n"); |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 632 | |
Stefan Roese | edf0b54 | 2006-10-18 15:59:35 +0200 | [diff] [blame] | 633 | if (addstr[0] != 0) |
| 634 | printf(" %s\n", addstr); |
| 635 | |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 636 | #if defined(I2C_BOOTROM) |
| 637 | printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis"); |
Stefan Roese | 90e6f41 | 2007-04-18 12:05:59 +0200 | [diff] [blame] | 638 | #endif /* I2C_BOOTROM */ |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 639 | #if defined(SDR0_PINSTP_SHIFT) |
BenoƮt Monin | e3cbe1f | 2007-06-04 08:36:05 +0200 | [diff] [blame] | 640 | printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]); |
Stefan Roese | cf94098 | 2009-04-15 10:50:48 +0200 | [diff] [blame] | 641 | printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]); |
| 642 | #ifdef CONFIG_NAND_U_BOOT |
| 643 | puts(", booting from NAND"); |
| 644 | #endif /* CONFIG_NAND_U_BOOT */ |
| 645 | putc('\n'); |
Wolfgang Denk | ba999c5 | 2006-10-20 17:54:33 +0200 | [diff] [blame] | 646 | #endif /* SDR0_PINSTP_SHIFT */ |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 647 | |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 648 | #if defined(CONFIG_PCI) && !defined(CONFIG_405EX) |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 649 | printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis"); |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 650 | #endif |
| 651 | |
Stefan Roese | 1bbae2b | 2009-05-27 10:34:32 +0200 | [diff] [blame] | 652 | #if defined(CONFIG_PCI) && defined(PCI_ASYNC) |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 653 | if (pci_async_enabled()) { |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 654 | printf (", PCI async ext clock used"); |
| 655 | } else { |
| 656 | printf (", PCI sync clock at %lu MHz", |
| 657 | sys_info.freqPLB / sys_info.pllPciDiv / 1000000); |
| 658 | } |
| 659 | #endif |
| 660 | |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 661 | #if defined(CONFIG_PCI) && !defined(CONFIG_405EX) |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 662 | putc('\n'); |
| 663 | #endif |
| 664 | |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 665 | #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 666 | printf (" 16 kB I-Cache 16 kB D-Cache"); |
| 667 | #elif defined(CONFIG_440) |
| 668 | printf (" 32 kB I-Cache 32 kB D-Cache"); |
| 669 | #else |
| 670 | printf (" 16 kB I-Cache %d kB D-Cache", |
| 671 | ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8); |
| 672 | #endif |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 673 | |
| 674 | #endif /* !defined(CONFIG_405) */ |
| 675 | |
| 676 | putc ('\n'); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 677 | |
| 678 | return 0; |
| 679 | } |
| 680 | |
Rafal Jaworowski | 692519b | 2006-08-10 12:43:17 +0200 | [diff] [blame] | 681 | int ppc440spe_revB() { |
| 682 | unsigned int pvr; |
| 683 | |
| 684 | pvr = get_pvr(); |
Stefan Roese | 5a5c569 | 2007-01-15 09:46:29 +0100 | [diff] [blame] | 685 | if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB)) |
Rafal Jaworowski | 692519b | 2006-08-10 12:43:17 +0200 | [diff] [blame] | 686 | return 1; |
| 687 | else |
| 688 | return 0; |
| 689 | } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 690 | |
| 691 | /* ------------------------------------------------------------------------- */ |
| 692 | |
Wolfgang Denk | 54841ab | 2010-06-28 22:00:46 +0200 | [diff] [blame] | 693 | int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 694 | { |
Stefan Roese | 1f94d16 | 2006-11-27 14:48:41 +0100 | [diff] [blame] | 695 | #if defined(CONFIG_BOARD_RESET) |
| 696 | board_reset(); |
Stefan Roese | 1729b92 | 2006-11-27 14:52:04 +0100 | [diff] [blame] | 697 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 698 | #if defined(CONFIG_SYS_4xx_RESET_TYPE) |
Matthias Fuchs | 58ea142 | 2009-07-22 17:27:56 +0200 | [diff] [blame] | 699 | mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28); |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 700 | #else |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 701 | /* |
| 702 | * Initiate system reset in debug control register DBCR |
| 703 | */ |
Matthias Fuchs | 58ea142 | 2009-07-22 17:27:56 +0200 | [diff] [blame] | 704 | mtspr(SPRN_DBCR0, 0x30000000); |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 705 | #endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */ |
Stefan Roese | f344386 | 2006-10-07 11:30:52 +0200 | [diff] [blame] | 706 | #endif /* defined(CONFIG_BOARD_RESET) */ |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 707 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 708 | return 1; |
| 709 | } |
| 710 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 711 | |
| 712 | /* |
| 713 | * Get timebase clock frequency |
| 714 | */ |
| 715 | unsigned long get_tbclk (void) |
| 716 | { |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 717 | sys_info_t sys_info; |
| 718 | |
| 719 | get_sys_info(&sys_info); |
| 720 | return (sys_info.freqProcessor); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 721 | } |
| 722 | |
| 723 | |
| 724 | #if defined(CONFIG_WATCHDOG) |
Stefan Roese | c7f69c3 | 2007-11-09 12:18:54 +0100 | [diff] [blame] | 725 | void watchdog_reset(void) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 726 | { |
| 727 | int re_enable = disable_interrupts(); |
| 728 | reset_4xx_watchdog(); |
| 729 | if (re_enable) enable_interrupts(); |
| 730 | } |
| 731 | |
Stefan Roese | c7f69c3 | 2007-11-09 12:18:54 +0100 | [diff] [blame] | 732 | void reset_4xx_watchdog(void) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 733 | { |
| 734 | /* |
| 735 | * Clear TSR(WIS) bit |
| 736 | */ |
Matthias Fuchs | 58ea142 | 2009-07-22 17:27:56 +0200 | [diff] [blame] | 737 | mtspr(SPRN_TSR, 0x40000000); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 738 | } |
| 739 | #endif /* CONFIG_WATCHDOG */ |
Ben Warren | 25a8590 | 2008-10-27 23:53:17 -0700 | [diff] [blame] | 740 | |
| 741 | /* |
| 742 | * Initializes on-chip ethernet controllers. |
| 743 | * to override, implement board_eth_init() |
| 744 | */ |
| 745 | int cpu_eth_init(bd_t *bis) |
| 746 | { |
| 747 | #if defined(CONFIG_PPC4xx_EMAC) |
| 748 | ppc_4xx_eth_initialize(bis); |
| 749 | #endif |
| 750 | return 0; |
| 751 | } |