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wdenkc6097192002-11-03 00:24:07 +00001/*
Stefan Roesedbbd1252007-10-05 17:10:59 +02002 * (C) Copyright 2000-2007
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
wdenkc6097192002-11-03 00:24:07 +000025 * CPU specific code
26 *
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
29 *
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
32 */
33
34#include <common.h>
35#include <watchdog.h>
36#include <command.h>
37#include <asm/cache.h>
38#include <ppc4xx.h>
Ben Warren25a85902008-10-27 23:53:17 -070039#include <netdev.h>
wdenkc6097192002-11-03 00:24:07 +000040
Wolfgang Denkd87080b2006-03-31 18:32:53 +020041DECLARE_GLOBAL_DATA_PTR;
Wolfgang Denkd87080b2006-03-31 18:32:53 +020042
Stefan Roesef3443862006-10-07 11:30:52 +020043void board_reset(void);
Stefan Roesef3443862006-10-07 11:30:52 +020044
Adam Grahamc9c11d72008-10-08 10:13:19 -070045/*
46 * To provide an interface to detect CPU number for boards that support
47 * more then one CPU, we implement the "weak" default functions here.
48 *
49 * Returns CPU number
50 */
51int __get_cpu_num(void)
52{
53 return NA_OR_UNKNOWN_CPU;
54}
55int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
56
Stefan Roese20b3c4b2009-07-06 11:44:33 +020057#if defined(CONFIG_PCI)
Stefan Roese887e2ec2006-09-07 11:51:23 +020058#if defined(CONFIG_405GP) || \
59 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
60 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010061
62#define PCI_ASYNC
63
Stefan Roesec7f69c32007-11-09 12:18:54 +010064static int pci_async_enabled(void)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010065{
66#if defined(CONFIG_405GP)
67 return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
68#endif
69
Stefan Roese887e2ec2006-09-07 11:51:23 +020070#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
Stefan Roese2801b2d2008-03-11 15:05:50 +010071 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
72 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010073 unsigned long val;
74
Wolfgang Denk74812662005-12-12 16:06:05 +010075 mfsdr(sdr_sdstp1, val);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010076 return (val & SDR0_SDSTP1_PAME_MASK);
77#endif
78}
79#endif
Stefan Roese20b3c4b2009-07-06 11:44:33 +020080#endif /* CONFIG_PCI */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010081
Stefan Roesedbbd1252007-10-05 17:10:59 +020082#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
83 !defined(CONFIG_405) && !defined(CONFIG_405EX)
Stefan Roesec7f69c32007-11-09 12:18:54 +010084static int pci_arbiter_enabled(void)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010085{
86#if defined(CONFIG_405GP)
87 return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
88#endif
89
90#if defined(CONFIG_405EP)
91 return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
92#endif
93
94#if defined(CONFIG_440GP)
95 return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
96#endif
97
Stefan Roese7372ca62007-02-02 12:44:22 +010098#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010099 unsigned long val;
100
Stefan Roese7372ca62007-02-02 12:44:22 +0100101 mfsdr(sdr_xcr, val);
102 return (val & 0x80000000);
103#endif
104#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
Stefan Roese2801b2d2008-03-11 15:05:50 +0100105 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
106 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Stefan Roese7372ca62007-02-02 12:44:22 +0100107 unsigned long val;
108
109 mfsdr(sdr_pci0, val);
110 return (val & 0x80000000);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100111#endif
112}
113#endif
114
Stefan Roesec7f69c32007-11-09 12:18:54 +0100115#if defined(CONFIG_405EP)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100116#define I2C_BOOTROM
117
Stefan Roesec7f69c32007-11-09 12:18:54 +0100118static int i2c_bootrom_enabled(void)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100119{
120#if defined(CONFIG_405EP)
121 return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200122#else
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100123 unsigned long val;
124
125 mfsdr(sdr_sdcs, val);
126 return (val & SDR0_SDCS_SDD);
127#endif
128}
Stefan Roese90e6f412007-04-18 12:05:59 +0200129#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200130
131#if defined(CONFIG_440GX)
132#define SDR0_PINSTP_SHIFT 29
133static char *bootstrap_str[] = {
134 "EBC (16 bits)",
135 "EBC (8 bits)",
136 "EBC (32 bits)",
137 "EBC (8 bits)",
138 "PCI",
139 "I2C (Addr 0x54)",
140 "Reserved",
141 "I2C (Addr 0x50)",
142};
BenoƮt Monine3cbe1f2007-06-04 08:36:05 +0200143static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
Stefan Roese887e2ec2006-09-07 11:51:23 +0200144#endif
145
146#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
147#define SDR0_PINSTP_SHIFT 30
148static char *bootstrap_str[] = {
149 "EBC (8 bits)",
150 "PCI",
151 "I2C (Addr 0x54)",
152 "I2C (Addr 0x50)",
153};
BenoƮt Monine3cbe1f2007-06-04 08:36:05 +0200154static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
Stefan Roese887e2ec2006-09-07 11:51:23 +0200155#endif
156
157#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
158#define SDR0_PINSTP_SHIFT 29
159static char *bootstrap_str[] = {
160 "EBC (8 bits)",
161 "PCI",
162 "NAND (8 bits)",
163 "EBC (16 bits)",
164 "EBC (16 bits)",
165 "I2C (Addr 0x54)",
166 "PCI",
167 "I2C (Addr 0x52)",
168};
BenoƮt Monine3cbe1f2007-06-04 08:36:05 +0200169static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
Stefan Roese887e2ec2006-09-07 11:51:23 +0200170#endif
171
172#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
173#define SDR0_PINSTP_SHIFT 29
174static char *bootstrap_str[] = {
175 "EBC (8 bits)",
176 "EBC (16 bits)",
177 "EBC (16 bits)",
178 "NAND (8 bits)",
179 "PCI",
180 "I2C (Addr 0x54)",
181 "PCI",
182 "I2C (Addr 0x52)",
183};
BenoƮt Monine3cbe1f2007-06-04 08:36:05 +0200184static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
Stefan Roese887e2ec2006-09-07 11:51:23 +0200185#endif
186
Stefan Roese2801b2d2008-03-11 15:05:50 +0100187#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
188#define SDR0_PINSTP_SHIFT 29
189static char *bootstrap_str[] = {
190 "EBC (8 bits)",
191 "EBC (16 bits)",
192 "PCI",
193 "PCI",
194 "EBC (16 bits)",
195 "NAND (8 bits)",
196 "I2C (Addr 0x54)", /* A8 */
197 "I2C (Addr 0x52)", /* A4 */
198};
199static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
200#endif
201
Feng Kan7d307932008-07-08 22:47:31 -0700202#if defined(CONFIG_460SX)
203#define SDR0_PINSTP_SHIFT 29
204static char *bootstrap_str[] = {
205 "EBC (8 bits)",
206 "EBC (16 bits)",
207 "EBC (32 bits)",
208 "NAND (8 bits)",
209 "I2C (Addr 0x54)", /* A8 */
210 "I2C (Addr 0x52)", /* A4 */
211};
212static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
213#endif
214
Stefan Roese90e6f412007-04-18 12:05:59 +0200215#if defined(CONFIG_405EZ)
216#define SDR0_PINSTP_SHIFT 28
217static char *bootstrap_str[] = {
218 "EBC (8 bits)",
219 "SPI (fast)",
220 "NAND (512 page, 4 addr cycle)",
221 "I2C (Addr 0x50)",
222 "EBC (32 bits)",
223 "I2C (Addr 0x50)",
224 "NAND (2K page, 5 addr cycle)",
225 "I2C (Addr 0x50)",
226 "EBC (16 bits)",
227 "Reserved",
228 "NAND (2K page, 4 addr cycle)",
229 "I2C (Addr 0x50)",
230 "NAND (512 page, 3 addr cycle)",
231 "I2C (Addr 0x50)",
232 "SPI (slow)",
233 "I2C (Addr 0x50)",
234};
BenoƮt Monine3cbe1f2007-06-04 08:36:05 +0200235static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
236 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
Stefan Roese90e6f412007-04-18 12:05:59 +0200237#endif
238
Stefan Roesedbbd1252007-10-05 17:10:59 +0200239#if defined(CONFIG_405EX)
240#define SDR0_PINSTP_SHIFT 29
241static char *bootstrap_str[] = {
242 "EBC (8 bits)",
243 "EBC (16 bits)",
244 "EBC (16 bits)",
245 "NAND (8 bits)",
246 "NAND (8 bits)",
247 "I2C (Addr 0x54)",
248 "EBC (8 bits)",
249 "I2C (Addr 0x52)",
250};
251static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
252#endif
253
Stefan Roese887e2ec2006-09-07 11:51:23 +0200254#if defined(SDR0_PINSTP_SHIFT)
255static int bootstrap_option(void)
256{
257 unsigned long val;
258
Stefan Roese90e6f412007-04-18 12:05:59 +0200259 mfsdr(SDR_PINSTP, val);
260 return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200261}
262#endif /* SDR0_PINSTP_SHIFT */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100263
Stefan Roese3d9569b2005-11-27 19:36:26 +0100264
265#if defined(CONFIG_440)
Stefan Roesec7f69c32007-11-09 12:18:54 +0100266static int do_chip_reset (unsigned long sys0, unsigned long sys1)
267{
268 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
269 * reset.
270 */
271 mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
272 mtdcr (cpc0_sys0, sys0);
273 mtdcr (cpc0_sys1, sys1);
274 mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200275 mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */
Stefan Roesec7f69c32007-11-09 12:18:54 +0100276
277 return 1;
278}
Stefan Roese3d9569b2005-11-27 19:36:26 +0100279#endif
280
wdenkc6097192002-11-03 00:24:07 +0000281
282int checkcpu (void)
283{
Stefan Roese3d9569b2005-11-27 19:36:26 +0100284#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
Stefan Roese3d9569b2005-11-27 19:36:26 +0100285 uint pvr = get_pvr();
wdenkc6097192002-11-03 00:24:07 +0000286 ulong clock = gd->cpu_clk;
287 char buf[32];
Stefan Roese89bcc482009-07-29 08:45:27 +0200288#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
289 u32 reg;
290#endif
wdenkc6097192002-11-03 00:24:07 +0000291
Stefan Roese3d9569b2005-11-27 19:36:26 +0100292#if !defined(CONFIG_IOP480)
Wolfgang Denkba999c52006-10-20 17:54:33 +0200293 char addstr[64] = "";
Stefan Roese3d9569b2005-11-27 19:36:26 +0100294 sys_info_t sys_info;
Adam Grahamc9c11d72008-10-08 10:13:19 -0700295 int cpu_num;
wdenkc6097192002-11-03 00:24:07 +0000296
Adam Grahamc9c11d72008-10-08 10:13:19 -0700297 cpu_num = get_cpu_num();
298 if (cpu_num >= 0)
299 printf("CPU%d: ", cpu_num);
300 else
301 puts("CPU: ");
wdenkc6097192002-11-03 00:24:07 +0000302
303 get_sys_info(&sys_info);
304
Ricardo Ribalda Delgadod865fd02008-07-17 11:44:12 +0200305#if defined(CONFIG_XILINX_440)
306 puts("IBM PowerPC 4");
307#else
Stefan Roese3d9569b2005-11-27 19:36:26 +0100308 puts("AMCC PowerPC 4");
Ricardo Ribalda Delgadod865fd02008-07-17 11:44:12 +0200309#endif
Stefan Roese3d9569b2005-11-27 19:36:26 +0100310
Stefan Roesee01bd212007-03-21 13:38:59 +0100311#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200312 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
313 defined(CONFIG_405EX)
Stefan Roese3d9569b2005-11-27 19:36:26 +0100314 puts("05");
wdenkc6097192002-11-03 00:24:07 +0000315#endif
Stefan Roese3d9569b2005-11-27 19:36:26 +0100316#if defined(CONFIG_440)
Stefan Roese2801b2d2008-03-11 15:05:50 +0100317#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
318 puts("60");
319#else
Stefan Roese3d9569b2005-11-27 19:36:26 +0100320 puts("40");
wdenkc6097192002-11-03 00:24:07 +0000321#endif
Stefan Roese2801b2d2008-03-11 15:05:50 +0100322#endif
Stefan Roese3d9569b2005-11-27 19:36:26 +0100323
wdenkc6097192002-11-03 00:24:07 +0000324 switch (pvr) {
325 case PVR_405GP_RB:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100326 puts("GP Rev. B");
wdenkc6097192002-11-03 00:24:07 +0000327 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100328
wdenkc6097192002-11-03 00:24:07 +0000329 case PVR_405GP_RC:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100330 puts("GP Rev. C");
wdenkc6097192002-11-03 00:24:07 +0000331 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100332
wdenkc6097192002-11-03 00:24:07 +0000333 case PVR_405GP_RD:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100334 puts("GP Rev. D");
wdenkc6097192002-11-03 00:24:07 +0000335 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100336
wdenk42dfe7a2004-03-14 22:25:36 +0000337#ifdef CONFIG_405GP
Stefan Roese3d9569b2005-11-27 19:36:26 +0100338 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
339 puts("GP Rev. E");
wdenkc6097192002-11-03 00:24:07 +0000340 break;
341#endif
Stefan Roese3d9569b2005-11-27 19:36:26 +0100342
wdenkc6097192002-11-03 00:24:07 +0000343 case PVR_405CR_RA:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100344 puts("CR Rev. A");
wdenkc6097192002-11-03 00:24:07 +0000345 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100346
wdenkc6097192002-11-03 00:24:07 +0000347 case PVR_405CR_RB:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100348 puts("CR Rev. B");
349 break;
350
351#ifdef CONFIG_405CR
352 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
353 puts("CR Rev. C");
354 break;
355#endif
356
357 case PVR_405GPR_RB:
358 puts("GPr Rev. B");
359 break;
360
stroeseb867d702003-05-23 11:18:02 +0000361 case PVR_405EP_RB:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100362 puts("EP Rev. B");
wdenkc6097192002-11-03 00:24:07 +0000363 break;
wdenkc6097192002-11-03 00:24:07 +0000364
Stefan Roesee01bd212007-03-21 13:38:59 +0100365 case PVR_405EZ_RA:
366 puts("EZ Rev. A");
367 break;
368
Stefan Roesedbbd1252007-10-05 17:10:59 +0200369 case PVR_405EX1_RA:
370 puts("EX Rev. A");
371 strcpy(addstr, "Security support");
372 break;
373
374 case PVR_405EX2_RA:
375 puts("EX Rev. A");
376 strcpy(addstr, "No Security support");
377 break;
378
379 case PVR_405EXR1_RA:
380 puts("EXr Rev. A");
381 strcpy(addstr, "Security support");
382 break;
383
384 case PVR_405EXR2_RA:
385 puts("EXr Rev. A");
386 strcpy(addstr, "No Security support");
387 break;
388
Stefan Roese70fab192008-05-13 20:22:01 +0200389 case PVR_405EX1_RC:
390 puts("EX Rev. C");
391 strcpy(addstr, "Security support");
392 break;
393
394 case PVR_405EX2_RC:
395 puts("EX Rev. C");
396 strcpy(addstr, "No Security support");
397 break;
398
399 case PVR_405EXR1_RC:
400 puts("EXr Rev. C");
401 strcpy(addstr, "Security support");
402 break;
403
404 case PVR_405EXR2_RC:
405 puts("EXr Rev. C");
406 strcpy(addstr, "No Security support");
407 break;
408
wdenkc6097192002-11-03 00:24:07 +0000409#if defined(CONFIG_440)
wdenk8bde7f72003-06-27 21:31:46 +0000410 case PVR_440GP_RB:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200411 puts("GP Rev. B");
wdenk4d816772003-09-03 14:03:26 +0000412 /* See errata 1.12: CHIP_4 */
413 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
414 (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
415 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
416 "Resetting chip ...\n");
417 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
418 do_chip_reset ( mfdcr(cpc0_strp0),
419 mfdcr(cpc0_strp1) );
420 }
wdenkc6097192002-11-03 00:24:07 +0000421 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100422
wdenk8bde7f72003-06-27 21:31:46 +0000423 case PVR_440GP_RC:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200424 puts("GP Rev. C");
wdenkba56f622004-02-06 23:19:44 +0000425 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100426
wdenkba56f622004-02-06 23:19:44 +0000427 case PVR_440GX_RA:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200428 puts("GX Rev. A");
wdenkba56f622004-02-06 23:19:44 +0000429 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100430
wdenkba56f622004-02-06 23:19:44 +0000431 case PVR_440GX_RB:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200432 puts("GX Rev. B");
wdenkc6097192002-11-03 00:24:07 +0000433 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100434
stroese0a7c5392005-04-07 05:33:41 +0000435 case PVR_440GX_RC:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200436 puts("GX Rev. C");
stroese0a7c5392005-04-07 05:33:41 +0000437 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100438
Stefan Roese57275b62005-11-01 10:08:03 +0100439 case PVR_440GX_RF:
440 puts("GX Rev. F");
441 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100442
Stefan Roesec157d8e2005-08-01 16:41:48 +0200443 case PVR_440EP_RA:
444 puts("EP Rev. A");
445 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100446
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200447#ifdef CONFIG_440EP
448 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200449 puts("EP Rev. B");
450 break;
Stefan Roese512f8d52006-05-10 14:10:41 +0200451
452 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
453 puts("EP Rev. C");
454 break;
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200455#endif /* CONFIG_440EP */
Stefan Roese3d9569b2005-11-27 19:36:26 +0100456
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200457#ifdef CONFIG_440GR
458 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
459 puts("GR Rev. A");
460 break;
Stefan Roese512f8d52006-05-10 14:10:41 +0200461
Stefan Roese5770a1e2006-05-18 19:21:53 +0200462 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
Stefan Roese512f8d52006-05-10 14:10:41 +0200463 puts("GR Rev. B");
464 break;
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200465#endif /* CONFIG_440GR */
Stefan Roese3d9569b2005-11-27 19:36:26 +0100466#endif /* CONFIG_440 */
467
Stefan Roese2902fad2007-01-31 16:56:10 +0100468#ifdef CONFIG_440EPX
469 case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
Stefan Roeseedf0b542006-10-18 15:59:35 +0200470 puts("EPx Rev. A");
471 strcpy(addstr, "Security/Kasumi support");
Stefan Roese887e2ec2006-09-07 11:51:23 +0200472 break;
473
Stefan Roese2902fad2007-01-31 16:56:10 +0100474 case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
Stefan Roeseedf0b542006-10-18 15:59:35 +0200475 puts("EPx Rev. A");
476 strcpy(addstr, "No Security/Kasumi support");
Stefan Roese887e2ec2006-09-07 11:51:23 +0200477 break;
Stefan Roese2902fad2007-01-31 16:56:10 +0100478#endif /* CONFIG_440EPX */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200479
Stefan Roese2902fad2007-01-31 16:56:10 +0100480#ifdef CONFIG_440GRX
481 case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
Stefan Roeseedf0b542006-10-18 15:59:35 +0200482 puts("GRx Rev. A");
483 strcpy(addstr, "Security/Kasumi support");
Stefan Roese887e2ec2006-09-07 11:51:23 +0200484 break;
485
Stefan Roese2902fad2007-01-31 16:56:10 +0100486 case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
Stefan Roeseedf0b542006-10-18 15:59:35 +0200487 puts("GRx Rev. A");
488 strcpy(addstr, "No Security/Kasumi support");
Stefan Roese887e2ec2006-09-07 11:51:23 +0200489 break;
Stefan Roese2902fad2007-01-31 16:56:10 +0100490#endif /* CONFIG_440GRX */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200491
Stefan Roese95981772007-01-13 08:01:03 +0100492 case PVR_440SP_6_RAB:
493 puts("SP Rev. A/B");
494 strcpy(addstr, "RAID 6 support");
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100495 break;
496
Stefan Roese95981772007-01-13 08:01:03 +0100497 case PVR_440SP_RAB:
498 puts("SP Rev. A/B");
499 strcpy(addstr, "No RAID 6 support");
500 break;
501
502 case PVR_440SP_6_RC:
503 puts("SP Rev. C");
504 strcpy(addstr, "RAID 6 support");
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100505 break;
506
Stefan Roesee732fae2006-11-28 16:09:24 +0100507 case PVR_440SP_RC:
508 puts("SP Rev. C");
Stefan Roese95981772007-01-13 08:01:03 +0100509 strcpy(addstr, "No RAID 6 support");
510 break;
511
512 case PVR_440SPe_6_RA:
513 puts("SPe Rev. A");
514 strcpy(addstr, "RAID 6 support");
Stefan Roesee732fae2006-11-28 16:09:24 +0100515 break;
516
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200517 case PVR_440SPe_RA:
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200518 puts("SPe Rev. A");
Stefan Roese95981772007-01-13 08:01:03 +0100519 strcpy(addstr, "No RAID 6 support");
520 break;
521
522 case PVR_440SPe_6_RB:
523 puts("SPe Rev. B");
524 strcpy(addstr, "RAID 6 support");
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200525 break;
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200526
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200527 case PVR_440SPe_RB:
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200528 puts("SPe Rev. B");
Stefan Roese95981772007-01-13 08:01:03 +0100529 strcpy(addstr, "No RAID 6 support");
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200530 break;
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200531
Stefan Roese89bcc482009-07-29 08:45:27 +0200532#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
Stefan Roese2801b2d2008-03-11 15:05:50 +0100533 case PVR_460EX_RA:
534 puts("EX Rev. A");
535 strcpy(addstr, "No Security/Kasumi support");
536 break;
537
538 case PVR_460EX_SE_RA:
539 puts("EX Rev. A");
540 strcpy(addstr, "Security/Kasumi support");
541 break;
542
Stefan Roese89bcc482009-07-29 08:45:27 +0200543 case PVR_460EX_RB:
544 puts("EX Rev. B");
545 mfsdr(SDR0_ECID3, reg);
546 if (reg & 0x00100000)
547 strcpy(addstr, "No Security/Kasumi support");
548 else
549 strcpy(addstr, "Security/Kasumi support");
550 break;
551
Stefan Roese2801b2d2008-03-11 15:05:50 +0100552 case PVR_460GT_RA:
553 puts("GT Rev. A");
554 strcpy(addstr, "No Security/Kasumi support");
555 break;
556
557 case PVR_460GT_SE_RA:
558 puts("GT Rev. A");
559 strcpy(addstr, "Security/Kasumi support");
560 break;
561
Stefan Roese89bcc482009-07-29 08:45:27 +0200562 case PVR_460GT_RB:
563 puts("GT Rev. B");
564 mfsdr(SDR0_ECID3, reg);
565 if (reg & 0x00100000)
566 strcpy(addstr, "No Security/Kasumi support");
567 else
568 strcpy(addstr, "Security/Kasumi support");
569 break;
570#endif
571
Feng Kan7d307932008-07-08 22:47:31 -0700572 case PVR_460SX_RA:
573 puts("SX Rev. A");
574 strcpy(addstr, "Security support");
575 break;
576
577 case PVR_460SX_RA_V1:
578 puts("SX Rev. A");
579 strcpy(addstr, "No Security support");
580 break;
581
582 case PVR_460GX_RA:
583 puts("GX Rev. A");
584 strcpy(addstr, "Security support");
585 break;
586
587 case PVR_460GX_RA_V1:
588 puts("GX Rev. A");
589 strcpy(addstr, "No Security support");
590 break;
591
Ricardo Ribalda Delgadod865fd02008-07-17 11:44:12 +0200592 case PVR_VIRTEX5:
593 puts("x5 VIRTEX5");
594 break;
595
wdenk8bde7f72003-06-27 21:31:46 +0000596 default:
Stefan Roese17f50f222005-08-04 17:09:16 +0200597 printf (" UNKNOWN (PVR=%08x)", pvr);
wdenkc6097192002-11-03 00:24:07 +0000598 break;
599 }
Stefan Roese3d9569b2005-11-27 19:36:26 +0100600
601 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
Stefan Roesee01bd212007-03-21 13:38:59 +0100602 sys_info.freqPLB / 1000000,
603 get_OPB_freq() / 1000000,
Stefan Roesedbbd1252007-10-05 17:10:59 +0200604 sys_info.freqEBC / 1000000);
Stefan Roese3d9569b2005-11-27 19:36:26 +0100605
Stefan Roeseedf0b542006-10-18 15:59:35 +0200606 if (addstr[0] != 0)
607 printf(" %s\n", addstr);
608
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100609#if defined(I2C_BOOTROM)
610 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
Stefan Roese90e6f412007-04-18 12:05:59 +0200611#endif /* I2C_BOOTROM */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200612#if defined(SDR0_PINSTP_SHIFT)
BenoƮt Monine3cbe1f2007-06-04 08:36:05 +0200613 printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
Stefan Roesecf940982009-04-15 10:50:48 +0200614 printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
615#ifdef CONFIG_NAND_U_BOOT
616 puts(", booting from NAND");
617#endif /* CONFIG_NAND_U_BOOT */
618 putc('\n');
Wolfgang Denkba999c52006-10-20 17:54:33 +0200619#endif /* SDR0_PINSTP_SHIFT */
Stefan Roese3d9569b2005-11-27 19:36:26 +0100620
Stefan Roesedbbd1252007-10-05 17:10:59 +0200621#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100622 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
Stefan Roese3d9569b2005-11-27 19:36:26 +0100623#endif
624
Stefan Roese1bbae2b2009-05-27 10:34:32 +0200625#if defined(CONFIG_PCI) && defined(PCI_ASYNC)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100626 if (pci_async_enabled()) {
Stefan Roese3d9569b2005-11-27 19:36:26 +0100627 printf (", PCI async ext clock used");
628 } else {
629 printf (", PCI sync clock at %lu MHz",
630 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
631 }
632#endif
633
Stefan Roesedbbd1252007-10-05 17:10:59 +0200634#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
Stefan Roese3d9569b2005-11-27 19:36:26 +0100635 putc('\n');
636#endif
637
Stefan Roesedbbd1252007-10-05 17:10:59 +0200638#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
Stefan Roese3d9569b2005-11-27 19:36:26 +0100639 printf (" 16 kB I-Cache 16 kB D-Cache");
640#elif defined(CONFIG_440)
641 printf (" 32 kB I-Cache 32 kB D-Cache");
642#else
643 printf (" 16 kB I-Cache %d kB D-Cache",
644 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
645#endif
646#endif /* !defined(CONFIG_IOP480) */
647
648#if defined(CONFIG_IOP480)
649 printf ("PLX IOP480 (PVR=%08x)", pvr);
650 printf (" at %s MHz:", strmhz(buf, clock));
651 printf (" %u kB I-Cache", 4);
652 printf (" %u kB D-Cache", 2);
653#endif
654
655#endif /* !defined(CONFIG_405) */
656
657 putc ('\n');
wdenkc6097192002-11-03 00:24:07 +0000658
659 return 0;
660}
661
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200662int ppc440spe_revB() {
663 unsigned int pvr;
664
665 pvr = get_pvr();
Stefan Roese5a5c5692007-01-15 09:46:29 +0100666 if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200667 return 1;
668 else
669 return 0;
670}
wdenkc6097192002-11-03 00:24:07 +0000671
672/* ------------------------------------------------------------------------- */
673
wdenk8bde7f72003-06-27 21:31:46 +0000674int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
wdenkc6097192002-11-03 00:24:07 +0000675{
Stefan Roese1f94d162006-11-27 14:48:41 +0100676#if defined(CONFIG_BOARD_RESET)
677 board_reset();
Stefan Roese1729b922006-11-27 14:52:04 +0100678#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200679#if defined(CONFIG_SYS_4xx_RESET_TYPE)
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200680 mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28);
Stefan Roesec157d8e2005-08-01 16:41:48 +0200681#else
wdenk8bde7f72003-06-27 21:31:46 +0000682 /*
683 * Initiate system reset in debug control register DBCR
684 */
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200685 mtspr(SPRN_DBCR0, 0x30000000);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200686#endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
Stefan Roesef3443862006-10-07 11:30:52 +0200687#endif /* defined(CONFIG_BOARD_RESET) */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200688
wdenkc6097192002-11-03 00:24:07 +0000689 return 1;
690}
691
wdenkc6097192002-11-03 00:24:07 +0000692
693/*
694 * Get timebase clock frequency
695 */
696unsigned long get_tbclk (void)
697{
Stefan Roese3d9569b2005-11-27 19:36:26 +0100698#if !defined(CONFIG_IOP480)
wdenkc6097192002-11-03 00:24:07 +0000699 sys_info_t sys_info;
700
701 get_sys_info(&sys_info);
702 return (sys_info.freqProcessor);
wdenkc6097192002-11-03 00:24:07 +0000703#else
Stefan Roese3d9569b2005-11-27 19:36:26 +0100704 return (66000000);
wdenkc6097192002-11-03 00:24:07 +0000705#endif
706
707}
708
709
710#if defined(CONFIG_WATCHDOG)
Stefan Roesec7f69c32007-11-09 12:18:54 +0100711void watchdog_reset(void)
wdenkc6097192002-11-03 00:24:07 +0000712{
713 int re_enable = disable_interrupts();
714 reset_4xx_watchdog();
715 if (re_enable) enable_interrupts();
716}
717
Stefan Roesec7f69c32007-11-09 12:18:54 +0100718void reset_4xx_watchdog(void)
wdenkc6097192002-11-03 00:24:07 +0000719{
720 /*
721 * Clear TSR(WIS) bit
722 */
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200723 mtspr(SPRN_TSR, 0x40000000);
wdenkc6097192002-11-03 00:24:07 +0000724}
725#endif /* CONFIG_WATCHDOG */
Ben Warren25a85902008-10-27 23:53:17 -0700726
727/*
728 * Initializes on-chip ethernet controllers.
729 * to override, implement board_eth_init()
730 */
731int cpu_eth_init(bd_t *bis)
732{
733#if defined(CONFIG_PPC4xx_EMAC)
734 ppc_4xx_eth_initialize(bis);
735#endif
736 return 0;
737}