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wdenkc6097192002-11-03 00:24:07 +00001/*
Stefan Roese512f8d52006-05-10 14:10:41 +02002 * (C) Copyright 2000-2006
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
wdenkc6097192002-11-03 00:24:07 +000025 * CPU specific code
26 *
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
29 *
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
32 */
33
34#include <common.h>
35#include <watchdog.h>
36#include <command.h>
37#include <asm/cache.h>
38#include <ppc4xx.h>
39
Wolfgang Denkd87080b2006-03-31 18:32:53 +020040#if !defined(CONFIG_405)
41DECLARE_GLOBAL_DATA_PTR;
42#endif
43
wdenkc6097192002-11-03 00:24:07 +000044
Stefan Roese3d9569b2005-11-27 19:36:26 +010045#if defined(CONFIG_440)
46#define FREQ_EBC (sys_info.freqEPB)
47#else
48#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
49#endif
50
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010051#if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
52
53#define PCI_ASYNC
54
55int pci_async_enabled(void)
56{
57#if defined(CONFIG_405GP)
58 return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
59#endif
60
61#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
62 unsigned long val;
63
Wolfgang Denk74812662005-12-12 16:06:05 +010064 mfsdr(sdr_sdstp1, val);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010065 return (val & SDR0_SDSTP1_PAME_MASK);
66#endif
67}
68#endif
69
Stefan Roesea46726f2005-11-29 19:13:38 +010070#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010071int pci_arbiter_enabled(void)
72{
73#if defined(CONFIG_405GP)
74 return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
75#endif
76
77#if defined(CONFIG_405EP)
78 return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
79#endif
80
81#if defined(CONFIG_440GP)
82 return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
83#endif
84
Marian Balakowicz6c5879f2006-06-30 16:30:46 +020085#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
86 defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
87 defined(CONFIG_440SPE)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010088 unsigned long val;
89
90 mfsdr(sdr_sdstp1, val);
91 return (val & SDR0_SDSTP1_PAE_MASK);
92#endif
93}
94#endif
95
Marian Balakowicz6c5879f2006-06-30 16:30:46 +020096#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
97 defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010098
99#define I2C_BOOTROM
100
101int i2c_bootrom_enabled(void)
102{
103#if defined(CONFIG_405EP)
104 return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
105#endif
106
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200107#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
108 defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
109 defined(CONFIG_440SPE)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100110 unsigned long val;
111
112 mfsdr(sdr_sdcs, val);
113 return (val & SDR0_SDCS_SDD);
114#endif
115}
116#endif
117
Stefan Roese3d9569b2005-11-27 19:36:26 +0100118
119#if defined(CONFIG_440)
120static int do_chip_reset(unsigned long sys0, unsigned long sys1);
121#endif
122
wdenkc6097192002-11-03 00:24:07 +0000123
124int checkcpu (void)
125{
Stefan Roese3d9569b2005-11-27 19:36:26 +0100126#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
Stefan Roese3d9569b2005-11-27 19:36:26 +0100127 uint pvr = get_pvr();
wdenkc6097192002-11-03 00:24:07 +0000128 ulong clock = gd->cpu_clk;
129 char buf[32];
wdenkc6097192002-11-03 00:24:07 +0000130
Stefan Roese3d9569b2005-11-27 19:36:26 +0100131#if !defined(CONFIG_IOP480)
132 sys_info_t sys_info;
wdenkc6097192002-11-03 00:24:07 +0000133
134 puts ("CPU: ");
135
136 get_sys_info(&sys_info);
137
Stefan Roese3d9569b2005-11-27 19:36:26 +0100138 puts("AMCC PowerPC 4");
139
140#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
141 puts("05");
wdenkc6097192002-11-03 00:24:07 +0000142#endif
Stefan Roese3d9569b2005-11-27 19:36:26 +0100143#if defined(CONFIG_440)
144 puts("40");
wdenkc6097192002-11-03 00:24:07 +0000145#endif
Stefan Roese3d9569b2005-11-27 19:36:26 +0100146
wdenkc6097192002-11-03 00:24:07 +0000147 switch (pvr) {
148 case PVR_405GP_RB:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100149 puts("GP Rev. B");
wdenkc6097192002-11-03 00:24:07 +0000150 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100151
wdenkc6097192002-11-03 00:24:07 +0000152 case PVR_405GP_RC:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100153 puts("GP Rev. C");
wdenkc6097192002-11-03 00:24:07 +0000154 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100155
wdenkc6097192002-11-03 00:24:07 +0000156 case PVR_405GP_RD:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100157 puts("GP Rev. D");
wdenkc6097192002-11-03 00:24:07 +0000158 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100159
wdenk42dfe7a2004-03-14 22:25:36 +0000160#ifdef CONFIG_405GP
Stefan Roese3d9569b2005-11-27 19:36:26 +0100161 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
162 puts("GP Rev. E");
wdenkc6097192002-11-03 00:24:07 +0000163 break;
164#endif
Stefan Roese3d9569b2005-11-27 19:36:26 +0100165
wdenkc6097192002-11-03 00:24:07 +0000166 case PVR_405CR_RA:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100167 puts("CR Rev. A");
wdenkc6097192002-11-03 00:24:07 +0000168 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100169
wdenkc6097192002-11-03 00:24:07 +0000170 case PVR_405CR_RB:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100171 puts("CR Rev. B");
172 break;
173
174#ifdef CONFIG_405CR
175 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
176 puts("CR Rev. C");
177 break;
178#endif
179
180 case PVR_405GPR_RB:
181 puts("GPr Rev. B");
182 break;
183
stroeseb867d702003-05-23 11:18:02 +0000184 case PVR_405EP_RB:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100185 puts("EP Rev. B");
wdenkc6097192002-11-03 00:24:07 +0000186 break;
wdenkc6097192002-11-03 00:24:07 +0000187
188#if defined(CONFIG_440)
wdenk8bde7f72003-06-27 21:31:46 +0000189 case PVR_440GP_RB:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200190 puts("GP Rev. B");
wdenk4d816772003-09-03 14:03:26 +0000191 /* See errata 1.12: CHIP_4 */
192 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
193 (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
194 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
195 "Resetting chip ...\n");
196 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
197 do_chip_reset ( mfdcr(cpc0_strp0),
198 mfdcr(cpc0_strp1) );
199 }
wdenkc6097192002-11-03 00:24:07 +0000200 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100201
wdenk8bde7f72003-06-27 21:31:46 +0000202 case PVR_440GP_RC:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200203 puts("GP Rev. C");
wdenkba56f622004-02-06 23:19:44 +0000204 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100205
wdenkba56f622004-02-06 23:19:44 +0000206 case PVR_440GX_RA:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200207 puts("GX Rev. A");
wdenkba56f622004-02-06 23:19:44 +0000208 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100209
wdenkba56f622004-02-06 23:19:44 +0000210 case PVR_440GX_RB:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200211 puts("GX Rev. B");
wdenkc6097192002-11-03 00:24:07 +0000212 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100213
stroese0a7c5392005-04-07 05:33:41 +0000214 case PVR_440GX_RC:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200215 puts("GX Rev. C");
stroese0a7c5392005-04-07 05:33:41 +0000216 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100217
Stefan Roese57275b62005-11-01 10:08:03 +0100218 case PVR_440GX_RF:
219 puts("GX Rev. F");
220 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100221
Stefan Roesec157d8e2005-08-01 16:41:48 +0200222 case PVR_440EP_RA:
223 puts("EP Rev. A");
224 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100225
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200226#ifdef CONFIG_440EP
227 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200228 puts("EP Rev. B");
229 break;
Stefan Roese512f8d52006-05-10 14:10:41 +0200230
231 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
232 puts("EP Rev. C");
233 break;
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200234#endif /* CONFIG_440EP */
Stefan Roese3d9569b2005-11-27 19:36:26 +0100235
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200236#ifdef CONFIG_440GR
237 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
238 puts("GR Rev. A");
239 break;
Stefan Roese512f8d52006-05-10 14:10:41 +0200240
Stefan Roese5770a1e2006-05-18 19:21:53 +0200241 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
Stefan Roese512f8d52006-05-10 14:10:41 +0200242 puts("GR Rev. B");
243 break;
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200244#endif /* CONFIG_440GR */
Stefan Roese3d9569b2005-11-27 19:36:26 +0100245#endif /* CONFIG_440 */
246
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100247 case PVR_440SP_RA:
248 puts("SP Rev. A");
249 break;
250
251 case PVR_440SP_RB:
252 puts("SP Rev. B");
253 break;
254
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200255 case PVR_440SPe_RA:
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200256 puts("SPe Rev. A");
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200257 break;
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200258
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200259 case PVR_440SPe_RB:
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200260 puts("SPe Rev. B");
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200261 break;
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200262
wdenk8bde7f72003-06-27 21:31:46 +0000263 default:
Stefan Roese17f50f222005-08-04 17:09:16 +0200264 printf (" UNKNOWN (PVR=%08x)", pvr);
wdenkc6097192002-11-03 00:24:07 +0000265 break;
266 }
Stefan Roese3d9569b2005-11-27 19:36:26 +0100267
268 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
269 sys_info.freqPLB / 1000000,
270 sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
271 FREQ_EBC / 1000000);
272
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100273#if defined(I2C_BOOTROM)
274 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
wdenkc6097192002-11-03 00:24:07 +0000275#endif
Stefan Roese3d9569b2005-11-27 19:36:26 +0100276
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100277#if defined(CONFIG_PCI)
278 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
Stefan Roese3d9569b2005-11-27 19:36:26 +0100279#endif
280
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100281#if defined(PCI_ASYNC)
282 if (pci_async_enabled()) {
Stefan Roese3d9569b2005-11-27 19:36:26 +0100283 printf (", PCI async ext clock used");
284 } else {
285 printf (", PCI sync clock at %lu MHz",
286 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
287 }
288#endif
289
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100290#if defined(CONFIG_PCI)
Stefan Roese3d9569b2005-11-27 19:36:26 +0100291 putc('\n');
292#endif
293
294#if defined(CONFIG_405EP)
295 printf (" 16 kB I-Cache 16 kB D-Cache");
296#elif defined(CONFIG_440)
297 printf (" 32 kB I-Cache 32 kB D-Cache");
298#else
299 printf (" 16 kB I-Cache %d kB D-Cache",
300 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
301#endif
302#endif /* !defined(CONFIG_IOP480) */
303
304#if defined(CONFIG_IOP480)
305 printf ("PLX IOP480 (PVR=%08x)", pvr);
306 printf (" at %s MHz:", strmhz(buf, clock));
307 printf (" %u kB I-Cache", 4);
308 printf (" %u kB D-Cache", 2);
309#endif
310
311#endif /* !defined(CONFIG_405) */
312
313 putc ('\n');
wdenkc6097192002-11-03 00:24:07 +0000314
315 return 0;
316}
317
318
319/* ------------------------------------------------------------------------- */
320
wdenk8bde7f72003-06-27 21:31:46 +0000321int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
wdenkc6097192002-11-03 00:24:07 +0000322{
Stefan Roesec157d8e2005-08-01 16:41:48 +0200323#if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)
324 /*give reset to BCSR*/
325 *(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09;
326
327#else
328
wdenk8bde7f72003-06-27 21:31:46 +0000329 /*
330 * Initiate system reset in debug control register DBCR
331 */
wdenkc6097192002-11-03 00:24:07 +0000332 __asm__ __volatile__("lis 3, 0x3000" ::: "r3");
333#if defined(CONFIG_440)
334 __asm__ __volatile__("mtspr 0x134, 3");
335#else
336 __asm__ __volatile__("mtspr 0x3f2, 3");
337#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +0200338
339#endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/
wdenkc6097192002-11-03 00:24:07 +0000340 return 1;
341}
342
343#if defined(CONFIG_440)
Stefan Roese3d9569b2005-11-27 19:36:26 +0100344static int do_chip_reset (unsigned long sys0, unsigned long sys1)
wdenkc6097192002-11-03 00:24:07 +0000345{
wdenk4d816772003-09-03 14:03:26 +0000346 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
347 * reset.
348 */
349 mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
350 mtdcr (cpc0_sys0, sys0);
351 mtdcr (cpc0_sys1, sys1);
352 mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
353 mtspr (dbcr0, 0x20000000); /* Reset the chip */
wdenkc6097192002-11-03 00:24:07 +0000354
wdenk4d816772003-09-03 14:03:26 +0000355 return 1;
wdenkc6097192002-11-03 00:24:07 +0000356}
357#endif
358
359
360/*
361 * Get timebase clock frequency
362 */
363unsigned long get_tbclk (void)
364{
Stefan Roese3d9569b2005-11-27 19:36:26 +0100365#if !defined(CONFIG_IOP480)
wdenkc6097192002-11-03 00:24:07 +0000366 sys_info_t sys_info;
367
368 get_sys_info(&sys_info);
369 return (sys_info.freqProcessor);
wdenkc6097192002-11-03 00:24:07 +0000370#else
Stefan Roese3d9569b2005-11-27 19:36:26 +0100371 return (66000000);
wdenkc6097192002-11-03 00:24:07 +0000372#endif
373
374}
375
376
377#if defined(CONFIG_WATCHDOG)
378void
379watchdog_reset(void)
380{
381 int re_enable = disable_interrupts();
382 reset_4xx_watchdog();
383 if (re_enable) enable_interrupts();
384}
385
386void
387reset_4xx_watchdog(void)
388{
389 /*
390 * Clear TSR(WIS) bit
391 */
392 mtspr(tsr, 0x40000000);
393}
394#endif /* CONFIG_WATCHDOG */