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Sascha Hauercdace062008-03-26 20:40:49 +01001/*
Marek Vasutdb841402011-09-22 09:22:12 +00002 * i2c driver for Freescale i.MX series
Sascha Hauercdace062008-03-26 20:40:49 +01003 *
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
Marek Vasutdb841402011-09-22 09:22:12 +00005 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
6 *
7 * Based on i2c-imx.c from linux kernel:
8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
10 * Copyright (C) 2007 RightHand Technologies, Inc.
11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
12 *
Sascha Hauercdace062008-03-26 20:40:49 +010013 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020014 * SPDX-License-Identifier: GPL-2.0+
Sascha Hauercdace062008-03-26 20:40:49 +010015 */
16
17#include <common.h>
Liu Hui-R64343127cec12011-01-03 22:27:39 +000018#include <asm/arch/clock.h>
Stefano Babic86271112011-03-14 15:43:56 +010019#include <asm/arch/imx-regs.h>
Troy Kiskycea60b02012-07-19 08:18:04 +000020#include <asm/errno.h>
Peng Fan71204e92015-05-15 07:29:12 +080021#include <asm/imx-common/mxc_i2c.h>
Troy Kisky24cd7382012-07-19 08:18:03 +000022#include <asm/io.h>
Marek Vasutbf0783d2011-10-26 00:05:44 +000023#include <i2c.h>
Troy Kisky7aa57a02012-07-19 08:18:09 +000024#include <watchdog.h>
Peng Fan71204e92015-05-15 07:29:12 +080025#include <dm.h>
26#include <fdtdec.h>
Sascha Hauercdace062008-03-26 20:40:49 +010027
York Sundec18612014-02-10 14:02:52 -080028DECLARE_GLOBAL_DATA_PTR;
29
Peng Fan71204e92015-05-15 07:29:12 +080030#define I2C_QUIRK_FLAG (1 << 0)
31
32#define IMX_I2C_REGSHIFT 2
33#define VF610_I2C_REGSHIFT 0
34/* Register index */
35#define IADR 0
36#define IFDR 1
37#define I2CR 2
38#define I2SR 3
39#define I2DR 4
Sascha Hauercdace062008-03-26 20:40:49 +010040
Sascha Hauercdace062008-03-26 20:40:49 +010041#define I2CR_IIEN (1 << 6)
42#define I2CR_MSTA (1 << 5)
43#define I2CR_MTX (1 << 4)
44#define I2CR_TX_NO_AK (1 << 3)
45#define I2CR_RSTA (1 << 2)
46
47#define I2SR_ICF (1 << 7)
48#define I2SR_IBB (1 << 5)
Troy Kiskyd5383a62012-07-19 08:18:15 +000049#define I2SR_IAL (1 << 4)
Sascha Hauercdace062008-03-26 20:40:49 +010050#define I2SR_IIF (1 << 1)
51#define I2SR_RX_NO_AK (1 << 0)
52
Alison Wang30ea41a2013-06-17 15:30:39 +080053#ifdef I2C_QUIRK_REG
54#define I2CR_IEN (0 << 7)
55#define I2CR_IDIS (1 << 7)
56#define I2SR_IIF_CLEAR (1 << 1)
57#else
58#define I2CR_IEN (1 << 7)
59#define I2CR_IDIS (0 << 7)
60#define I2SR_IIF_CLEAR (0 << 1)
61#endif
62
Troy Kiskye4ff5252012-07-19 08:18:18 +000063#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
Troy Kiskyde6f6042012-04-24 17:33:25 +000064#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
Sascha Hauercdace062008-03-26 20:40:49 +010065#endif
66
Alison Wang30ea41a2013-06-17 15:30:39 +080067#ifdef I2C_QUIRK_REG
68static u16 i2c_clk_div[60][2] = {
69 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
70 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
71 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
72 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
73 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
74 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
75 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
76 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
77 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
78 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
79 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
80 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
81 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
82 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
83 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
84};
85#else
Marek Vasutdb841402011-09-22 09:22:12 +000086static u16 i2c_clk_div[50][2] = {
87 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
88 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
89 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
90 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
91 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
92 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
93 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
94 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
95 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
96 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
97 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
98 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
99 { 3072, 0x1E }, { 3840, 0x1F }
100};
Alison Wang30ea41a2013-06-17 15:30:39 +0800101#endif
Sascha Hauercdace062008-03-26 20:40:49 +0100102
tremfac96402013-09-21 18:13:35 +0200103#ifndef CONFIG_SYS_MXC_I2C1_SPEED
104#define CONFIG_SYS_MXC_I2C1_SPEED 100000
105#endif
106#ifndef CONFIG_SYS_MXC_I2C2_SPEED
107#define CONFIG_SYS_MXC_I2C2_SPEED 100000
108#endif
109#ifndef CONFIG_SYS_MXC_I2C3_SPEED
110#define CONFIG_SYS_MXC_I2C3_SPEED 100000
111#endif
York Sunf8cb1012015-03-20 10:20:40 -0700112#ifndef CONFIG_SYS_MXC_I2C4_SPEED
113#define CONFIG_SYS_MXC_I2C4_SPEED 100000
114#endif
tremfac96402013-09-21 18:13:35 +0200115
116#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
117#define CONFIG_SYS_MXC_I2C1_SLAVE 0
118#endif
119#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
120#define CONFIG_SYS_MXC_I2C2_SLAVE 0
121#endif
122#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
123#define CONFIG_SYS_MXC_I2C3_SLAVE 0
124#endif
York Sunf8cb1012015-03-20 10:20:40 -0700125#ifndef CONFIG_SYS_MXC_I2C4_SLAVE
126#define CONFIG_SYS_MXC_I2C4_SLAVE 0
127#endif
tremfac96402013-09-21 18:13:35 +0200128
Marek Vasutdb841402011-09-22 09:22:12 +0000129/*
130 * Calculate and set proper clock divider
131 */
Peng Fan71204e92015-05-15 07:29:12 +0800132static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
Stefano Babic1d549ad2011-01-20 07:50:44 +0000133{
Marek Vasutdb841402011-09-22 09:22:12 +0000134 unsigned int i2c_clk_rate;
135 unsigned int div;
Marek Vasutbf0783d2011-10-26 00:05:44 +0000136 u8 clk_div;
Sascha Hauercdace062008-03-26 20:40:49 +0100137
Liu Hui-R64343127cec12011-01-03 22:27:39 +0000138#if defined(CONFIG_MX31)
Stefano Babic1d549ad2011-01-20 07:50:44 +0000139 struct clock_control_regs *sc_regs =
140 (struct clock_control_regs *)CCM_BASE;
Marek Vasutdb841402011-09-22 09:22:12 +0000141
Guennadi Liakhovetskie7de18a2009-02-13 09:23:36 +0100142 /* start the required I2C clock */
Troy Kiskyde6f6042012-04-24 17:33:25 +0000143 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
Stefano Babic1d549ad2011-01-20 07:50:44 +0000144 &sc_regs->cgr0);
Liu Hui-R64343127cec12011-01-03 22:27:39 +0000145#endif
Guennadi Liakhovetskie7de18a2009-02-13 09:23:36 +0100146
Marek Vasutdb841402011-09-22 09:22:12 +0000147 /* Divider value calculation */
Matthias Weissere7bed5c2012-09-24 02:46:53 +0000148 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
Marek Vasutdb841402011-09-22 09:22:12 +0000149 div = (i2c_clk_rate + rate - 1) / rate;
150 if (div < i2c_clk_div[0][0])
Marek Vasutb567b8f2011-09-27 06:34:11 +0000151 clk_div = 0;
Marek Vasutdb841402011-09-22 09:22:12 +0000152 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
Marek Vasutb567b8f2011-09-27 06:34:11 +0000153 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
Marek Vasutdb841402011-09-22 09:22:12 +0000154 else
Marek Vasutb567b8f2011-09-27 06:34:11 +0000155 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
Marek Vasutdb841402011-09-22 09:22:12 +0000156 ;
Sascha Hauercdace062008-03-26 20:40:49 +0100157
Marek Vasutdb841402011-09-22 09:22:12 +0000158 /* Store divider value */
Marek Vasutbf0783d2011-10-26 00:05:44 +0000159 return clk_div;
Marek Vasutdb841402011-09-22 09:22:12 +0000160}
Sascha Hauercdace062008-03-26 20:40:49 +0100161
Marek Vasutdb841402011-09-22 09:22:12 +0000162/*
Troy Kiskye4ff5252012-07-19 08:18:18 +0000163 * Set I2C Bus speed
Marek Vasutdb841402011-09-22 09:22:12 +0000164 */
Peng Fan71204e92015-05-15 07:29:12 +0800165static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
Marek Vasutdb841402011-09-22 09:22:12 +0000166{
Peng Fan71204e92015-05-15 07:29:12 +0800167 ulong base = i2c_bus->base;
168 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
169 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
Marek Vasutbf0783d2011-10-26 00:05:44 +0000170 u8 idx = i2c_clk_div[clk_idx][1];
Peng Fan71204e92015-05-15 07:29:12 +0800171 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
Marek Vasutbf0783d2011-10-26 00:05:44 +0000172
Heiko Schochere6c8b712015-05-18 10:58:12 +0200173 if (!base)
174 return -ENODEV;
175
Marek Vasutbf0783d2011-10-26 00:05:44 +0000176 /* Store divider value */
Peng Fan71204e92015-05-15 07:29:12 +0800177 writeb(idx, base + (IFDR << reg_shift));
Marek Vasutbf0783d2011-10-26 00:05:44 +0000178
Troy Kisky83a1a192012-07-19 08:18:12 +0000179 /* Reset module */
Peng Fan71204e92015-05-15 07:29:12 +0800180 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
181 writeb(0, base + (I2SR << reg_shift));
Marek Vasutb567b8f2011-09-27 06:34:11 +0000182 return 0;
183}
184
Troy Kisky7aa57a02012-07-19 08:18:09 +0000185#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
186#define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
187#define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
188
Peng Fan71204e92015-05-15 07:29:12 +0800189static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
Stefano Babic81687212011-01-20 07:51:31 +0000190{
Troy Kisky7aa57a02012-07-19 08:18:09 +0000191 unsigned sr;
192 ulong elapsed;
Peng Fan71204e92015-05-15 07:29:12 +0800193 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
194 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
195 ulong base = i2c_bus->base;
Troy Kisky7aa57a02012-07-19 08:18:09 +0000196 ulong start_time = get_timer(0);
197 for (;;) {
Peng Fan71204e92015-05-15 07:29:12 +0800198 sr = readb(base + (I2SR << reg_shift));
Troy Kiskyd5383a62012-07-19 08:18:15 +0000199 if (sr & I2SR_IAL) {
Peng Fan71204e92015-05-15 07:29:12 +0800200 if (quirk)
201 writeb(sr | I2SR_IAL, base +
202 (I2SR << reg_shift));
203 else
204 writeb(sr & ~I2SR_IAL, base +
205 (I2SR << reg_shift));
Troy Kiskyd5383a62012-07-19 08:18:15 +0000206 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
Peng Fan71204e92015-05-15 07:29:12 +0800207 __func__, sr, readb(base + (I2CR << reg_shift)),
208 state);
Troy Kiskyd5383a62012-07-19 08:18:15 +0000209 return -ERESTART;
210 }
Troy Kisky7aa57a02012-07-19 08:18:09 +0000211 if ((sr & (state >> 8)) == (unsigned char)state)
212 return sr;
213 WATCHDOG_RESET();
214 elapsed = get_timer(start_time);
215 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
216 break;
Stefano Babic81687212011-01-20 07:51:31 +0000217 }
Troy Kisky7aa57a02012-07-19 08:18:09 +0000218 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
Peng Fan71204e92015-05-15 07:29:12 +0800219 sr, readb(base + (I2CR << reg_shift)), state);
Troy Kiskycea60b02012-07-19 08:18:04 +0000220 return -ETIMEDOUT;
Stefano Babic81687212011-01-20 07:51:31 +0000221}
222
Peng Fan71204e92015-05-15 07:29:12 +0800223static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
Sascha Hauercdace062008-03-26 20:40:49 +0100224{
Troy Kiskycea60b02012-07-19 08:18:04 +0000225 int ret;
Peng Fan71204e92015-05-15 07:29:12 +0800226 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
227 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
228 ulong base = i2c_bus->base;
Sascha Hauercdace062008-03-26 20:40:49 +0100229
Peng Fan71204e92015-05-15 07:29:12 +0800230 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
231 writeb(byte, base + (I2DR << reg_shift));
232
233 ret = wait_for_sr_state(i2c_bus, ST_IIF);
Troy Kiskycea60b02012-07-19 08:18:04 +0000234 if (ret < 0)
235 return ret;
Troy Kiskycea60b02012-07-19 08:18:04 +0000236 if (ret & I2SR_RX_NO_AK)
237 return -ENODEV;
238 return 0;
Marek Vasutdb841402011-09-22 09:22:12 +0000239}
240
241/*
Peng Fan71204e92015-05-15 07:29:12 +0800242 * Stub implementations for outer i2c slave operations.
243 */
244void __i2c_force_reset_slave(void)
245{
246}
247void i2c_force_reset_slave(void)
248 __attribute__((weak, alias("__i2c_force_reset_slave")));
249
250/*
Troy Kisky90a5b702012-07-19 08:18:13 +0000251 * Stop I2C transaction
Marek Vasutdb841402011-09-22 09:22:12 +0000252 */
Peng Fan71204e92015-05-15 07:29:12 +0800253static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
Sascha Hauercdace062008-03-26 20:40:49 +0100254{
Troy Kisky7aa57a02012-07-19 08:18:09 +0000255 int ret;
Peng Fan71204e92015-05-15 07:29:12 +0800256 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
257 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
258 ulong base = i2c_bus->base;
259 unsigned int temp = readb(base + (I2CR << reg_shift));
Sascha Hauercdace062008-03-26 20:40:49 +0100260
Troy Kisky1c076db2012-07-19 08:18:02 +0000261 temp &= ~(I2CR_MSTA | I2CR_MTX);
Peng Fan71204e92015-05-15 07:29:12 +0800262 writeb(temp, base + (I2CR << reg_shift));
263 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
Troy Kisky7aa57a02012-07-19 08:18:09 +0000264 if (ret < 0)
265 printf("%s:trigger stop failed\n", __func__);
Sascha Hauercdace062008-03-26 20:40:49 +0100266}
267
Marek Vasutdb841402011-09-22 09:22:12 +0000268/*
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000269 * Send start signal, chip address and
270 * write register address
Marek Vasutdb841402011-09-22 09:22:12 +0000271 */
Peng Fan71204e92015-05-15 07:29:12 +0800272static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
273 u32 addr, int alen)
Sascha Hauercdace062008-03-26 20:40:49 +0100274{
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000275 unsigned int temp;
276 int ret;
Peng Fan71204e92015-05-15 07:29:12 +0800277 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
278 ulong base = i2c_bus->base;
279 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
280
281 /* Reset i2c slave */
282 i2c_force_reset_slave();
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000283
284 /* Enable I2C controller */
Peng Fan71204e92015-05-15 07:29:12 +0800285 if (quirk)
286 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
287 else
288 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
289
290 if (ret) {
291 writeb(I2CR_IEN, base + (I2CR << reg_shift));
Troy Kisky90a5b702012-07-19 08:18:13 +0000292 /* Wait for controller to be stable */
293 udelay(50);
294 }
Peng Fan71204e92015-05-15 07:29:12 +0800295
296 if (readb(base + (IADR << reg_shift)) == (chip << 1))
297 writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
298 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
299 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
Troy Kisky90a5b702012-07-19 08:18:13 +0000300 if (ret < 0)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000301 return ret;
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000302
303 /* Start I2C transaction */
Peng Fan71204e92015-05-15 07:29:12 +0800304 temp = readb(base + (I2CR << reg_shift));
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000305 temp |= I2CR_MSTA;
Peng Fan71204e92015-05-15 07:29:12 +0800306 writeb(temp, base + (I2CR << reg_shift));
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000307
Peng Fan71204e92015-05-15 07:29:12 +0800308 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000309 if (ret < 0)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000310 return ret;
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000311
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000312 temp |= I2CR_MTX | I2CR_TX_NO_AK;
Peng Fan71204e92015-05-15 07:29:12 +0800313 writeb(temp, base + (I2CR << reg_shift));
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000314
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000315 /* write slave address */
Peng Fan71204e92015-05-15 07:29:12 +0800316 ret = tx_byte(i2c_bus, chip << 1);
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000317 if (ret < 0)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000318 return ret;
Marek Vasutdb841402011-09-22 09:22:12 +0000319
Marek Vasutbf0783d2011-10-26 00:05:44 +0000320 while (alen--) {
Peng Fan71204e92015-05-15 07:29:12 +0800321 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
Troy Kiskycea60b02012-07-19 08:18:04 +0000322 if (ret < 0)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000323 return ret;
Stefano Babic81687212011-01-20 07:51:31 +0000324 }
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000325 return 0;
Troy Kiskya7f1a002012-07-19 08:18:16 +0000326}
327
Peng Fan71204e92015-05-15 07:29:12 +0800328#ifndef CONFIG_DM_I2C
329int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
330{
331 if (i2c_bus && i2c_bus->idle_bus_fn)
332 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
333 return 0;
334}
335#else
336/*
337 * Since pinmux is not supported, implement a weak function here.
338 * You can implement your i2c_bus_idle in board file. When pinctrl
339 * is supported, this can be removed.
340 */
341int __i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
342{
343 return 0;
344}
Troy Kisky96c19bd2012-07-19 08:18:19 +0000345
Peng Fan71204e92015-05-15 07:29:12 +0800346int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
347 __attribute__((weak, alias("__i2c_idle_bus")));
348#endif
349
350static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
351 u32 addr, int alen)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000352{
353 int retry;
354 int ret;
Peng Fan71204e92015-05-15 07:29:12 +0800355 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
356 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
Heiko Schochere6c8b712015-05-18 10:58:12 +0200357
358 if (!i2c_bus->base)
359 return -ENODEV;
360
Troy Kiskya7f1a002012-07-19 08:18:16 +0000361 for (retry = 0; retry < 3; retry++) {
Peng Fan71204e92015-05-15 07:29:12 +0800362 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
Troy Kiskya7f1a002012-07-19 08:18:16 +0000363 if (ret >= 0)
364 return 0;
Peng Fan71204e92015-05-15 07:29:12 +0800365 i2c_imx_stop(i2c_bus);
Troy Kiskya7f1a002012-07-19 08:18:16 +0000366 if (ret == -ENODEV)
367 return ret;
368
369 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
370 retry);
371 if (ret != -ERESTART)
Alison Wang30ea41a2013-06-17 15:30:39 +0800372 /* Disable controller */
Peng Fan71204e92015-05-15 07:29:12 +0800373 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
Troy Kiskya7f1a002012-07-19 08:18:16 +0000374 udelay(100);
Peng Fan71204e92015-05-15 07:29:12 +0800375 if (i2c_idle_bus(i2c_bus) < 0)
Troy Kisky96c19bd2012-07-19 08:18:19 +0000376 break;
Troy Kiskya7f1a002012-07-19 08:18:16 +0000377 }
Peng Fan71204e92015-05-15 07:29:12 +0800378 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
Marek Vasutdb841402011-09-22 09:22:12 +0000379 return ret;
Sascha Hauercdace062008-03-26 20:40:49 +0100380}
381
Peng Fan71204e92015-05-15 07:29:12 +0800382
383static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
384 int len)
385{
386 int i, ret = 0;
387
388 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
389 debug("write_data: ");
390 /* use rc for counter */
391 for (i = 0; i < len; ++i)
392 debug(" 0x%02x", buf[i]);
393 debug("\n");
394
395 for (i = 0; i < len; i++) {
396 ret = tx_byte(i2c_bus, buf[i]);
397 if (ret < 0) {
398 debug("i2c_write_data(): rc=%d\n", ret);
399 break;
400 }
401 }
402
403 return ret;
404}
405
406static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
407 int len)
Marek Vasutdb841402011-09-22 09:22:12 +0000408{
Marek Vasutdb841402011-09-22 09:22:12 +0000409 int ret;
410 unsigned int temp;
411 int i;
Peng Fan71204e92015-05-15 07:29:12 +0800412 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
413 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
414 ulong base = i2c_bus->base;
Marek Vasutdb841402011-09-22 09:22:12 +0000415
Peng Fan71204e92015-05-15 07:29:12 +0800416 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
Marek Vasutdb841402011-09-22 09:22:12 +0000417
418 /* setup bus to read data */
Peng Fan71204e92015-05-15 07:29:12 +0800419 temp = readb(base + (I2CR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000420 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
421 if (len == 1)
422 temp |= I2CR_TX_NO_AK;
Peng Fan71204e92015-05-15 07:29:12 +0800423 writeb(temp, base + (I2CR << reg_shift));
424 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
425 /* dummy read to clear ICF */
426 readb(base + (I2DR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000427
428 /* read data */
429 for (i = 0; i < len; i++) {
Peng Fan71204e92015-05-15 07:29:12 +0800430 ret = wait_for_sr_state(i2c_bus, ST_IIF);
Troy Kisky7aa57a02012-07-19 08:18:09 +0000431 if (ret < 0) {
Peng Fan71204e92015-05-15 07:29:12 +0800432 debug("i2c_read_data(): ret=%d\n", ret);
433 i2c_imx_stop(i2c_bus);
Marek Vasutdb841402011-09-22 09:22:12 +0000434 return ret;
Troy Kiskyc4330d22012-07-19 08:18:07 +0000435 }
Marek Vasutdb841402011-09-22 09:22:12 +0000436
437 /*
438 * It must generate STOP before read I2DR to prevent
439 * controller from generating another clock cycle
440 */
441 if (i == (len - 1)) {
Peng Fan71204e92015-05-15 07:29:12 +0800442 i2c_imx_stop(i2c_bus);
Marek Vasutdb841402011-09-22 09:22:12 +0000443 } else if (i == (len - 2)) {
Peng Fan71204e92015-05-15 07:29:12 +0800444 temp = readb(base + (I2CR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000445 temp |= I2CR_TX_NO_AK;
Peng Fan71204e92015-05-15 07:29:12 +0800446 writeb(temp, base + (I2CR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000447 }
Peng Fan71204e92015-05-15 07:29:12 +0800448 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
449 buf[i] = readb(base + (I2DR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000450 }
Peng Fan71204e92015-05-15 07:29:12 +0800451
452 /* reuse ret for counter*/
453 for (ret = 0; ret < len; ++ret)
454 debug(" 0x%02x", buf[ret]);
455 debug("\n");
456
457 i2c_imx_stop(i2c_bus);
Troy Kisky7aa57a02012-07-19 08:18:09 +0000458 return 0;
Marek Vasutdb841402011-09-22 09:22:12 +0000459}
460
Peng Fan71204e92015-05-15 07:29:12 +0800461#ifndef CONFIG_DM_I2C
462/*
463 * Read data from I2C device
464 */
465static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
466 int alen, u8 *buf, int len)
467{
468 int ret = 0;
469 u32 temp;
470 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
471 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
472 ulong base = i2c_bus->base;
473
474 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
475 if (ret < 0)
476 return ret;
477
478 temp = readb(base + (I2CR << reg_shift));
479 temp |= I2CR_RSTA;
480 writeb(temp, base + (I2CR << reg_shift));
481
482 ret = tx_byte(i2c_bus, (chip << 1) | 1);
483 if (ret < 0) {
484 i2c_imx_stop(i2c_bus);
485 return ret;
486 }
487
488 ret = i2c_read_data(i2c_bus, chip, buf, len);
489
490 i2c_imx_stop(i2c_bus);
491 return ret;
492}
493
Marek Vasutdb841402011-09-22 09:22:12 +0000494/*
495 * Write data to I2C device
496 */
Peng Fan71204e92015-05-15 07:29:12 +0800497static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
498 int alen, const u8 *buf, int len)
Sascha Hauercdace062008-03-26 20:40:49 +0100499{
Peng Fan71204e92015-05-15 07:29:12 +0800500 int ret = 0;
Sascha Hauercdace062008-03-26 20:40:49 +0100501
Peng Fan71204e92015-05-15 07:29:12 +0800502 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
Troy Kiskycea60b02012-07-19 08:18:04 +0000503 if (ret < 0)
Marek Vasutdb841402011-09-22 09:22:12 +0000504 return ret;
Sascha Hauercdace062008-03-26 20:40:49 +0100505
Peng Fan71204e92015-05-15 07:29:12 +0800506 ret = i2c_write_data(i2c_bus, chip, buf, len);
507
508 i2c_imx_stop(i2c_bus);
509
Marek Vasutdb841402011-09-22 09:22:12 +0000510 return ret;
Sascha Hauercdace062008-03-26 20:40:49 +0100511}
Troy Kiskycfbb88d2012-07-19 08:18:08 +0000512
Heiko Schochere6c8b712015-05-18 10:58:12 +0200513#if !defined(I2C2_BASE_ADDR)
514#define I2C2_BASE_ADDR 0
Heiko Schocher21a26942015-05-18 10:56:24 +0200515#endif
Heiko Schochere6c8b712015-05-18 10:58:12 +0200516
517#if !defined(I2C3_BASE_ADDR)
518#define I2C3_BASE_ADDR 0
519#endif
520
521#if !defined(I2C4_BASE_ADDR)
522#define I2C4_BASE_ADDR 0
523#endif
524
525static struct mxc_i2c_bus mxc_i2c_buses[] = {
Albert ARIBAUD \(3ADEV\)b44e60a2015-06-19 14:18:29 +0200526#if defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LSCH3) || \
527 defined(CONFIG_VF610)
Peng Fan71204e92015-05-15 07:29:12 +0800528 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
529 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
530 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
531 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
Troy Kiskye4ff5252012-07-19 08:18:18 +0000532#else
Heiko Schochere6c8b712015-05-18 10:58:12 +0200533 { 0, I2C1_BASE_ADDR, 0 },
534 { 1, I2C2_BASE_ADDR, 0 },
535 { 2, I2C3_BASE_ADDR, 0 },
536 { 3, I2C4_BASE_ADDR, 0 },
Troy Kiskye4ff5252012-07-19 08:18:18 +0000537#endif
tremfac96402013-09-21 18:13:35 +0200538};
539
Peng Fan71204e92015-05-15 07:29:12 +0800540struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
tremfac96402013-09-21 18:13:35 +0200541{
Peng Fan71204e92015-05-15 07:29:12 +0800542 return &mxc_i2c_buses[adap->hwadapnr];
Troy Kisky96c19bd2012-07-19 08:18:19 +0000543}
544
tremfac96402013-09-21 18:13:35 +0200545static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
546 uint addr, int alen, uint8_t *buffer,
547 int len)
Troy Kisky98153262012-07-19 08:18:20 +0000548{
tremfac96402013-09-21 18:13:35 +0200549 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
Troy Kisky98153262012-07-19 08:18:20 +0000550}
551
tremfac96402013-09-21 18:13:35 +0200552static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
553 uint addr, int alen, uint8_t *buffer,
554 int len)
Troy Kisky98153262012-07-19 08:18:20 +0000555{
tremfac96402013-09-21 18:13:35 +0200556 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000557}
558
Troy Kiskycfbb88d2012-07-19 08:18:08 +0000559/*
560 * Test if a chip at a given address responds (probe the chip)
561 */
tremfac96402013-09-21 18:13:35 +0200562static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
Troy Kiskycfbb88d2012-07-19 08:18:08 +0000563{
tremfac96402013-09-21 18:13:35 +0200564 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000565}
566
Peng Fan71204e92015-05-15 07:29:12 +0800567int __enable_i2c_clk(unsigned char enable, unsigned i2c_num)
Troy Kiskye4ff5252012-07-19 08:18:18 +0000568{
Peng Fan71204e92015-05-15 07:29:12 +0800569 return 1;
570}
571int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
572 __attribute__((weak, alias("__enable_i2c_clk")));
573
574void bus_i2c_init(int index, int speed, int unused,
575 int (*idle_bus_fn)(void *p), void *idle_bus_data)
576{
577 int ret;
578
579 if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
580 debug("Error i2c index\n");
Troy Kiskye4ff5252012-07-19 08:18:18 +0000581 return;
Troy Kiskye4ff5252012-07-19 08:18:18 +0000582 }
Peng Fan71204e92015-05-15 07:29:12 +0800583
584 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
585 mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
586
587 ret = enable_i2c_clk(1, index);
588 if (ret < 0) {
589 debug("I2C-%d clk fail to enable.\n", index);
590 return;
591 }
592
593 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000594}
595
596/*
597 * Init I2C Bus
598 */
tremfac96402013-09-21 18:13:35 +0200599static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
Troy Kiskye4ff5252012-07-19 08:18:18 +0000600{
Peng Fan71204e92015-05-15 07:29:12 +0800601 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000602}
603
604/*
605 * Set I2C Speed
606 */
Peng Fan71204e92015-05-15 07:29:12 +0800607static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
Troy Kiskye4ff5252012-07-19 08:18:18 +0000608{
tremfac96402013-09-21 18:13:35 +0200609 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000610}
611
612/*
tremfac96402013-09-21 18:13:35 +0200613 * Register mxc i2c adapters
Troy Kiskye4ff5252012-07-19 08:18:18 +0000614 */
tremfac96402013-09-21 18:13:35 +0200615U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
616 mxc_i2c_read, mxc_i2c_write,
617 mxc_i2c_set_bus_speed,
618 CONFIG_SYS_MXC_I2C1_SPEED,
619 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
620U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
621 mxc_i2c_read, mxc_i2c_write,
622 mxc_i2c_set_bus_speed,
623 CONFIG_SYS_MXC_I2C2_SPEED,
624 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
York Sunf8cb1012015-03-20 10:20:40 -0700625#ifdef CONFIG_SYS_I2C_MXC_I2C3
tremfac96402013-09-21 18:13:35 +0200626U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
627 mxc_i2c_read, mxc_i2c_write,
628 mxc_i2c_set_bus_speed,
629 CONFIG_SYS_MXC_I2C3_SPEED,
630 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
631#endif
Peng Fan71204e92015-05-15 07:29:12 +0800632
York Sunf8cb1012015-03-20 10:20:40 -0700633#ifdef CONFIG_SYS_I2C_MXC_I2C4
634U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
635 mxc_i2c_read, mxc_i2c_write,
636 mxc_i2c_set_bus_speed,
637 CONFIG_SYS_MXC_I2C4_SPEED,
638 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
639#endif
Peng Fan71204e92015-05-15 07:29:12 +0800640
641#else
642
643static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
644{
645 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
646
647 return bus_i2c_set_bus_speed(i2c_bus, speed);
648}
649
650static int mxc_i2c_probe(struct udevice *bus)
651{
652 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
653 fdt_addr_t addr;
654 int ret;
655
656 i2c_bus->driver_data = dev_get_driver_data(bus);
657
658 addr = dev_get_addr(bus);
659 if (addr == FDT_ADDR_T_NONE)
660 return -ENODEV;
661
662 i2c_bus->base = addr;
663 i2c_bus->index = bus->seq;
664
665 /* Enable clk */
666 ret = enable_i2c_clk(1, bus->seq);
667 if (ret < 0)
668 return ret;
669
670 ret = i2c_idle_bus(i2c_bus);
671 if (ret < 0) {
672 /* Disable clk */
673 enable_i2c_clk(0, bus->seq);
674 return ret;
675 }
676
677 /*
678 * Pinmux settings are in board file now, until pinmux is supported,
679 * we can set pinmux here in probe function.
680 */
681
682 debug("i2c : controller bus %d at %lu , speed %d: ",
683 bus->seq, i2c_bus->base,
684 i2c_bus->speed);
685
686 return 0;
687}
688
689static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
690 u32 chip_flags)
691{
692 int ret;
693 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
694
695 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
696 if (ret < 0) {
697 debug("%s failed, ret = %d\n", __func__, ret);
698 return ret;
699 }
700
701 i2c_imx_stop(i2c_bus);
702
703 return 0;
704}
705
706static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
707{
708 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
709 int ret = 0;
710 ulong base = i2c_bus->base;
711 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
712 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
713
714 /*
715 * Here the 3rd parameter addr and the 4th one alen are set to 0,
716 * because here we only want to send out chip address. The register
717 * address is wrapped in msg.
718 */
719 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, 0);
720 if (ret < 0) {
721 debug("i2c_init_transfer error: %d\n", ret);
722 return ret;
723 }
724
725 for (; nmsgs > 0; nmsgs--, msg++) {
726 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
727 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
728 if (msg->flags & I2C_M_RD)
729 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
730 msg->len);
731 else {
732 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
733 msg->len);
734 if (ret)
735 break;
736 if (next_is_read) {
737 /* Reuse ret */
738 ret = readb(base + (I2CR << reg_shift));
739 ret |= I2CR_RSTA;
740 writeb(ret, base + (I2CR << reg_shift));
741
742 ret = tx_byte(i2c_bus, (msg->addr << 1) | 1);
743 if (ret < 0) {
744 i2c_imx_stop(i2c_bus);
745 break;
746 }
747 }
748 }
749 }
750
751 if (ret)
752 debug("i2c_write: error sending\n");
753
754 i2c_imx_stop(i2c_bus);
755
756 return ret;
757}
758
759static const struct dm_i2c_ops mxc_i2c_ops = {
760 .xfer = mxc_i2c_xfer,
761 .probe_chip = mxc_i2c_probe_chip,
762 .set_bus_speed = mxc_i2c_set_bus_speed,
763};
764
765static const struct udevice_id mxc_i2c_ids[] = {
766 { .compatible = "fsl,imx21-i2c", },
767 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
768 {}
769};
770
771U_BOOT_DRIVER(i2c_mxc) = {
772 .name = "i2c_mxc",
773 .id = UCLASS_I2C,
774 .of_match = mxc_i2c_ids,
775 .probe = mxc_i2c_probe,
776 .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus),
777 .ops = &mxc_i2c_ops,
778};
779#endif