blob: 603d38143d188218ca656bbd9598af69de162f81 [file] [log] [blame]
Ian Campbell2c7e3b92014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Simon Glass53b5bf32016-09-12 23:18:39 -06003config SPL_GPIO_SUPPORT
4 default y
5
Hans de Goede44d8ae52015-04-06 20:33:34 +02006# Note only one of these may be selected at a time! But hidden choices are
7# not supported by Kconfig
8config SUNXI_GEN_SUN4I
9 bool
10 ---help---
11 Select this for sunxi SoCs which have resets and clocks set up
12 as the original A10 (mach-sun4i).
13
14config SUNXI_GEN_SUN6I
15 bool
16 ---help---
17 Select this for sunxi SoCs which have sun6i like periphery, like
18 separate ahb reset control registers, custom pmic bus, new style
19 watchdog, etc.
20
21
Ian Campbell2c7e3b92014-10-24 21:20:44 +010022choice
23 prompt "Sunxi SoC Variant"
Hans de Goede3da95362016-06-12 11:57:07 +020024 optional
Ian Campbell2c7e3b92014-10-24 21:20:44 +010025
Ian Campbellc3be2792014-10-24 21:20:45 +010026config MACH_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010027 bool "sun4i (Allwinner A10)"
28 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020029 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010030 select SUPPORT_SPL
31
Ian Campbellc3be2792014-10-24 21:20:45 +010032config MACH_SUN5I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010033 bool "sun5i (Allwinner A13)"
34 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020035 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010036 select SUPPORT_SPL
37
Ian Campbellc3be2792014-10-24 21:20:45 +010038config MACH_SUN6I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010039 bool "sun6i (Allwinner A31)"
40 select CPU_V7
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080041 select CPU_V7_HAS_NONSEC
42 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090043 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020044 select SUNXI_GEN_SUN6I
Hans de Goede8c2c9cf2014-10-25 20:18:10 +020045 select SUPPORT_SPL
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080046 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010047
Ian Campbellc3be2792014-10-24 21:20:45 +010048config MACH_SUN7I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010049 bool "sun7i (Allwinner A20)"
50 select CPU_V7
Hans de Goedeea624e12014-11-14 09:34:30 +010051 select CPU_V7_HAS_NONSEC
52 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090053 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020054 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010055 select SUPPORT_SPL
Hans de Goedeb366fb92014-10-24 20:12:04 +020056 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010057
Hans de Goede5e6bacd2015-04-06 20:55:39 +020058config MACH_SUN8I_A23
Ian Campbell2c7e3b92014-10-24 21:20:44 +010059 bool "sun8i (Allwinner A23)"
60 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080061 select CPU_V7_HAS_NONSEC
62 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090063 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020064 select SUNXI_GEN_SUN6I
Hans de Goede08fd1472014-12-07 14:34:27 +010065 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080066 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010067
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053068config MACH_SUN8I_A33
69 bool "sun8i (Allwinner A33)"
70 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080071 select CPU_V7_HAS_NONSEC
72 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090073 select ARCH_SUPPORT_PSCI
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053074 select SUNXI_GEN_SUN6I
75 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080076 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053077
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +080078config MACH_SUN8I_A83T
79 bool "sun8i (Allwinner A83T)"
80 select CPU_V7
81 select SUNXI_GEN_SUN6I
82 select SUPPORT_SPL
83
Jens Kuske1c27b7d2015-11-17 15:12:58 +010084config MACH_SUN8I_H3
85 bool "sun8i (Allwinner H3)"
86 select CPU_V7
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +080087 select CPU_V7_HAS_NONSEC
88 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090089 select ARCH_SUPPORT_PSCI
Jens Kuske1c27b7d2015-11-17 15:12:58 +010090 select SUNXI_GEN_SUN6I
Jens Kuske0404d532015-11-17 15:12:59 +010091 select SUPPORT_SPL
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +080092 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuske1c27b7d2015-11-17 15:12:58 +010093
Hans de Goede1871a8c2015-01-13 19:25:06 +010094config MACH_SUN9I
95 bool "sun9i (Allwinner A80)"
96 select CPU_V7
97 select SUNXI_GEN_SUN6I
98
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +080099config MACH_SUN50I
100 bool "sun50i (Allwinner A64)"
101 select ARM64
102 select SUNXI_GEN_SUN6I
103
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100104endchoice
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800105
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200106# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
107config MACH_SUN8I
108 bool
vishnupatekar762e24a2015-11-29 01:07:19 +0800109 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200110
Vishnu Patekarf5fd8ca2016-01-12 01:20:58 +0800111config DRAM_TYPE
112 int "sunxi dram type"
113 depends on MACH_SUN8I_A83T
114 default 3
115 ---help---
116 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200117
Hans de Goede37781a12014-11-15 19:46:39 +0100118config DRAM_CLK
Hans de Goede8ffc4872015-01-17 14:24:55 +0100119 int "sunxi dram clock speed"
120 default 312 if MACH_SUN6I || MACH_SUN8I
121 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +0100122 ---help---
123 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goedee1a08882015-01-25 11:29:27 +0100124 of 24.
Hans de Goede37781a12014-11-15 19:46:39 +0100125
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200126if MACH_SUN5I || MACH_SUN7I
127config DRAM_MBUS_CLK
128 int "sunxi mbus clock speed"
129 default 300
130 ---help---
131 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
132
133endif
134
Hans de Goede37781a12014-11-15 19:46:39 +0100135config DRAM_ZQ
Hans de Goede8ffc4872015-01-17 14:24:55 +0100136 int "sunxi dram zq value"
137 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
138 default 127 if MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +0100139 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100140 Set the dram zq value.
Hans de Goede37781a12014-11-15 19:46:39 +0100141
Hans de Goede8975cdf2015-05-13 15:00:46 +0200142config DRAM_ODT_EN
143 bool "sunxi dram odt enable"
144 default n if !MACH_SUN8I_A23
145 default y if MACH_SUN8I_A23
146 ---help---
147 Select this to enable dram odt (on die termination).
148
Hans de Goede8ffc4872015-01-17 14:24:55 +0100149if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
150config DRAM_EMR1
151 int "sunxi dram emr1 value"
152 default 0 if MACH_SUN4I
153 default 4 if MACH_SUN5I || MACH_SUN7I
154 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100155 Set the dram controller emr1 value.
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200156
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200157config DRAM_TPR3
158 hex "sunxi dram tpr3 value"
159 default 0
160 ---help---
161 Set the dram controller tpr3 parameter. This parameter configures
162 the delay on the command lane and also phase shifts, which are
163 applied for sampling incoming read data. The default value 0
164 means that no phase/delay adjustments are necessary. Properly
165 configuring this parameter increases reliability at high DRAM
166 clock speeds.
167
168config DRAM_DQS_GATING_DELAY
169 hex "sunxi dram dqs_gating_delay value"
170 default 0
171 ---help---
172 Set the dram controller dqs_gating_delay parmeter. Each byte
173 encodes the DQS gating delay for each byte lane. The delay
174 granularity is 1/4 cycle. For example, the value 0x05060606
175 means that the delay is 5 quarter-cycles for one lane (1.25
176 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
177 The default value 0 means autodetection. The results of hardware
178 autodetection are not very reliable and depend on the chip
179 temperature (sometimes producing different results on cold start
180 and warm reboot). But the accuracy of hardware autodetection
181 is usually good enough, unless running at really high DRAM
182 clocks speeds (up to 600MHz). If unsure, keep as 0.
183
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200184choice
185 prompt "sunxi dram timings"
186 default DRAM_TIMINGS_VENDOR_MAGIC
187 ---help---
188 Select the timings of the DDR3 chips.
189
190config DRAM_TIMINGS_VENDOR_MAGIC
191 bool "Magic vendor timings from Android"
192 ---help---
193 The same DRAM timings as in the Allwinner boot0 bootloader.
194
195config DRAM_TIMINGS_DDR3_1066F_1333H
196 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
197 ---help---
198 Use the timings of the standard JEDEC DDR3-1066F speed bin for
199 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
200 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
201 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
202 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
203 that down binning to DDR3-1066F is supported (because DDR3-1066F
204 uses a bit faster timings than DDR3-1333H).
205
206config DRAM_TIMINGS_DDR3_800E_1066G_1333J
207 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
208 ---help---
209 Use the timings of the slowest possible JEDEC speed bin for the
210 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
211 DDR3-800E, DDR3-1066G or DDR3-1333J.
212
213endchoice
214
Hans de Goede37781a12014-11-15 19:46:39 +0100215endif
216
Hans de Goede8975cdf2015-05-13 15:00:46 +0200217if MACH_SUN8I_A23
218config DRAM_ODT_CORRECTION
219 int "sunxi dram odt correction value"
220 default 0
221 ---help---
222 Set the dram odt correction value (range -255 - 255). In allwinner
223 fex files, this option is found in bits 8-15 of the u32 odt_en variable
224 in the [dram] section. When bit 31 of the odt_en variable is set
225 then the correction is negative. Usually the value for this is 0.
226endif
227
Iain Patone71b4222015-03-28 10:26:38 +0000228config SYS_CLK_FREQ
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200229 default 816000000 if MACH_SUN50I
Iain Patone71b4222015-03-28 10:26:38 +0000230 default 912000000 if MACH_SUN7I
231 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
232
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800233config SYS_CONFIG_NAME
Ian Campbellc3be2792014-10-24 21:20:45 +0100234 default "sun4i" if MACH_SUN4I
235 default "sun5i" if MACH_SUN5I
236 default "sun6i" if MACH_SUN6I
237 default "sun7i" if MACH_SUN7I
238 default "sun8i" if MACH_SUN8I
Hans de Goede1871a8c2015-01-13 19:25:06 +0100239 default "sun9i" if MACH_SUN9I
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200240 default "sun50i" if MACH_SUN50I
Hans de Goede6ae66f22014-08-01 09:28:24 +0200241
Masahiro Yamadadd840582014-07-30 14:08:14 +0900242config SYS_BOARD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900243 default "sunxi"
244
245config SYS_SOC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900246 default "sunxi"
247
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200248config UART0_PORT_F
249 bool "UART0 on MicroSD breakout board"
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200250 default n
251 ---help---
252 Repurpose the SD card slot for getting access to the UART0 serial
253 console. Primarily useful only for low level u-boot debugging on
254 tablets, where normal UART0 is difficult to access and requires
255 device disassembly and/or soldering. As the SD card can't be used
256 at the same time, the system can be only booted in the FEL mode.
257 Only enable this if you really know what you are doing.
258
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200259config OLD_SUNXI_KERNEL_COMPAT
Masahiro Yamadaab650062016-08-12 10:26:50 +0900260 bool "Enable workarounds for booting old kernels"
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200261 default n
262 ---help---
263 Set this to enable various workarounds for old kernels, this results in
264 sub-optimal settings for newer kernels, only enable if needed.
265
Maxime Ripard44c79872015-10-15 22:04:07 +0200266config MMC
267 depends on !UART0_PORT_F
268 default y if ARCH_SUNXI
269
Hans de Goedecd821132014-10-02 20:29:26 +0200270config MMC0_CD_PIN
271 string "Card detect pin for mmc0"
Chen-Yu Tsaiacdab172016-05-02 10:28:08 +0800272 default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
Hans de Goedecd821132014-10-02 20:29:26 +0200273 default ""
274 ---help---
275 Set the card detect pin for mmc0, leave empty to not use cd. This
276 takes a string in the format understood by sunxi_name_to_gpio, e.g.
277 PH1 for pin 1 of port H.
278
279config MMC1_CD_PIN
280 string "Card detect pin for mmc1"
281 default ""
282 ---help---
283 See MMC0_CD_PIN help text.
284
285config MMC2_CD_PIN
286 string "Card detect pin for mmc2"
287 default ""
288 ---help---
289 See MMC0_CD_PIN help text.
290
291config MMC3_CD_PIN
292 string "Card detect pin for mmc3"
293 default ""
294 ---help---
295 See MMC0_CD_PIN help text.
296
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100297config MMC1_PINS
298 string "Pins for mmc1"
299 default ""
300 ---help---
301 Set the pins used for mmc1, when applicable. This takes a string in the
302 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
303
304config MMC2_PINS
305 string "Pins for mmc2"
306 default ""
307 ---help---
308 See MMC1_PINS help text.
309
310config MMC3_PINS
311 string "Pins for mmc3"
312 default ""
313 ---help---
314 See MMC1_PINS help text.
315
Hans de Goede2ccfac02014-10-02 20:43:50 +0200316config MMC_SUNXI_SLOT_EXTRA
317 int "mmc extra slot number"
318 default -1
319 ---help---
320 sunxi builds always enable mmc0, some boards also have a second sdcard
321 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
322 support for this.
323
Hans de Goede2c3c3ec2016-04-01 22:39:26 +0200324config INITIAL_USB_SCAN_DELAY
325 int "delay initial usb scan by x ms to allow builtin devices to init"
326 default 0
327 ---help---
328 Some boards have on board usb devices which need longer than the
329 USB spec's 1 second to connect from board powerup. Set this config
330 option to a non 0 value to add an extra delay before the first usb
331 bus scan.
332
Hans de Goede4458b7a2015-01-07 15:26:06 +0100333config USB0_VBUS_PIN
334 string "Vbus enable pin for usb0 (otg)"
335 default ""
336 ---help---
337 Set the Vbus enable pin for usb0 (otg). This takes a string in the
338 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
339
Hans de Goede52defe82015-02-16 22:13:43 +0100340config USB0_VBUS_DET
341 string "Vbus detect pin for usb0 (otg)"
Hans de Goede52defe82015-02-16 22:13:43 +0100342 default ""
343 ---help---
344 Set the Vbus detect pin for usb0 (otg). This takes a string in the
345 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
346
Hans de Goede48c06c92015-06-14 17:29:53 +0200347config USB0_ID_DET
348 string "ID detect pin for usb0 (otg)"
349 default ""
350 ---help---
351 Set the ID detect pin for usb0 (otg). This takes a string in the
352 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
353
Hans de Goede115200c2014-11-07 16:09:00 +0100354config USB1_VBUS_PIN
355 string "Vbus enable pin for usb1 (ehci0)"
356 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100357 default "PH27" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100358 ---help---
359 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
360 a string in the format understood by sunxi_name_to_gpio, e.g.
361 PH1 for pin 1 of port H.
362
363config USB2_VBUS_PIN
364 string "Vbus enable pin for usb2 (ehci1)"
365 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100366 default "PH24" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100367 ---help---
368 See USB1_VBUS_PIN help text.
369
Hans de Goede60fa6302016-03-18 08:42:01 +0100370config USB3_VBUS_PIN
371 string "Vbus enable pin for usb3 (ehci2)"
372 default ""
373 ---help---
374 See USB1_VBUS_PIN help text.
375
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200376config I2C0_ENABLE
377 bool "Enable I2C/TWI controller 0"
378 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
379 default n if MACH_SUN6I || MACH_SUN8I
Hans de Goede0878a8a2016-05-15 13:51:58 +0200380 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200381 ---help---
382 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
383 its clock and setting up the bus. This is especially useful on devices
384 with slaves connected to the bus or with pins exposed through e.g. an
385 expansion port/header.
386
387config I2C1_ENABLE
388 bool "Enable I2C/TWI controller 1"
389 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200390 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200391 ---help---
392 See I2C0_ENABLE help text.
393
394config I2C2_ENABLE
395 bool "Enable I2C/TWI controller 2"
396 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200397 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200398 ---help---
399 See I2C0_ENABLE help text.
400
401if MACH_SUN6I || MACH_SUN7I
402config I2C3_ENABLE
403 bool "Enable I2C/TWI controller 3"
404 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200405 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200406 ---help---
407 See I2C0_ENABLE help text.
408endif
409
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100410if SUNXI_GEN_SUN6I
Jelle van der Waa9d082682016-01-14 14:06:26 +0100411config R_I2C_ENABLE
412 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100413 # This is used for the pmic on H3
414 default y if SY8106A_POWER
Hans de Goede0878a8a2016-05-15 13:51:58 +0200415 select CMD_I2C
Jelle van der Waa9d082682016-01-14 14:06:26 +0100416 ---help---
417 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100418endif
Jelle van der Waa9d082682016-01-14 14:06:26 +0100419
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200420if MACH_SUN7I
421config I2C4_ENABLE
422 bool "Enable I2C/TWI controller 4"
423 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200424 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200425 ---help---
426 See I2C0_ENABLE help text.
427endif
428
Hans de Goede2fcf0332015-04-25 17:25:14 +0200429config AXP_GPIO
Masahiro Yamadaab650062016-08-12 10:26:50 +0900430 bool "Enable support for gpio-s on axp PMICs"
Hans de Goede2fcf0332015-04-25 17:25:14 +0200431 default n
432 ---help---
433 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
434
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200435config VIDEO
Masahiro Yamadaab650062016-08-12 10:26:50 +0900436 bool "Enable graphical uboot console on HDMI, LCD or VGA"
Andre Przywarafa855d32016-09-05 01:32:40 +0100437 depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200438 default y
439 ---help---
Hans de Goede2dae8002014-12-21 16:28:32 +0100440 Say Y here to add support for using a cfb console on the HDMI, LCD
441 or VGA output found on most sunxi devices. See doc/README.video for
442 info on how to select the video output and mode.
443
Hans de Goede2fbf0912014-12-23 23:04:35 +0100444config VIDEO_HDMI
Masahiro Yamadaab650062016-08-12 10:26:50 +0900445 bool "HDMI output support"
Hans de Goede2fbf0912014-12-23 23:04:35 +0100446 depends on VIDEO && !MACH_SUN8I
447 default y
448 ---help---
449 Say Y here to add support for outputting video over HDMI.
450
Hans de Goeded9786d22014-12-25 13:58:06 +0100451config VIDEO_VGA
Masahiro Yamadaab650062016-08-12 10:26:50 +0900452 bool "VGA output support"
Hans de Goeded9786d22014-12-25 13:58:06 +0100453 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
454 default n
455 ---help---
456 Say Y here to add support for outputting video over VGA.
457
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100458config VIDEO_VGA_VIA_LCD
Masahiro Yamadaab650062016-08-12 10:26:50 +0900459 bool "VGA via LCD controller support"
Chen-Yu Tsai2583d5b2015-01-12 18:02:10 +0800460 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100461 default n
462 ---help---
463 Say Y here to add support for external DACs connected to the parallel
464 LCD interface driving a VGA connector, such as found on the
465 Olimex A13 boards.
466
Hans de Goedefb75d972015-01-25 15:33:07 +0100467config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
Masahiro Yamadaab650062016-08-12 10:26:50 +0900468 bool "Force sync active high for VGA via LCD controller support"
Hans de Goedefb75d972015-01-25 15:33:07 +0100469 depends on VIDEO_VGA_VIA_LCD
470 default n
471 ---help---
472 Say Y here if you've a board which uses opendrain drivers for the vga
473 hsync and vsync signals. Opendrain drivers cannot generate steep enough
474 positive edges for a stable video output, so on boards with opendrain
475 drivers the sync signals must always be active high.
476
Chen-Yu Tsai507e27d2015-01-12 18:02:11 +0800477config VIDEO_VGA_EXTERNAL_DAC_EN
478 string "LCD panel power enable pin"
479 depends on VIDEO_VGA_VIA_LCD
480 default ""
481 ---help---
482 Set the enable pin for the external VGA DAC. This takes a string in the
483 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
484
Hans de Goede39920c82015-08-03 19:20:26 +0200485config VIDEO_COMPOSITE
Masahiro Yamadaab650062016-08-12 10:26:50 +0900486 bool "Composite video output support"
Hans de Goede39920c82015-08-03 19:20:26 +0200487 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
488 default n
489 ---help---
490 Say Y here to add support for outputting composite video.
491
Hans de Goede2dae8002014-12-21 16:28:32 +0100492config VIDEO_LCD_MODE
493 string "LCD panel timing details"
494 depends on VIDEO
495 default ""
496 ---help---
497 LCD panel timing details string, leave empty if there is no LCD panel.
498 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
499 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede8addd3e2015-08-16 11:23:42 +0200500 Also see: http://linux-sunxi.org/LCD
Hans de Goede2dae8002014-12-21 16:28:32 +0100501
Hans de Goede65150322015-01-13 13:21:46 +0100502config VIDEO_LCD_DCLK_PHASE
503 int "LCD panel display clock phase"
504 depends on VIDEO
505 default 1
506 ---help---
507 Select LCD panel display clock phase shift, range 0-3.
508
Hans de Goede2dae8002014-12-21 16:28:32 +0100509config VIDEO_LCD_POWER
510 string "LCD panel power enable pin"
511 depends on VIDEO
512 default ""
513 ---help---
514 Set the power enable pin for the LCD panel. This takes a string in the
515 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
516
Hans de Goede242e3d82015-02-16 17:26:41 +0100517config VIDEO_LCD_RESET
518 string "LCD panel reset pin"
519 depends on VIDEO
520 default ""
521 ---help---
522 Set the reset pin for the LCD panel. This takes a string in the format
523 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
524
Hans de Goede2dae8002014-12-21 16:28:32 +0100525config VIDEO_LCD_BL_EN
526 string "LCD panel backlight enable pin"
527 depends on VIDEO
528 default ""
529 ---help---
530 Set the backlight enable pin for the LCD panel. This takes a string in the
531 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
532 port H.
533
534config VIDEO_LCD_BL_PWM
535 string "LCD panel backlight pwm pin"
536 depends on VIDEO
537 default ""
538 ---help---
539 Set the backlight pwm pin for the LCD panel. This takes a string in the
540 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200541
Hans de Goedea7403ae2015-01-22 21:02:42 +0100542config VIDEO_LCD_BL_PWM_ACTIVE_LOW
543 bool "LCD panel backlight pwm is inverted"
544 depends on VIDEO
545 default y
546 ---help---
547 Set this if the backlight pwm output is active low.
548
Hans de Goede55410082015-02-16 17:23:25 +0100549config VIDEO_LCD_PANEL_I2C
550 bool "LCD panel needs to be configured via i2c"
551 depends on VIDEO
Hans de Goede1fc42012015-03-07 12:00:02 +0100552 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200553 select CMD_I2C
Hans de Goede55410082015-02-16 17:23:25 +0100554 ---help---
555 Say y here if the LCD panel needs to be configured via i2c. This
556 will add a bitbang i2c controller using gpios to talk to the LCD.
557
558config VIDEO_LCD_PANEL_I2C_SDA
559 string "LCD panel i2c interface SDA pin"
560 depends on VIDEO_LCD_PANEL_I2C
561 default "PG12"
562 ---help---
563 Set the SDA pin for the LCD i2c interface. This takes a string in the
564 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
565
566config VIDEO_LCD_PANEL_I2C_SCL
567 string "LCD panel i2c interface SCL pin"
568 depends on VIDEO_LCD_PANEL_I2C
569 default "PG10"
570 ---help---
571 Set the SCL pin for the LCD i2c interface. This takes a string in the
572 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
573
Hans de Goede213480e2015-01-01 22:04:34 +0100574
575# Note only one of these may be selected at a time! But hidden choices are
576# not supported by Kconfig
577config VIDEO_LCD_IF_PARALLEL
578 bool
579
580config VIDEO_LCD_IF_LVDS
581 bool
582
583
584choice
585 prompt "LCD panel support"
586 depends on VIDEO
587 ---help---
588 Select which type of LCD panel to support.
589
590config VIDEO_LCD_PANEL_PARALLEL
591 bool "Generic parallel interface LCD panel"
592 select VIDEO_LCD_IF_PARALLEL
593
594config VIDEO_LCD_PANEL_LVDS
595 bool "Generic lvds interface LCD panel"
596 select VIDEO_LCD_IF_LVDS
597
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200598config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
599 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
600 select VIDEO_LCD_SSD2828
601 select VIDEO_LCD_IF_PARALLEL
602 ---help---
Hans de Goedec1cfd512015-08-08 16:13:53 +0200603 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
604
605config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
606 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
607 select VIDEO_LCD_ANX9804
608 select VIDEO_LCD_IF_PARALLEL
609 select VIDEO_LCD_PANEL_I2C
610 ---help---
611 Select this for eDP LCD panels with 4 lanes running at 1.62G,
612 connected via an ANX9804 bridge chip.
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200613
Hans de Goede27515b22015-01-20 09:23:36 +0100614config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
615 bool "Hitachi tx18d42vm LCD panel"
616 select VIDEO_LCD_HITACHI_TX18D42VM
617 select VIDEO_LCD_IF_LVDS
618 ---help---
619 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
620
Hans de Goedeaad2ac22015-02-16 17:49:47 +0100621config VIDEO_LCD_TL059WV5C0
622 bool "tl059wv5c0 LCD panel"
623 select VIDEO_LCD_PANEL_I2C
624 select VIDEO_LCD_IF_PARALLEL
625 ---help---
626 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
627 Aigo M60/M608/M606 tablets.
628
Hans de Goede213480e2015-01-01 22:04:34 +0100629endchoice
630
631
Hans de Goedec13f60d2015-01-25 12:10:48 +0100632config GMAC_TX_DELAY
633 int "GMAC Transmit Clock Delay Chain"
634 default 0
635 ---help---
636 Set the GMAC Transmit Clock Delay Chain value.
637
Hans de Goedeff42d102015-09-13 13:02:48 +0200638config SPL_STACK_R_ADDR
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200639 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
Hans de Goedeff42d102015-09-13 13:02:48 +0200640 default 0x2fe00000 if MACH_SUN9I
641
Masahiro Yamadadd840582014-07-30 14:08:14 +0900642endif