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08415652005-08-09 14:52:00 +02001/*
2 * (C) Copyright 2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
32#define CONFIG_MPC5200
33#define CONFIG_O2DNT 1 /* ... on O2DNT board */
34
Wolfgang Denk2ae18242010-10-06 09:05:45 +020035#define CONFIG_SYS_TEXT_BASE 0xFF000000 /* boot low for 16 MiB boards */
36
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
08415652005-08-09 14:52:00 +020038
Becky Bruce31d82672008-05-08 19:02:12 -050039#define CONFIG_HIGH_BATS 1 /* High BATs supported */
40
08415652005-08-09 14:52:00 +020041/*
42 * Serial console configuration
43 */
44#define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */
45#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
08415652005-08-09 14:52:00 +020047
48/*
49 * PCI Mapping:
50 * 0x40000000 - 0x4fffffff - PCI Memory
51 * 0x50000000 - 0x50ffffff - PCI IO Space
52 */
53#define CONFIG_PCI 1
54#define CONFIG_PCI_PNP 1
30eb1772005-08-16 20:39:05 +020055/* #define CONFIG_PCI_SCAN_SHOW 1 */
TsiChung Liewf33fca22008-03-30 01:19:06 -050056#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
08415652005-08-09 14:52:00 +020057
58#define CONFIG_PCI_MEM_BUS 0x40000000
59#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
60#define CONFIG_PCI_MEM_SIZE 0x10000000
61
62#define CONFIG_PCI_IO_BUS 0x50000000
63#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
64#define CONFIG_PCI_IO_SIZE 0x01000000
65
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_XLB_PIPELINING 1
08415652005-08-09 14:52:00 +020067
68#define CONFIG_NET_MULTI 1
Marian Balakowicz63ff0042005-10-28 22:30:33 +020069#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
08415652005-08-09 14:52:00 +020071#define CONFIG_NS8382X 1
72
08415652005-08-09 14:52:00 +020073/* Partitions */
74#define CONFIG_MAC_PARTITION
75#define CONFIG_DOS_PARTITION
76#define CONFIG_ISO_PARTITION
77
78#define CONFIG_TIMESTAMP /* Print image info with timestamp */
79
08415652005-08-09 14:52:00 +020080
Jon Loeligera5cb2302007-07-04 22:33:13 -050081/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050082 * BOOTP options
83 */
84#define CONFIG_BOOTP_BOOTFILESIZE
85#define CONFIG_BOOTP_BOOTPATH
86#define CONFIG_BOOTP_GATEWAY
87#define CONFIG_BOOTP_HOSTNAME
88
89
90/*
Jon Loeligera5cb2302007-07-04 22:33:13 -050091 * Command line configuration.
92 */
93#include <config_cmd_default.h>
94
95#define CONFIG_CMD_EEPROM
96#define CONFIG_CMD_FAT
97#define CONFIG_CMD_I2C
98#define CONFIG_CMD_NFS
99#define CONFIG_CMD_MII
100#define CONFIG_CMD_PING
Jon Loeliger7f5c0152007-07-10 09:38:02 -0500101#define CONFIG_CMD_PCI
Jon Loeligera5cb2302007-07-04 22:33:13 -0500102
08415652005-08-09 14:52:00 +0200103
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200104#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105# define CONFIG_SYS_LOWBOOT 1
08415652005-08-09 14:52:00 +0200106#else
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200107# error "CONFIG_SYS_TEXT_BASE must be 0xFF000000"
08415652005-08-09 14:52:00 +0200108#endif
109
110/*
111 * Autobooting
112 */
113#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
114
115#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100116 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
08415652005-08-09 14:52:00 +0200117 "echo"
118
119#undef CONFIG_BOOTARGS
120
121#define CONFIG_EXTRA_ENV_SETTINGS \
122 "netdev=eth0\0" \
123 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100124 "nfsroot=${serverip}:${rootpath}\0" \
08415652005-08-09 14:52:00 +0200125 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100126 "addip=setenv bootargs ${bootargs} " \
127 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
128 ":${hostname}:${netdev}:off panic=1\0" \
08415652005-08-09 14:52:00 +0200129 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100130 "bootm ${kernel_addr}\0" \
08415652005-08-09 14:52:00 +0200131 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100132 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
133 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
08415652005-08-09 14:52:00 +0200134 "rootpath=/opt/eldk/ppc_82xx\0" \
135 "bootfile=/tftpboot/MPC5200/uImage\0" \
136 ""
137
138#define CONFIG_BOOTCOMMAND "run flash_self"
139
08415652005-08-09 14:52:00 +0200140/*
141 * IPB Bus clocking configuration.
142 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Marian Balakowicz0a69b262005-11-27 20:15:41 +0100144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
Marian Balakowicz0a69b262005-11-27 20:15:41 +0100146/*
147 * PCI Bus clocking configuration
148 *
149 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200151 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
Marian Balakowicz0a69b262005-11-27 20:15:41 +0100152 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
08415652005-08-09 14:52:00 +0200154#endif
Marian Balakowicz0a69b262005-11-27 20:15:41 +0100155
08415652005-08-09 14:52:00 +0200156/*
157 * I2C configuration
158 */
159#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
08415652005-08-09 14:52:00 +0200161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
163#define CONFIG_SYS_I2C_SLAVE 0x7F
08415652005-08-09 14:52:00 +0200164
165/*
5a27f842005-08-11 15:56:59 +0200166 * EEPROM configuration:
167 *
168 * O2DNT board is equiped with Ramtron FRAM device FM24CL16
169 * 16 Kib Ferroelectric Nonvolatile serial RAM memory
170 * organized as 2048 x 8 bits and addressable as eight I2C devices
171 * 0x50 ... 0x57 each 256 bytes in size
172 *
08415652005-08-09 14:52:00 +0200173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_I2C_FRAM
175#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
176#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
177#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
5a27f842005-08-11 15:56:59 +0200178/*
179 * There is no write delay with FRAM, write operations are performed at bus
180 * speed. Thus, no status polling or write delay is needed.
181 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182/*#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70*/
5a27f842005-08-11 15:56:59 +0200183
08415652005-08-09 14:52:00 +0200184
185/*
186 * Flash configuration
187 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_FLASH_BASE 0xFF000000
189#define CONFIG_SYS_FLASH_SIZE 0x01000000
190#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
08415652005-08-09 14:52:00 +0200191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
193#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
08415652005-08-09 14:52:00 +0200194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
196#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
197#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
198#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
08415652005-08-09 14:52:00 +0200199
200/*
201 * Environment settings
202 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200203#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200204#define CONFIG_ENV_SIZE 0x20000
205#define CONFIG_ENV_SECT_SIZE 0x20000
08415652005-08-09 14:52:00 +0200206#define CONFIG_ENV_OVERWRITE 1
207
208/*
209 * Memory map
210 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_MBAR 0xF0000000
212#define CONFIG_SYS_SDRAM_BASE 0x00000000
213#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
08415652005-08-09 14:52:00 +0200214
215/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
217#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
08415652005-08-09 14:52:00 +0200218
219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
221#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
222#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
08415652005-08-09 14:52:00 +0200223
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200224#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
226#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
227#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
08415652005-08-09 14:52:00 +0200228
229/*
230 * Ethernet configuration
231 */
232#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800233#define CONFIG_MPC5xxx_FEC_MII100
08415652005-08-09 14:52:00 +0200234/*
Ben Warren86321fc2009-02-05 23:58:25 -0800235 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
08415652005-08-09 14:52:00 +0200236 */
Ben Warren86321fc2009-02-05 23:58:25 -0800237/* #define CONFIG_MPC5xxx_FEC_MII10 */
08415652005-08-09 14:52:00 +0200238#define CONFIG_PHY_ADDR 0x00
239
240/*
241 * GPIO configuration
242 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243/*#define CONFIG_SYS_GPS_PORT_CONFIG 0x10002004 */
244#define CONFIG_SYS_GPS_PORT_CONFIG 0x00002006 /* no CAN */
08415652005-08-09 14:52:00 +0200245
246/*
247 * Miscellaneous configurable options
248 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_LONGHELP /* undef to save memory */
250#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
08415652005-08-09 14:52:00 +0200251
Jon Loeligera5cb2302007-07-04 22:33:13 -0500252#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
08415652005-08-09 14:52:00 +0200254#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
08415652005-08-09 14:52:00 +0200256#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
258#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
259#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
08415652005-08-09 14:52:00 +0200260
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
262#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
08415652005-08-09 14:52:00 +0200263
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
08415652005-08-09 14:52:00 +0200265
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
08415652005-08-09 14:52:00 +0200267
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeligera5cb2302007-07-04 22:33:13 -0500269#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligera5cb2302007-07-04 22:33:13 -0500271#endif
272
08415652005-08-09 14:52:00 +0200273/*
274 * Various low-level settings
275 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
277#define CONFIG_SYS_HID0_FINAL HID0_ICE
08415652005-08-09 14:52:00 +0200278
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
280#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
Marian Balakowicz0a69b262005-11-27 20:15:41 +0100281
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100283/*
Marian Balakowicz0a69b262005-11-27 20:15:41 +0100284 * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
285 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_BOOTCS_CFG 0x00057801 /* for pci_clk = 66 MHz */
Marian Balakowicz0a69b262005-11-27 20:15:41 +0100287#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_BOOTCS_CFG 0x00047801 /* for pci_clk = 33 MHz */
Marian Balakowicz0a69b262005-11-27 20:15:41 +0100289#endif
290
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
292#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
08415652005-08-09 14:52:00 +0200293
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_CS_BURST 0x00000000
295#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
08415652005-08-09 14:52:00 +0200296
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_RESET_ADDRESS 0xff000000
08415652005-08-09 14:52:00 +0200298
299#endif /* __CONFIG_H */