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08415652005-08-09 14:52:00 +02001/*
2 * (C) Copyright 2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
32#define CONFIG_MPC5200
33#define CONFIG_O2DNT 1 /* ... on O2DNT board */
34
35#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
36
37#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
38#define BOOTFLAG_WARM 0x02 /* Software reboot */
39
08415652005-08-09 14:52:00 +020040/*
41 * Serial console configuration
42 */
43#define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */
44#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
45#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
46
47/*
48 * PCI Mapping:
49 * 0x40000000 - 0x4fffffff - PCI Memory
50 * 0x50000000 - 0x50ffffff - PCI IO Space
51 */
52#define CONFIG_PCI 1
53#define CONFIG_PCI_PNP 1
30eb1772005-08-16 20:39:05 +020054/* #define CONFIG_PCI_SCAN_SHOW 1 */
08415652005-08-09 14:52:00 +020055
56#define CONFIG_PCI_MEM_BUS 0x40000000
57#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
58#define CONFIG_PCI_MEM_SIZE 0x10000000
59
60#define CONFIG_PCI_IO_BUS 0x50000000
61#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
62#define CONFIG_PCI_IO_SIZE 0x01000000
63
64#define CFG_XLB_PIPELINING 1
65
66#define CONFIG_NET_MULTI 1
Marian Balakowicz63ff0042005-10-28 22:30:33 +020067#define CONFIG_EEPRO100
08415652005-08-09 14:52:00 +020068#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
69#define CONFIG_NS8382X 1
70
08415652005-08-09 14:52:00 +020071/* Partitions */
72#define CONFIG_MAC_PARTITION
73#define CONFIG_DOS_PARTITION
74#define CONFIG_ISO_PARTITION
75
76#define CONFIG_TIMESTAMP /* Print image info with timestamp */
77
08415652005-08-09 14:52:00 +020078
Jon Loeligera5cb2302007-07-04 22:33:13 -050079/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050080 * BOOTP options
81 */
82#define CONFIG_BOOTP_BOOTFILESIZE
83#define CONFIG_BOOTP_BOOTPATH
84#define CONFIG_BOOTP_GATEWAY
85#define CONFIG_BOOTP_HOSTNAME
86
87
88/*
Jon Loeligera5cb2302007-07-04 22:33:13 -050089 * Command line configuration.
90 */
91#include <config_cmd_default.h>
92
93#define CONFIG_CMD_EEPROM
94#define CONFIG_CMD_FAT
95#define CONFIG_CMD_I2C
96#define CONFIG_CMD_NFS
97#define CONFIG_CMD_MII
98#define CONFIG_CMD_PING
Jon Loeliger7f5c0152007-07-10 09:38:02 -050099#define CONFIG_CMD_PCI
Jon Loeligera5cb2302007-07-04 22:33:13 -0500100
08415652005-08-09 14:52:00 +0200101
102#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
103# define CFG_LOWBOOT 1
104#else
105# error "TEXT_BASE must be 0xFF000000"
106#endif
107
108/*
109 * Autobooting
110 */
111#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
112
113#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100114 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
08415652005-08-09 14:52:00 +0200115 "echo"
116
117#undef CONFIG_BOOTARGS
118
119#define CONFIG_EXTRA_ENV_SETTINGS \
120 "netdev=eth0\0" \
121 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100122 "nfsroot=${serverip}:${rootpath}\0" \
08415652005-08-09 14:52:00 +0200123 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100124 "addip=setenv bootargs ${bootargs} " \
125 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
126 ":${hostname}:${netdev}:off panic=1\0" \
08415652005-08-09 14:52:00 +0200127 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100128 "bootm ${kernel_addr}\0" \
08415652005-08-09 14:52:00 +0200129 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100130 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
131 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
08415652005-08-09 14:52:00 +0200132 "rootpath=/opt/eldk/ppc_82xx\0" \
133 "bootfile=/tftpboot/MPC5200/uImage\0" \
134 ""
135
136#define CONFIG_BOOTCOMMAND "run flash_self"
137
138#if defined(CONFIG_MPC5200)
139/*
140 * IPB Bus clocking configuration.
141 */
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200142#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Marian Balakowicz0a69b262005-11-27 20:15:41 +0100143
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200144#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
Marian Balakowicz0a69b262005-11-27 20:15:41 +0100145/*
146 * PCI Bus clocking configuration
147 *
148 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200149 * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
150 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
Marian Balakowicz0a69b262005-11-27 20:15:41 +0100151 */
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200152#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
08415652005-08-09 14:52:00 +0200153#endif
Marian Balakowicz0a69b262005-11-27 20:15:41 +0100154#endif
155
08415652005-08-09 14:52:00 +0200156/*
157 * I2C configuration
158 */
159#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
160#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */
161
162#define CFG_I2C_SPEED 100000 /* 100 kHz */
163#define CFG_I2C_SLAVE 0x7F
164
165/*
5a27f842005-08-11 15:56:59 +0200166 * EEPROM configuration:
167 *
168 * O2DNT board is equiped with Ramtron FRAM device FM24CL16
169 * 16 Kib Ferroelectric Nonvolatile serial RAM memory
170 * organized as 2048 x 8 bits and addressable as eight I2C devices
171 * 0x50 ... 0x57 each 256 bytes in size
172 *
08415652005-08-09 14:52:00 +0200173 */
d4f5c722005-08-12 21:16:13 +0200174#define CFG_I2C_FRAM
08415652005-08-09 14:52:00 +0200175#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
176#define CFG_I2C_EEPROM_ADDR_LEN 1
177#define CFG_EEPROM_PAGE_WRITE_BITS 3
5a27f842005-08-11 15:56:59 +0200178/*
179 * There is no write delay with FRAM, write operations are performed at bus
180 * speed. Thus, no status polling or write delay is needed.
181 */
182/*#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70*/
183
08415652005-08-09 14:52:00 +0200184
185/*
186 * Flash configuration
187 */
188#define CFG_FLASH_BASE 0xFF000000
189#define CFG_FLASH_SIZE 0x01000000
190#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
191
192#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
193#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
194
195#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
196#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
adac3762005-08-11 10:10:30 +0200197#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
198#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
08415652005-08-09 14:52:00 +0200199
200/*
201 * Environment settings
202 */
203#define CFG_ENV_IS_IN_FLASH 1
204#define CFG_ENV_SIZE 0x20000
205#define CFG_ENV_SECT_SIZE 0x20000
206#define CONFIG_ENV_OVERWRITE 1
207
208/*
209 * Memory map
210 */
211#define CFG_MBAR 0xF0000000
212#define CFG_SDRAM_BASE 0x00000000
213#define CFG_DEFAULT_MBAR 0x80000000
214
215/* Use SRAM until RAM will be available */
216#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
217#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
218
219
220#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
221#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
222#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
223
224#define CFG_MONITOR_BASE TEXT_BASE
225#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
226#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
227#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
228
229/*
230 * Ethernet configuration
231 */
232#define CONFIG_MPC5xxx_FEC 1
233/*
234 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
235 */
236/* #define CONFIG_FEC_10MBIT 1 */
237#define CONFIG_PHY_ADDR 0x00
238
239/*
240 * GPIO configuration
241 */
Wolfgang Denk6617aae2005-08-19 00:46:54 +0200242/*#define CFG_GPS_PORT_CONFIG 0x10002004 */
Marian Balakowicz3a7b1422005-12-06 20:33:07 +0100243#define CFG_GPS_PORT_CONFIG 0x00002006 /* no CAN */
08415652005-08-09 14:52:00 +0200244
245/*
246 * Miscellaneous configurable options
247 */
248#define CFG_LONGHELP /* undef to save memory */
249#define CFG_PROMPT "=> " /* Monitor Command Prompt */
250
Jon Loeligera5cb2302007-07-04 22:33:13 -0500251#if defined(CONFIG_CMD_KGDB)
08415652005-08-09 14:52:00 +0200252#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
253#else
254#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
255#endif
256#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
257#define CFG_MAXARGS 16 /* max number of command args */
258#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
259
260#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
261#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
262
263#define CFG_LOAD_ADDR 0x100000 /* default load address */
264
265#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
266
Jon Loeligera5cb2302007-07-04 22:33:13 -0500267#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
268#if defined(CONFIG_CMD_KGDB)
269# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
270#endif
271
08415652005-08-09 14:52:00 +0200272/*
273 * Various low-level settings
274 */
275#if defined(CONFIG_MPC5200)
276#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
277#define CFG_HID0_FINAL HID0_ICE
278#else
279#define CFG_HID0_INIT 0
280#define CFG_HID0_FINAL 0
281#endif
282
283#define CFG_BOOTCS_START CFG_FLASH_BASE
284#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
Marian Balakowicz0a69b262005-11-27 20:15:41 +0100285
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200286#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100287/*
Marian Balakowicz0a69b262005-11-27 20:15:41 +0100288 * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
289 */
290#define CFG_BOOTCS_CFG 0x00057801 /* for pci_clk = 66 MHz */
291#else
292#define CFG_BOOTCS_CFG 0x00047801 /* for pci_clk = 33 MHz */
293#endif
294
08415652005-08-09 14:52:00 +0200295#define CFG_CS0_START CFG_FLASH_BASE
296#define CFG_CS0_SIZE CFG_FLASH_SIZE
297
298#define CFG_CS_BURST 0x00000000
299#define CFG_CS_DEADCYCLE 0x33333333
300
301#define CFG_RESET_ADDRESS 0xff000000
302
303#endif /* __CONFIG_H */