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wdenkd4ca31c2004-01-02 14:00:00 +00001/*
Wolfgang Denk7c803be2008-09-16 18:02:19 +02002 * (C) Copyright 2000-2008
wdenkd4ca31c2004-01-02 14:00:00 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkd4ca31c2004-01-02 14:00:00 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
21#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
22
Wolfgang Denk2ae18242010-10-06 09:05:45 +020023#define CONFIG_SYS_TEXT_BASE 0x40000000
24
wdenk66ca92a2004-09-28 17:59:53 +000025#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020026#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
27#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
wdenk66ca92a2004-09-28 17:59:53 +000028#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
wdenkc178d3d2004-01-24 20:25:54 +000029 /* (it will be used if there is no */
30 /* 'cpuclk' variable with valid value) */
wdenkd4ca31c2004-01-02 14:00:00 +000031
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032#undef CONFIG_SYS_MEASURE_CPUCLK /* Measure real cpu clock */
wdenk75d1ea72004-01-31 20:06:54 +000033 /* (function measure_gclk() */
34 /* will be called) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035#ifdef CONFIG_SYS_MEASURE_CPUCLK
36#define CONFIG_SYS_8XX_XIN 10000000 /* measure_gclk() needs this */
wdenk75d1ea72004-01-31 20:06:54 +000037#endif
38
wdenkc178d3d2004-01-24 20:25:54 +000039#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020040#define CONFIG_SYS_SMC_RXBUFLEN 128
41#define CONFIG_SYS_MAXIDLE 10
wdenkd4ca31c2004-01-02 14:00:00 +000042#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
43
wdenkc178d3d2004-01-24 20:25:54 +000044#define CONFIG_BOOTCOUNT_LIMIT
wdenkd4ca31c2004-01-02 14:00:00 +000045
46#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
47
48#define CONFIG_BOARD_TYPES 1 /* support board types */
49
wdenkc178d3d2004-01-24 20:25:54 +000050#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010051 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkd4ca31c2004-01-02 14:00:00 +000052 "echo"
53
54#undef CONFIG_BOOTARGS
55
wdenkc178d3d2004-01-24 20:25:54 +000056#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkd4ca31c2004-01-02 14:00:00 +000057 "netdev=eth0\0" \
58 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010059 "nfsroot=${serverip}:${rootpath}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000060 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010061 "addip=setenv bootargs ${bootargs} " \
62 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
63 ":${hostname}:${netdev}:off panic=1\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000064 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010065 "bootm ${kernel_addr}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000066 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010067 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
68 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000069 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020070 "hostname=TQM866M\0" \
71 "bootfile=TQM866M/uImage\0" \
Martin Krause9ef57bb2007-09-26 17:55:55 +020072 "fdt_addr=400C0000\0" \
73 "kernel_addr=40100000\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020074 "ramdisk_addr=40280000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020075 "u-boot=TQM866M/u-image.bin\0" \
Martin Krause9ef57bb2007-09-26 17:55:55 +020076 "load=tftp 200000 ${u-boot}\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020077 "update=prot off 40000000 +${filesize};" \
78 "era 40000000 +${filesize};" \
Martin Krause9ef57bb2007-09-26 17:55:55 +020079 "cp.b 200000 40000000 ${filesize};" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020080 "sete filesize;save\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000081 ""
82#define CONFIG_BOOTCOMMAND "run flash_self"
83
84#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkd4ca31c2004-01-02 14:00:00 +000086
87#undef CONFIG_WATCHDOG /* watchdog disabled */
88
wdenkc178d3d2004-01-24 20:25:54 +000089#define CONFIG_STATUS_LED 1 /* Status LED enabled */
wdenkd4ca31c2004-01-02 14:00:00 +000090
91#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
92
93/* enable I2C and select the hardware/software driver */
Heiko Schocherea818db2013-01-29 08:53:15 +010094#define CONFIG_SYS_I2C
95#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
96#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
97#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
wdenkd4ca31c2004-01-02 14:00:00 +000098
wdenkd4ca31c2004-01-02 14:00:00 +000099/*
100 * Software (bit-bang) I2C driver configuration
101 */
102#define PB_SCL 0x00000020 /* PB 26 */
103#define PB_SDA 0x00000010 /* PB 27 */
104
105#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
106#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
107#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
108#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
109#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
wdenkc178d3d2004-01-24 20:25:54 +0000110 else immr->im_cpm.cp_pbdat &= ~PB_SDA
wdenkd4ca31c2004-01-02 14:00:00 +0000111#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
wdenkc178d3d2004-01-24 20:25:54 +0000112 else immr->im_cpm.cp_pbdat &= ~PB_SCL
wdenkd4ca31c2004-01-02 14:00:00 +0000113#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
wdenkd4ca31c2004-01-02 14:00:00 +0000114
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */
116#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
117#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
118#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkd4ca31c2004-01-02 14:00:00 +0000119
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500120/*
121 * BOOTP options
122 */
123#define CONFIG_BOOTP_SUBNETMASK
124#define CONFIG_BOOTP_GATEWAY
125#define CONFIG_BOOTP_HOSTNAME
126#define CONFIG_BOOTP_BOOTPATH
127#define CONFIG_BOOTP_BOOTFILESIZE
128
wdenkd4ca31c2004-01-02 14:00:00 +0000129
130#define CONFIG_MAC_PARTITION
131#define CONFIG_DOS_PARTITION
132
wdenka6cccae2004-02-06 21:48:22 +0000133#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
134
135#define CONFIG_TIMESTAMP /* but print image timestmps */
wdenkd4ca31c2004-01-02 14:00:00 +0000136
wdenkd4ca31c2004-01-02 14:00:00 +0000137
Jon Loeliger26946902007-07-04 22:30:50 -0500138/*
139 * Command line configuration.
140 */
141#include <config_cmd_default.h>
142
143#define CONFIG_CMD_ASKENV
144#define CONFIG_CMD_DHCP
145#define CONFIG_CMD_EEPROM
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200146#define CONFIG_CMD_ELF
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100147#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500148#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200149#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500150#define CONFIG_CMD_NFS
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200151#define CONFIG_CMD_SNTP
152
153
154#define CONFIG_NETCONSOLE
Jon Loeliger26946902007-07-04 22:30:50 -0500155
wdenkd4ca31c2004-01-02 14:00:00 +0000156
157/*
158 * Miscellaneous configurable options
159 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_LONGHELP /* undef to save memory */
161#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenkd4ca31c2004-01-02 14:00:00 +0000162
Wolfgang Denk2751a952006-10-28 02:29:14 +0200163#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
wdenkd4ca31c2004-01-02 14:00:00 +0000165
Jon Loeliger26946902007-07-04 22:30:50 -0500166#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkd4ca31c2004-01-02 14:00:00 +0000168#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkd4ca31c2004-01-02 14:00:00 +0000170#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
172#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
173#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkd4ca31c2004-01-02 14:00:00 +0000174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
176#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkd4ca31c2004-01-02 14:00:00 +0000177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkd4ca31c2004-01-02 14:00:00 +0000179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkd4ca31c2004-01-02 14:00:00 +0000181
wdenkd4ca31c2004-01-02 14:00:00 +0000182/*
183 * Low Level Configuration Settings
184 * (address mappings, register initial values, etc.)
185 * You should know what you are doing if you make changes here.
186 */
187/*-----------------------------------------------------------------------
188 * Internal Memory Mapped Register
189 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_IMMR 0xFFF00000
wdenkd4ca31c2004-01-02 14:00:00 +0000191
192/*-----------------------------------------------------------------------
193 * Definitions for initial stack pointer and data area (in DPRAM)
194 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200196#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200197#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkd4ca31c2004-01-02 14:00:00 +0000199
200/*-----------------------------------------------------------------------
201 * Start addresses for the final memory configuration
202 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkd4ca31c2004-01-02 14:00:00 +0000204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_SDRAM_BASE 0x00000000
206#define CONFIG_SYS_FLASH_BASE 0x40000000
207#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
208#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
209#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
wdenkd4ca31c2004-01-02 14:00:00 +0000210
211/*
212 * For booting Linux, the board info and command line data
213 * have to be in the first 8 MB of memory, since this is
214 * the maximum mapped by the Linux kernel during initialization.
215 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkd4ca31c2004-01-02 14:00:00 +0000217
218/*-----------------------------------------------------------------------
219 * FLASH organization
220 */
Martin Krausee318d9e2007-09-27 11:10:08 +0200221/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200223#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
225#define CONFIG_SYS_FLASH_EMPTY_INFO
226#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
227#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
228#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkd4ca31c2004-01-02 14:00:00 +0000229
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200230#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200231#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
232#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
233#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
wdenkd4ca31c2004-01-02 14:00:00 +0000234
235/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200236#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
237#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkd4ca31c2004-01-02 14:00:00 +0000238
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200240
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200241#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
242
wdenkd4ca31c2004-01-02 14:00:00 +0000243/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200244 * Dynamic MTD partition support
245 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100246#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200247#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
248#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200249#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
250
251#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
252 "128k(dtb)," \
253 "1920k(kernel)," \
254 "5632(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200255 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200256
257/*-----------------------------------------------------------------------
wdenkd4ca31c2004-01-02 14:00:00 +0000258 * Hardware Information Block
259 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
261#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
262#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkd4ca31c2004-01-02 14:00:00 +0000263
264/*-----------------------------------------------------------------------
265 * Cache Configuration
266 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500268#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkd4ca31c2004-01-02 14:00:00 +0000270#endif
271
272/*-----------------------------------------------------------------------
273 * SYPCR - System Protection Control 11-9
274 * SYPCR can only be written once after reset!
275 *-----------------------------------------------------------------------
276 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
277 */
278#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkd4ca31c2004-01-02 14:00:00 +0000280 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
281#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkd4ca31c2004-01-02 14:00:00 +0000283#endif
284
285/*-----------------------------------------------------------------------
286 * SIUMCR - SIU Module Configuration 11-6
287 *-----------------------------------------------------------------------
288 * PCMCIA config., multi-function pin tri-state
289 */
wdenkc178d3d2004-01-24 20:25:54 +0000290#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkd4ca31c2004-01-02 14:00:00 +0000292#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkd4ca31c2004-01-02 14:00:00 +0000294#endif /* CONFIG_CAN_DRIVER */
295
296/*-----------------------------------------------------------------------
297 * TBSCR - Time Base Status and Control 11-26
298 *-----------------------------------------------------------------------
299 * Clear Reference Interrupt Status, Timebase freezing enabled
300 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkd4ca31c2004-01-02 14:00:00 +0000302
303/*-----------------------------------------------------------------------
wdenkd4ca31c2004-01-02 14:00:00 +0000304 * PISCR - Periodic Interrupt Status and Control 11-31
305 *-----------------------------------------------------------------------
306 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
307 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkd4ca31c2004-01-02 14:00:00 +0000309
310/*-----------------------------------------------------------------------
wdenkd4ca31c2004-01-02 14:00:00 +0000311 * SCCR - System Clock and reset Control Register 15-27
312 *-----------------------------------------------------------------------
313 * Set clock output, timebase and RTC source and divider,
314 * power management and some other internal clocks
315 */
316#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkd4ca31c2004-01-02 14:00:00 +0000318 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
319 SCCR_DFALCD00)
wdenkd4ca31c2004-01-02 14:00:00 +0000320
321/*-----------------------------------------------------------------------
322 * PCMCIA stuff
323 *-----------------------------------------------------------------------
324 *
325 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
327#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
328#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
329#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
330#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
331#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
332#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
333#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkd4ca31c2004-01-02 14:00:00 +0000334
335/*-----------------------------------------------------------------------
336 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
337 *-----------------------------------------------------------------------
338 */
339
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000340#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenkc178d3d2004-01-24 20:25:54 +0000341#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
wdenkd4ca31c2004-01-02 14:00:00 +0000342
wdenkc178d3d2004-01-24 20:25:54 +0000343#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
344#undef CONFIG_IDE_LED /* LED for ide not supported */
wdenkd4ca31c2004-01-02 14:00:00 +0000345#undef CONFIG_IDE_RESET /* reset for ide not supported */
346
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
348#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkd4ca31c2004-01-02 14:00:00 +0000349
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkd4ca31c2004-01-02 14:00:00 +0000351
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkd4ca31c2004-01-02 14:00:00 +0000353
354/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkd4ca31c2004-01-02 14:00:00 +0000356
357/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkd4ca31c2004-01-02 14:00:00 +0000359
360/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkd4ca31c2004-01-02 14:00:00 +0000362
363/*-----------------------------------------------------------------------
364 *
365 *-----------------------------------------------------------------------
366 *
367 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_DER 0
wdenkd4ca31c2004-01-02 14:00:00 +0000369
370/*
371 * Init Memory Controller:
372 *
373 * BR0/1 and OR0/1 (FLASH)
374 */
375
376#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
377#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
378
379/* used to re-map FLASH both when starting from SRAM or FLASH:
380 * restrict access enough to keep SRAM working (if any)
381 * but not too much to meddle with FLASH accesses
382 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
384#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkd4ca31c2004-01-02 14:00:00 +0000385
386/*
wdenkc178d3d2004-01-24 20:25:54 +0000387 * FLASH timing: Default value of OR0 after reset
wdenkd4ca31c2004-01-02 14:00:00 +0000388 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
wdenkc178d3d2004-01-24 20:25:54 +0000390 OR_SCY_15_CLK | OR_TRLX)
wdenkd4ca31c2004-01-02 14:00:00 +0000391
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
393#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
394#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkd4ca31c2004-01-02 14:00:00 +0000395
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
397#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
398#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkd4ca31c2004-01-02 14:00:00 +0000399
400/*
401 * BR2/3 and OR2/3 (SDRAM)
402 *
403 */
404#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
405#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
wdenkc178d3d2004-01-24 20:25:54 +0000406#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
wdenkd4ca31c2004-01-02 14:00:00 +0000407
408/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkd4ca31c2004-01-02 14:00:00 +0000410
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
412#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkd4ca31c2004-01-02 14:00:00 +0000413
wdenkc178d3d2004-01-24 20:25:54 +0000414#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
416#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkd4ca31c2004-01-02 14:00:00 +0000417#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
419#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
420#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
421#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkd4ca31c2004-01-02 14:00:00 +0000422 BR_PS_8 | BR_MS_UPMB | BR_V )
423#endif /* CONFIG_CAN_DRIVER */
424
425/*
wdenkc178d3d2004-01-24 20:25:54 +0000426 * 4096 Rows from SDRAM example configuration
427 * 1000 factor s -> ms
428 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
429 * 4 Number of refresh cycles per period
430 * 64 Refresh cycle in ms per number of rows
wdenkd4ca31c2004-01-02 14:00:00 +0000431 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
wdenkc178d3d2004-01-24 20:25:54 +0000433
434/*
Martin Kraused43e4892007-09-27 14:54:36 +0200435 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
436 *
437 * CPUclock(MHz) * 31.2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
Martin Kraused43e4892007-09-27 14:54:36 +0200439 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
440 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
442 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
443 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
444 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
Martin Kraused43e4892007-09-27 14:54:36 +0200445 *
446 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
447 * be met also in the default configuration, i.e. if environment variable
448 * 'cpuclk' is not set.
wdenkc178d3d2004-01-24 20:25:54 +0000449 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_MAMR_PTA 97
wdenkd4ca31c2004-01-02 14:00:00 +0000451
452/*
Martin Kraused43e4892007-09-27 14:54:36 +0200453 * Memory Periodic Timer Prescaler Register (MPTPR) values.
wdenkd4ca31c2004-01-02 14:00:00 +0000454 */
Martin Kraused43e4892007-09-27 14:54:36 +0200455/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
Martin Kraused43e4892007-09-27 14:54:36 +0200457/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
wdenkd4ca31c2004-01-02 14:00:00 +0000459
460/*
461 * MAMR settings for SDRAM
462 */
463
464/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkd4ca31c2004-01-02 14:00:00 +0000466 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
467 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
468/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200469#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkd4ca31c2004-01-02 14:00:00 +0000470 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
471 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
wdenkc178d3d2004-01-24 20:25:54 +0000472/* 10 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkc178d3d2004-01-24 20:25:54 +0000474 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
475 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
wdenkd4ca31c2004-01-02 14:00:00 +0000476
wdenkd4ca31c2004-01-02 14:00:00 +0000477#define CONFIG_SCC1_ENET
478#define CONFIG_FEC_ENET
Heiko Schocher48690d82010-07-20 17:45:02 +0200479#define CONFIG_ETHPRIME "SCC"
wdenkd4ca31c2004-01-02 14:00:00 +0000480
Heiko Schocher7026ead2010-02-09 15:50:27 +0100481/* pass open firmware flat tree */
482#define CONFIG_OF_LIBFDT 1
483#define CONFIG_OF_BOARD_SETUP 1
484#define CONFIG_HWCONFIG 1
485
wdenkd4ca31c2004-01-02 14:00:00 +0000486#endif /* __CONFIG_H */