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wdenkd4ca31c2004-01-02 14:00:00 +00001/*
2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkc178d3d2004-01-24 20:25:54 +000015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkd4ca31c2004-01-02 14:00:00 +000016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
37#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
38
wdenk68766092004-01-29 09:22:58 +000039#define CFG_866_OSCCLK 10000000 /* 10 MHz - PLL input clock */
wdenk75d1ea72004-01-31 20:06:54 +000040#define CFG_866_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
wdenkc178d3d2004-01-24 20:25:54 +000041#define CFG_866_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
wdenk68766092004-01-29 09:22:58 +000042#define CFG_866_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
wdenkc178d3d2004-01-24 20:25:54 +000043 /* (it will be used if there is no */
44 /* 'cpuclk' variable with valid value) */
wdenkd4ca31c2004-01-02 14:00:00 +000045
wdenk75d1ea72004-01-31 20:06:54 +000046#undef CFG_MEASURE_CPUCLK /* Measure real cpu clock */
47 /* (function measure_gclk() */
48 /* will be called) */
49#ifdef CFG_MEASURE_CPUCLK
50#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */
51#endif
52
wdenkc178d3d2004-01-24 20:25:54 +000053#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
wdenkd4ca31c2004-01-02 14:00:00 +000054
55#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
56
wdenkc178d3d2004-01-24 20:25:54 +000057#define CONFIG_BOOTCOUNT_LIMIT
wdenkd4ca31c2004-01-02 14:00:00 +000058
59#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
60
61#define CONFIG_BOARD_TYPES 1 /* support board types */
62
wdenkc178d3d2004-01-24 20:25:54 +000063#define CONFIG_PREBOOT "echo;" \
wdenkd4ca31c2004-01-02 14:00:00 +000064 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
65 "echo"
66
67#undef CONFIG_BOOTARGS
68
wdenkc178d3d2004-01-24 20:25:54 +000069#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkd4ca31c2004-01-02 14:00:00 +000070 "netdev=eth0\0" \
71 "nfsargs=setenv bootargs root=/dev/nfs rw " \
72 "nfsroot=$(serverip):$(rootpath)\0" \
73 "ramargs=setenv bootargs root=/dev/ram rw\0" \
74 "addip=setenv bootargs $(bootargs) " \
75 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
76 ":$(hostname):$(netdev):off panic=1\0" \
77 "flash_nfs=run nfsargs addip;" \
78 "bootm $(kernel_addr)\0" \
79 "flash_self=run ramargs addip;" \
80 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
81 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
82 "rootpath=/opt/eldk/ppc_8xx\0" \
83 "bootfile=/tftpboot/TQM855M/uImage\0" \
84 "kernel_addr=40080000\0" \
85 "ramdisk_addr=40180000\0" \
86 ""
87#define CONFIG_BOOTCOMMAND "run flash_self"
88
89#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
90#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
91
92#undef CONFIG_WATCHDOG /* watchdog disabled */
93
wdenkc178d3d2004-01-24 20:25:54 +000094#define CONFIG_STATUS_LED 1 /* Status LED enabled */
wdenkd4ca31c2004-01-02 14:00:00 +000095
96#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
97
98/* enable I2C and select the hardware/software driver */
99#undef CONFIG_HARD_I2C /* I2C with hardware support */
wdenkc178d3d2004-01-24 20:25:54 +0000100#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
wdenkd4ca31c2004-01-02 14:00:00 +0000101
102#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
103#define CFG_I2C_SLAVE 0xFE
104
105#ifdef CONFIG_SOFT_I2C
106/*
107 * Software (bit-bang) I2C driver configuration
108 */
109#define PB_SCL 0x00000020 /* PB 26 */
110#define PB_SDA 0x00000010 /* PB 27 */
111
112#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
113#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
114#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
115#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
116#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
wdenkc178d3d2004-01-24 20:25:54 +0000117 else immr->im_cpm.cp_pbdat &= ~PB_SDA
wdenkd4ca31c2004-01-02 14:00:00 +0000118#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
wdenkc178d3d2004-01-24 20:25:54 +0000119 else immr->im_cpm.cp_pbdat &= ~PB_SCL
wdenkd4ca31c2004-01-02 14:00:00 +0000120#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
121#endif /* CONFIG_SOFT_I2C */
122
123#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */
wdenkc178d3d2004-01-24 20:25:54 +0000124#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
wdenkd4ca31c2004-01-02 14:00:00 +0000125#define CFG_EEPROM_PAGE_WRITE_BITS 4
126#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
127
128#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
129
130#define CONFIG_MAC_PARTITION
131#define CONFIG_DOS_PARTITION
132
wdenkc178d3d2004-01-24 20:25:54 +0000133#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
wdenkd4ca31c2004-01-02 14:00:00 +0000134
135#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
136 CFG_CMD_ASKENV | \
137 CFG_CMD_DHCP | \
138 CFG_CMD_EEPROM | \
139 CFG_CMD_IDE | \
140 CFG_CMD_I2C | \
141 CFG_CMD_DATE )
142
143/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
144#include <cmd_confdefs.h>
145
146/*
147 * Miscellaneous configurable options
148 */
wdenkc178d3d2004-01-24 20:25:54 +0000149#define CFG_LONGHELP /* undef to save memory */
150#define CFG_PROMPT "=> " /* Monitor Command Prompt */
wdenkd4ca31c2004-01-02 14:00:00 +0000151
152#if 0
wdenkc178d3d2004-01-24 20:25:54 +0000153#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
wdenkd4ca31c2004-01-02 14:00:00 +0000154#endif
155#ifdef CFG_HUSH_PARSER
wdenkc178d3d2004-01-24 20:25:54 +0000156#define CFG_PROMPT_HUSH_PS2 "> "
wdenkd4ca31c2004-01-02 14:00:00 +0000157#endif
158
159#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenkc178d3d2004-01-24 20:25:54 +0000160#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkd4ca31c2004-01-02 14:00:00 +0000161#else
wdenkc178d3d2004-01-24 20:25:54 +0000162#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenkd4ca31c2004-01-02 14:00:00 +0000163#endif
wdenkc178d3d2004-01-24 20:25:54 +0000164#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
165#define CFG_MAXARGS 16 /* max number of command args */
wdenkd4ca31c2004-01-02 14:00:00 +0000166#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
167
168#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
169#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
170
wdenkc178d3d2004-01-24 20:25:54 +0000171#define CFG_LOAD_ADDR 0x100000 /* default load address */
wdenkd4ca31c2004-01-02 14:00:00 +0000172
wdenkc178d3d2004-01-24 20:25:54 +0000173#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkd4ca31c2004-01-02 14:00:00 +0000174
175#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
176
177/*
178 * Low Level Configuration Settings
179 * (address mappings, register initial values, etc.)
180 * You should know what you are doing if you make changes here.
181 */
182/*-----------------------------------------------------------------------
183 * Internal Memory Mapped Register
184 */
185#define CFG_IMMR 0xFFF00000
186
187/*-----------------------------------------------------------------------
188 * Definitions for initial stack pointer and data area (in DPRAM)
189 */
190#define CFG_INIT_RAM_ADDR CFG_IMMR
wdenkc178d3d2004-01-24 20:25:54 +0000191#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
192#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
wdenkd4ca31c2004-01-02 14:00:00 +0000193#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenkc178d3d2004-01-24 20:25:54 +0000194#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
wdenkd4ca31c2004-01-02 14:00:00 +0000195
196/*-----------------------------------------------------------------------
197 * Start addresses for the final memory configuration
198 * (Set up by the startup code)
199 * Please note that CFG_SDRAM_BASE _must_ start at 0
200 */
wdenkc178d3d2004-01-24 20:25:54 +0000201#define CFG_SDRAM_BASE 0x00000000
wdenkd4ca31c2004-01-02 14:00:00 +0000202#define CFG_FLASH_BASE 0x40000000
wdenkc178d3d2004-01-24 20:25:54 +0000203#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenkd4ca31c2004-01-02 14:00:00 +0000204#define CFG_MONITOR_BASE CFG_FLASH_BASE
wdenkc178d3d2004-01-24 20:25:54 +0000205#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkd4ca31c2004-01-02 14:00:00 +0000206
207/*
208 * For booting Linux, the board info and command line data
209 * have to be in the first 8 MB of memory, since this is
210 * the maximum mapped by the Linux kernel during initialization.
211 */
wdenkc178d3d2004-01-24 20:25:54 +0000212#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkd4ca31c2004-01-02 14:00:00 +0000213
214/*-----------------------------------------------------------------------
215 * FLASH organization
216 */
217#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
218#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
219
220#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
221#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
222
wdenkc178d3d2004-01-24 20:25:54 +0000223#define CFG_ENV_IS_IN_FLASH 1
224#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
225#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
226#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
wdenkd4ca31c2004-01-02 14:00:00 +0000227
228/* Address and size of Redundant Environment Sector */
229#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
230#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
231
232/*-----------------------------------------------------------------------
233 * Hardware Information Block
234 */
235#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
wdenkc178d3d2004-01-24 20:25:54 +0000236#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
wdenkd4ca31c2004-01-02 14:00:00 +0000237#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
238
239/*-----------------------------------------------------------------------
240 * Cache Configuration
241 */
242#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
243#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
244#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
245#endif
246
247/*-----------------------------------------------------------------------
248 * SYPCR - System Protection Control 11-9
249 * SYPCR can only be written once after reset!
250 *-----------------------------------------------------------------------
251 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
252 */
253#if defined(CONFIG_WATCHDOG)
254#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
255 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
256#else
257#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
258#endif
259
260/*-----------------------------------------------------------------------
261 * SIUMCR - SIU Module Configuration 11-6
262 *-----------------------------------------------------------------------
263 * PCMCIA config., multi-function pin tri-state
264 */
wdenkc178d3d2004-01-24 20:25:54 +0000265#ifndef CONFIG_CAN_DRIVER
wdenkd4ca31c2004-01-02 14:00:00 +0000266#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
267#else /* we must activate GPL5 in the SIUMCR for CAN */
268#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
269#endif /* CONFIG_CAN_DRIVER */
270
271/*-----------------------------------------------------------------------
272 * TBSCR - Time Base Status and Control 11-26
273 *-----------------------------------------------------------------------
274 * Clear Reference Interrupt Status, Timebase freezing enabled
275 */
276#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
277
278/*-----------------------------------------------------------------------
279 * RTCSC - Real-Time Clock Status and Control Register 11-27
280 *-----------------------------------------------------------------------
281 */
282#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
283
284/*-----------------------------------------------------------------------
285 * PISCR - Periodic Interrupt Status and Control 11-31
286 *-----------------------------------------------------------------------
287 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
288 */
289#define CFG_PISCR (PISCR_PS | PISCR_PITF)
290
291/*-----------------------------------------------------------------------
wdenkd4ca31c2004-01-02 14:00:00 +0000292 * SCCR - System Clock and reset Control Register 15-27
293 *-----------------------------------------------------------------------
294 * Set clock output, timebase and RTC source and divider,
295 * power management and some other internal clocks
296 */
297#define SCCR_MASK SCCR_EBDF11
wdenkc178d3d2004-01-24 20:25:54 +0000298#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkd4ca31c2004-01-02 14:00:00 +0000299 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
300 SCCR_DFALCD00)
wdenkd4ca31c2004-01-02 14:00:00 +0000301
302/*-----------------------------------------------------------------------
303 * PCMCIA stuff
304 *-----------------------------------------------------------------------
305 *
306 */
307#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
308#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
309#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
310#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
311#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
312#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
313#define CFG_PCMCIA_IO_ADDR (0xEC000000)
314#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
315
316/*-----------------------------------------------------------------------
317 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
318 *-----------------------------------------------------------------------
319 */
320
wdenkc178d3d2004-01-24 20:25:54 +0000321#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
wdenkd4ca31c2004-01-02 14:00:00 +0000322
wdenkc178d3d2004-01-24 20:25:54 +0000323#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
324#undef CONFIG_IDE_LED /* LED for ide not supported */
wdenkd4ca31c2004-01-02 14:00:00 +0000325#undef CONFIG_IDE_RESET /* reset for ide not supported */
326
327#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
328#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
329
330#define CFG_ATA_IDE0_OFFSET 0x0000
331
332#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
333
334/* Offset for data I/O */
335#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
336
337/* Offset for normal register accesses */
338#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
339
340/* Offset for alternate registers */
341#define CFG_ATA_ALT_OFFSET 0x0100
342
343/*-----------------------------------------------------------------------
344 *
345 *-----------------------------------------------------------------------
346 *
347 */
wdenkc178d3d2004-01-24 20:25:54 +0000348#define CFG_DER 0
wdenkd4ca31c2004-01-02 14:00:00 +0000349
350/*
351 * Init Memory Controller:
352 *
353 * BR0/1 and OR0/1 (FLASH)
354 */
355
356#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
357#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
358
359/* used to re-map FLASH both when starting from SRAM or FLASH:
360 * restrict access enough to keep SRAM working (if any)
361 * but not too much to meddle with FLASH accesses
362 */
363#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
364#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
365
366/*
wdenkc178d3d2004-01-24 20:25:54 +0000367 * FLASH timing: Default value of OR0 after reset
wdenkd4ca31c2004-01-02 14:00:00 +0000368 */
wdenkc178d3d2004-01-24 20:25:54 +0000369#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
370 OR_SCY_15_CLK | OR_TRLX)
wdenkd4ca31c2004-01-02 14:00:00 +0000371
372#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
373#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
374#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
375
376#define CFG_OR1_REMAP CFG_OR0_REMAP
377#define CFG_OR1_PRELIM CFG_OR0_PRELIM
378#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
379
380/*
381 * BR2/3 and OR2/3 (SDRAM)
382 *
383 */
384#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
385#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
wdenkc178d3d2004-01-24 20:25:54 +0000386#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
wdenkd4ca31c2004-01-02 14:00:00 +0000387
388/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
389#define CFG_OR_TIMING_SDRAM 0x00000A00
390
391#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
392#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
393
wdenkc178d3d2004-01-24 20:25:54 +0000394#ifndef CONFIG_CAN_DRIVER
395#define CFG_OR3_PRELIM CFG_OR2_PRELIM
wdenkd4ca31c2004-01-02 14:00:00 +0000396#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
397#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
wdenkc178d3d2004-01-24 20:25:54 +0000398#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
wdenkd4ca31c2004-01-02 14:00:00 +0000399#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
400#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
401#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
402 BR_PS_8 | BR_MS_UPMB | BR_V )
403#endif /* CONFIG_CAN_DRIVER */
404
405/*
wdenkc178d3d2004-01-24 20:25:54 +0000406 *
407 * 4096 Rows from SDRAM example configuration
408 * 1000 factor s -> ms
409 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
410 * 4 Number of refresh cycles per period
411 * 64 Refresh cycle in ms per number of rows
wdenkd4ca31c2004-01-02 14:00:00 +0000412 */
wdenkc178d3d2004-01-24 20:25:54 +0000413#define CFG_866_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
414
415/*
416 * Memory Periodic Timer Prescaler
417 * Periodic timer for refresh, start with refresh rate for 40 MHz clock
418 * (CFG_866_CPUCLK_MIN / CFG_866_PTA_PER_CLK)
419 */
420#define CFG_MAMR_PTA 39
wdenkd4ca31c2004-01-02 14:00:00 +0000421
422/*
423 * For 16 MBit, refresh rates could be 31.3 us
424 * (= 64 ms / 2K = 125 / quad bursts).
425 * For a simpler initialization, 15.6 us is used instead.
426 *
427 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
428 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
429 */
430#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
431#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
432
433/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
434#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
435#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
436
437/*
438 * MAMR settings for SDRAM
439 */
440
441/* 8 column SDRAM */
442#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
443 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
444 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
445/* 9 column SDRAM */
446#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
447 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
448 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
wdenkc178d3d2004-01-24 20:25:54 +0000449/* 10 column SDRAM */
450#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
451 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
452 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
wdenkd4ca31c2004-01-02 14:00:00 +0000453
454/*
455 * Internal Definitions
456 *
457 * Boot Flags
458 */
wdenkc178d3d2004-01-24 20:25:54 +0000459#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
wdenkd4ca31c2004-01-02 14:00:00 +0000460#define BOOTFLAG_WARM 0x02 /* Software reboot */
461
462#define CONFIG_SCC1_ENET
463#define CONFIG_FEC_ENET
464#define CONFIG_ETHPRIME "SCC ETHERNET"
465
466#endif /* __CONFIG_H */