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wdenkd4ca31c2004-01-02 14:00:00 +00001/*
Wolfgang Denk7c803be2008-09-16 18:02:19 +02002 * (C) Copyright 2000-2008
wdenkd4ca31c2004-01-02 14:00:00 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkc178d3d2004-01-24 20:25:54 +000015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkd4ca31c2004-01-02 14:00:00 +000016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
37#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
38
wdenk66ca92a2004-09-28 17:59:53 +000039#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
41#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
wdenk66ca92a2004-09-28 17:59:53 +000042#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
wdenkc178d3d2004-01-24 20:25:54 +000043 /* (it will be used if there is no */
44 /* 'cpuclk' variable with valid value) */
wdenkd4ca31c2004-01-02 14:00:00 +000045
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#undef CONFIG_SYS_MEASURE_CPUCLK /* Measure real cpu clock */
wdenk75d1ea72004-01-31 20:06:54 +000047 /* (function measure_gclk() */
48 /* will be called) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#ifdef CONFIG_SYS_MEASURE_CPUCLK
50#define CONFIG_SYS_8XX_XIN 10000000 /* measure_gclk() needs this */
wdenk75d1ea72004-01-31 20:06:54 +000051#endif
52
wdenkc178d3d2004-01-24 20:25:54 +000053#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020054#define CONFIG_SYS_SMC_RXBUFLEN 128
55#define CONFIG_SYS_MAXIDLE 10
wdenkd4ca31c2004-01-02 14:00:00 +000056#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
57
wdenkc178d3d2004-01-24 20:25:54 +000058#define CONFIG_BOOTCOUNT_LIMIT
wdenkd4ca31c2004-01-02 14:00:00 +000059
60#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
61
62#define CONFIG_BOARD_TYPES 1 /* support board types */
63
wdenkc178d3d2004-01-24 20:25:54 +000064#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010065 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkd4ca31c2004-01-02 14:00:00 +000066 "echo"
67
68#undef CONFIG_BOOTARGS
69
wdenkc178d3d2004-01-24 20:25:54 +000070#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkd4ca31c2004-01-02 14:00:00 +000071 "netdev=eth0\0" \
72 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010073 "nfsroot=${serverip}:${rootpath}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000074 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010075 "addip=setenv bootargs ${bootargs} " \
76 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
77 ":${hostname}:${netdev}:off panic=1\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000078 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010079 "bootm ${kernel_addr}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000080 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010081 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
82 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000083 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020084 "hostname=TQM866M\0" \
85 "bootfile=TQM866M/uImage\0" \
Martin Krause9ef57bb2007-09-26 17:55:55 +020086 "fdt_addr=400C0000\0" \
87 "kernel_addr=40100000\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020088 "ramdisk_addr=40280000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020089 "u-boot=TQM866M/u-image.bin\0" \
Martin Krause9ef57bb2007-09-26 17:55:55 +020090 "load=tftp 200000 ${u-boot}\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020091 "update=prot off 40000000 +${filesize};" \
92 "era 40000000 +${filesize};" \
Martin Krause9ef57bb2007-09-26 17:55:55 +020093 "cp.b 200000 40000000 ${filesize};" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020094 "sete filesize;save\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000095 ""
96#define CONFIG_BOOTCOMMAND "run flash_self"
97
98#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkd4ca31c2004-01-02 14:00:00 +0000100
101#undef CONFIG_WATCHDOG /* watchdog disabled */
102
wdenkc178d3d2004-01-24 20:25:54 +0000103#define CONFIG_STATUS_LED 1 /* Status LED enabled */
wdenkd4ca31c2004-01-02 14:00:00 +0000104
105#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
106
107/* enable I2C and select the hardware/software driver */
108#undef CONFIG_HARD_I2C /* I2C with hardware support */
wdenkc178d3d2004-01-24 20:25:54 +0000109#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
wdenkd4ca31c2004-01-02 14:00:00 +0000110
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
112#define CONFIG_SYS_I2C_SLAVE 0xFE
wdenkd4ca31c2004-01-02 14:00:00 +0000113
114#ifdef CONFIG_SOFT_I2C
115/*
116 * Software (bit-bang) I2C driver configuration
117 */
118#define PB_SCL 0x00000020 /* PB 26 */
119#define PB_SDA 0x00000010 /* PB 27 */
120
121#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
122#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
123#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
124#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
125#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
wdenkc178d3d2004-01-24 20:25:54 +0000126 else immr->im_cpm.cp_pbdat &= ~PB_SDA
wdenkd4ca31c2004-01-02 14:00:00 +0000127#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
wdenkc178d3d2004-01-24 20:25:54 +0000128 else immr->im_cpm.cp_pbdat &= ~PB_SCL
wdenkd4ca31c2004-01-02 14:00:00 +0000129#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
130#endif /* CONFIG_SOFT_I2C */
131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */
133#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
134#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
135#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkd4ca31c2004-01-02 14:00:00 +0000136
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500137/*
138 * BOOTP options
139 */
140#define CONFIG_BOOTP_SUBNETMASK
141#define CONFIG_BOOTP_GATEWAY
142#define CONFIG_BOOTP_HOSTNAME
143#define CONFIG_BOOTP_BOOTPATH
144#define CONFIG_BOOTP_BOOTFILESIZE
145
wdenkd4ca31c2004-01-02 14:00:00 +0000146
147#define CONFIG_MAC_PARTITION
148#define CONFIG_DOS_PARTITION
149
wdenka6cccae2004-02-06 21:48:22 +0000150#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
151
152#define CONFIG_TIMESTAMP /* but print image timestmps */
wdenkd4ca31c2004-01-02 14:00:00 +0000153
wdenkd4ca31c2004-01-02 14:00:00 +0000154
Jon Loeliger26946902007-07-04 22:30:50 -0500155/*
156 * Command line configuration.
157 */
158#include <config_cmd_default.h>
159
160#define CONFIG_CMD_ASKENV
161#define CONFIG_CMD_DHCP
162#define CONFIG_CMD_EEPROM
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200163#define CONFIG_CMD_ELF
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100164#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500165#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200166#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500167#define CONFIG_CMD_NFS
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200168#define CONFIG_CMD_SNTP
169
170
171#define CONFIG_NETCONSOLE
Jon Loeliger26946902007-07-04 22:30:50 -0500172
wdenkd4ca31c2004-01-02 14:00:00 +0000173
174/*
175 * Miscellaneous configurable options
176 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_LONGHELP /* undef to save memory */
178#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenkd4ca31c2004-01-02 14:00:00 +0000179
Wolfgang Denk2751a952006-10-28 02:29:14 +0200180#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
182#ifdef CONFIG_SYS_HUSH_PARSER
183#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkd4ca31c2004-01-02 14:00:00 +0000184#endif
185
Jon Loeliger26946902007-07-04 22:30:50 -0500186#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkd4ca31c2004-01-02 14:00:00 +0000188#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkd4ca31c2004-01-02 14:00:00 +0000190#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
192#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
193#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkd4ca31c2004-01-02 14:00:00 +0000194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
196#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkd4ca31c2004-01-02 14:00:00 +0000197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkd4ca31c2004-01-02 14:00:00 +0000199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkd4ca31c2004-01-02 14:00:00 +0000201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkd4ca31c2004-01-02 14:00:00 +0000203
204/*
205 * Low Level Configuration Settings
206 * (address mappings, register initial values, etc.)
207 * You should know what you are doing if you make changes here.
208 */
209/*-----------------------------------------------------------------------
210 * Internal Memory Mapped Register
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_IMMR 0xFFF00000
wdenkd4ca31c2004-01-02 14:00:00 +0000213
214/*-----------------------------------------------------------------------
215 * Definitions for initial stack pointer and data area (in DPRAM)
216 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
218#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
219#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
220#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
221#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkd4ca31c2004-01-02 14:00:00 +0000222
223/*-----------------------------------------------------------------------
224 * Start addresses for the final memory configuration
225 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkd4ca31c2004-01-02 14:00:00 +0000227 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_SDRAM_BASE 0x00000000
229#define CONFIG_SYS_FLASH_BASE 0x40000000
230#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
231#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
232#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
wdenkd4ca31c2004-01-02 14:00:00 +0000233
234/*
235 * For booting Linux, the board info and command line data
236 * have to be in the first 8 MB of memory, since this is
237 * the maximum mapped by the Linux kernel during initialization.
238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkd4ca31c2004-01-02 14:00:00 +0000240
241/*-----------------------------------------------------------------------
242 * FLASH organization
243 */
Martin Krausee318d9e2007-09-27 11:10:08 +0200244/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200246#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
248#define CONFIG_SYS_FLASH_EMPTY_INFO
249#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
250#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
251#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkd4ca31c2004-01-02 14:00:00 +0000252
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200253#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200254#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
255#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
256#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
wdenkd4ca31c2004-01-02 14:00:00 +0000257
258/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200259#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
260#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkd4ca31c2004-01-02 14:00:00 +0000261
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200263
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200264#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
265
wdenkd4ca31c2004-01-02 14:00:00 +0000266/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200267 * Dynamic MTD partition support
268 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100269#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200270#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
271#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200272#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
273
274#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
275 "128k(dtb)," \
276 "1920k(kernel)," \
277 "5632(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200278 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200279
280/*-----------------------------------------------------------------------
wdenkd4ca31c2004-01-02 14:00:00 +0000281 * Hardware Information Block
282 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
284#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
285#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkd4ca31c2004-01-02 14:00:00 +0000286
287/*-----------------------------------------------------------------------
288 * Cache Configuration
289 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500291#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkd4ca31c2004-01-02 14:00:00 +0000293#endif
294
295/*-----------------------------------------------------------------------
296 * SYPCR - System Protection Control 11-9
297 * SYPCR can only be written once after reset!
298 *-----------------------------------------------------------------------
299 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
300 */
301#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkd4ca31c2004-01-02 14:00:00 +0000303 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
304#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkd4ca31c2004-01-02 14:00:00 +0000306#endif
307
308/*-----------------------------------------------------------------------
309 * SIUMCR - SIU Module Configuration 11-6
310 *-----------------------------------------------------------------------
311 * PCMCIA config., multi-function pin tri-state
312 */
wdenkc178d3d2004-01-24 20:25:54 +0000313#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkd4ca31c2004-01-02 14:00:00 +0000315#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkd4ca31c2004-01-02 14:00:00 +0000317#endif /* CONFIG_CAN_DRIVER */
318
319/*-----------------------------------------------------------------------
320 * TBSCR - Time Base Status and Control 11-26
321 *-----------------------------------------------------------------------
322 * Clear Reference Interrupt Status, Timebase freezing enabled
323 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkd4ca31c2004-01-02 14:00:00 +0000325
326/*-----------------------------------------------------------------------
wdenkd4ca31c2004-01-02 14:00:00 +0000327 * PISCR - Periodic Interrupt Status and Control 11-31
328 *-----------------------------------------------------------------------
329 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
330 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkd4ca31c2004-01-02 14:00:00 +0000332
333/*-----------------------------------------------------------------------
wdenkd4ca31c2004-01-02 14:00:00 +0000334 * SCCR - System Clock and reset Control Register 15-27
335 *-----------------------------------------------------------------------
336 * Set clock output, timebase and RTC source and divider,
337 * power management and some other internal clocks
338 */
339#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkd4ca31c2004-01-02 14:00:00 +0000341 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
342 SCCR_DFALCD00)
wdenkd4ca31c2004-01-02 14:00:00 +0000343
344/*-----------------------------------------------------------------------
345 * PCMCIA stuff
346 *-----------------------------------------------------------------------
347 *
348 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
350#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
351#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
352#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
353#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
354#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
355#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
356#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkd4ca31c2004-01-02 14:00:00 +0000357
358/*-----------------------------------------------------------------------
359 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
360 *-----------------------------------------------------------------------
361 */
362
wdenkc178d3d2004-01-24 20:25:54 +0000363#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
wdenkd4ca31c2004-01-02 14:00:00 +0000364
wdenkc178d3d2004-01-24 20:25:54 +0000365#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
366#undef CONFIG_IDE_LED /* LED for ide not supported */
wdenkd4ca31c2004-01-02 14:00:00 +0000367#undef CONFIG_IDE_RESET /* reset for ide not supported */
368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
370#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkd4ca31c2004-01-02 14:00:00 +0000371
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkd4ca31c2004-01-02 14:00:00 +0000373
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkd4ca31c2004-01-02 14:00:00 +0000375
376/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkd4ca31c2004-01-02 14:00:00 +0000378
379/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkd4ca31c2004-01-02 14:00:00 +0000381
382/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkd4ca31c2004-01-02 14:00:00 +0000384
385/*-----------------------------------------------------------------------
386 *
387 *-----------------------------------------------------------------------
388 *
389 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_DER 0
wdenkd4ca31c2004-01-02 14:00:00 +0000391
392/*
393 * Init Memory Controller:
394 *
395 * BR0/1 and OR0/1 (FLASH)
396 */
397
398#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
399#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
400
401/* used to re-map FLASH both when starting from SRAM or FLASH:
402 * restrict access enough to keep SRAM working (if any)
403 * but not too much to meddle with FLASH accesses
404 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
406#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkd4ca31c2004-01-02 14:00:00 +0000407
408/*
wdenkc178d3d2004-01-24 20:25:54 +0000409 * FLASH timing: Default value of OR0 after reset
wdenkd4ca31c2004-01-02 14:00:00 +0000410 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
wdenkc178d3d2004-01-24 20:25:54 +0000412 OR_SCY_15_CLK | OR_TRLX)
wdenkd4ca31c2004-01-02 14:00:00 +0000413
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
415#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
416#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkd4ca31c2004-01-02 14:00:00 +0000417
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
419#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
420#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkd4ca31c2004-01-02 14:00:00 +0000421
422/*
423 * BR2/3 and OR2/3 (SDRAM)
424 *
425 */
426#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
427#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
wdenkc178d3d2004-01-24 20:25:54 +0000428#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
wdenkd4ca31c2004-01-02 14:00:00 +0000429
430/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkd4ca31c2004-01-02 14:00:00 +0000432
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
434#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkd4ca31c2004-01-02 14:00:00 +0000435
wdenkc178d3d2004-01-24 20:25:54 +0000436#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
438#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkd4ca31c2004-01-02 14:00:00 +0000439#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
441#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
442#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
443#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkd4ca31c2004-01-02 14:00:00 +0000444 BR_PS_8 | BR_MS_UPMB | BR_V )
445#endif /* CONFIG_CAN_DRIVER */
446
447/*
wdenkc178d3d2004-01-24 20:25:54 +0000448 * 4096 Rows from SDRAM example configuration
449 * 1000 factor s -> ms
450 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
451 * 4 Number of refresh cycles per period
452 * 64 Refresh cycle in ms per number of rows
wdenkd4ca31c2004-01-02 14:00:00 +0000453 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200454#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
wdenkc178d3d2004-01-24 20:25:54 +0000455
456/*
Martin Kraused43e4892007-09-27 14:54:36 +0200457 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
458 *
459 * CPUclock(MHz) * 31.2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
Martin Kraused43e4892007-09-27 14:54:36 +0200461 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
462 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
464 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
465 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
466 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
Martin Kraused43e4892007-09-27 14:54:36 +0200467 *
468 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
469 * be met also in the default configuration, i.e. if environment variable
470 * 'cpuclk' is not set.
wdenkc178d3d2004-01-24 20:25:54 +0000471 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472#define CONFIG_SYS_MAMR_PTA 97
wdenkd4ca31c2004-01-02 14:00:00 +0000473
474/*
Martin Kraused43e4892007-09-27 14:54:36 +0200475 * Memory Periodic Timer Prescaler Register (MPTPR) values.
wdenkd4ca31c2004-01-02 14:00:00 +0000476 */
Martin Kraused43e4892007-09-27 14:54:36 +0200477/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
Martin Kraused43e4892007-09-27 14:54:36 +0200479/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
wdenkd4ca31c2004-01-02 14:00:00 +0000481
482/*
483 * MAMR settings for SDRAM
484 */
485
486/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200487#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkd4ca31c2004-01-02 14:00:00 +0000488 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
489 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
490/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkd4ca31c2004-01-02 14:00:00 +0000492 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
493 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
wdenkc178d3d2004-01-24 20:25:54 +0000494/* 10 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200495#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkc178d3d2004-01-24 20:25:54 +0000496 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
497 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
wdenkd4ca31c2004-01-02 14:00:00 +0000498
499/*
500 * Internal Definitions
501 *
502 * Boot Flags
503 */
wdenkc178d3d2004-01-24 20:25:54 +0000504#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
wdenkd4ca31c2004-01-02 14:00:00 +0000505#define BOOTFLAG_WARM 0x02 /* Software reboot */
506
507#define CONFIG_SCC1_ENET
508#define CONFIG_FEC_ENET
509#define CONFIG_ETHPRIME "SCC ETHERNET"
510
511#endif /* __CONFIG_H */