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Srikanth Srinivasanfeb78382009-04-03 15:36:13 -05001/*
Kumar Gala561e7102011-01-31 15:51:20 -06002 * Copyright 2007-2011 Freescale Semiconductor, Inc.
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <command.h>
25#include <pci.h>
26#include <asm/processor.h>
27#include <asm/mmu.h>
28#include <asm/cache.h>
29#include <asm/immap_85xx.h>
30#include <asm/fsl_pci.h>
31#include <asm/fsl_ddr_sdram.h>
32#include <asm/io.h>
Kumar Gala5d27e022010-12-15 04:55:20 -060033#include <asm/fsl_serdes.h>
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050034#include <miiphy.h>
35#include <libfdt.h>
36#include <fdt_support.h>
Andy Fleming063c1262011-04-08 02:10:54 -050037#include <fsl_mdio.h>
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050038#include <tsec.h>
39#include <asm/fsl_law.h>
Roy Zang29c35182009-06-30 13:56:23 +080040#include <netdev.h>
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050041
Timur Tabi5a469602010-04-01 10:49:42 -050042#include "../common/ngpixis.h"
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050043#include "../common/sgmii_riser.h"
44
45DECLARE_GLOBAL_DATA_PTR;
46
Jerry Huang9c4d8762011-01-24 17:09:53 +000047int board_early_init_f(void)
48{
49#ifdef CONFIG_MMC
50 ccsr_gur_t *gur = (ccsr_gur_t *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
51
52 setbits_be32(&gur->pmuxcr,
53 (MPC85xx_PMUXCR_SDHC_CD |
54 MPC85xx_PMUXCR_SDHC_WP));
55#endif
56
57 return 0;
58}
59
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050060int checkboard(void)
61{
Timur Tabi5a469602010-04-01 10:49:42 -050062 u8 sw;
Kumar Gala6bb5b412009-07-14 22:42:01 -050063
Timur Tabi5d065c32012-03-15 11:42:27 +000064 printf("Board: P2020DS Sys ID: 0x%02x, "
65 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
Timur Tabi5a469602010-04-01 10:49:42 -050066 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
Kumar Gala6bb5b412009-07-14 22:42:01 -050067
Timur Tabi5a469602010-04-01 10:49:42 -050068 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
69 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
70
71 if (sw < 0x8)
72 /* The lower two bits are the actual vbank number */
73 printf("vBank: %d\n", sw & 3);
74 else
75 puts("Promjet\n");
Kumar Gala6bb5b412009-07-14 22:42:01 -050076
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050077 return 0;
78}
79
york394c46c2010-07-02 22:25:58 +000080#if !defined(CONFIG_DDR_SPD)
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050081/*
82 * Fixed sdram init -- doesn't use serial presence detect.
83 */
84
85phys_size_t fixed_sdram(void)
86{
87 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
88 uint d_init;
89
90 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
91 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
92 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
93 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
94 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
95 ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
96 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
97 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
98 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
99 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
100 ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
101 ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
102 ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
103 ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
104 ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
105
106 if (!strcmp("performance", getenv("perf_mode"))) {
107 /* Performance Mode Values */
108
109 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
110 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
111 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
112 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
113 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
114
115 asm("sync;isync");
116
117 udelay(500);
118
119 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
120 } else {
121 /* Stable Mode Values */
122
123 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
124 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
125 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
126 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
127 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
128
129 /* ECC will be assumed in stable mode */
130 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
131 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
132 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
133
134 asm("sync;isync");
135
136 udelay(500);
137
138 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
139 }
140
141#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
142 d_init = 1;
143 debug("DDR - 1st controller: memory initializing\n");
144 /*
145 * Poll until memory is initialized.
146 * 512 Meg at 400 might hit this 200 times or so.
147 */
148 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
149 udelay(1000);
150 debug("DDR: memory initialized\n\n");
151 asm("sync; isync");
152 udelay(500);
153#endif
154
Becky Bruce38dba0c2010-12-17 17:17:56 -0600155 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
156 CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
157 LAW_TRGT_IF_DDR) < 0) {
158 printf("ERROR setting Local Access Windows for DDR\n");
159 return 0;
160 };
161
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500162 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
163}
164
165#endif
166
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500167#ifdef CONFIG_PCI
168void pci_init_board(void)
169{
Kumar Gala4d5723d2010-12-17 07:01:00 -0600170 fsl_pcie_init_board(0);
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500171}
172#endif
173
174int board_early_init_r(void)
175{
176 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
Kumar Gala5fb6ea32009-11-13 09:25:07 -0600177 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500178
179 /*
180 * Remap Boot flash + PROMJET region to caching-inhibited
181 * so that flash can be erased properly.
182 */
183
184 /* Flush d-cache and invalidate i-cache of any FLASH data */
185 flush_dcache();
186 invalidate_icache();
187
188 /* invalidate existing TLB entry for flash + promjet */
189 disable_tlb(flash_esel);
190
191 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
192 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
193 0, flash_esel, BOOKE_PAGESZ_256M, 1);
194
195 return 0;
196}
197
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500198#ifdef CONFIG_TSEC_ENET
199int board_eth_init(bd_t *bis)
200{
Andy Fleming063c1262011-04-08 02:10:54 -0500201 struct fsl_pq_mdio_info mdio_info;
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500202 struct tsec_info_struct tsec_info[4];
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500203 int num = 0;
204
205#ifdef CONFIG_TSEC1
206 SET_STD_TSEC_INFO(tsec_info[num], 1);
207 num++;
208#endif
209#ifdef CONFIG_TSEC2
210 SET_STD_TSEC_INFO(tsec_info[num], 2);
Kumar Gala058d7dc2010-12-16 14:28:06 -0600211 if (is_serdes_configured(SGMII_TSEC2)) {
212 puts("eTSEC2 is in sgmii mode.\n");
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500213 tsec_info[num].flags |= TSEC_SGMII;
Kumar Gala058d7dc2010-12-16 14:28:06 -0600214 }
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500215 num++;
216#endif
217#ifdef CONFIG_TSEC3
218 SET_STD_TSEC_INFO(tsec_info[num], 3);
Kumar Gala058d7dc2010-12-16 14:28:06 -0600219 if (is_serdes_configured(SGMII_TSEC3)) {
220 puts("eTSEC3 is in sgmii mode.\n");
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500221 tsec_info[num].flags |= TSEC_SGMII;
Kumar Gala058d7dc2010-12-16 14:28:06 -0600222}
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500223 num++;
224#endif
225
226 if (!num) {
227 printf("No TSECs initialized\n");
228
229 return 0;
230 }
231
232#ifdef CONFIG_FSL_SGMII_RISER
233 fsl_sgmii_riser_init(tsec_info, num);
234#endif
235
Andy Fleming063c1262011-04-08 02:10:54 -0500236 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
237 mdio_info.name = DEFAULT_MII_NAME;
238
239 fsl_pq_mdio_init(bis, &mdio_info);
240
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500241 tsec_eth_init(bis, tsec_info, num);
242
Roy Zang29c35182009-06-30 13:56:23 +0800243 return pci_eth_init(bis);
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500244}
245#endif
246
247#if defined(CONFIG_OF_BOARD_SETUP)
248void ft_board_setup(void *blob, bd_t *bd)
249{
250 phys_addr_t base;
251 phys_size_t size;
252
253 ft_cpu_setup(blob, bd);
254
255 base = getenv_bootm_low();
256 size = getenv_bootm_size();
257
258 fdt_fixup_memory(blob, (u64)base, (u64)size);
259
Kumar Gala6525d512010-07-08 22:37:44 -0500260 FT_FSL_PCI_SETUP;
261
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500262#ifdef CONFIG_FSL_SGMII_RISER
263 fsl_sgmii_riser_fdt_fixup(blob);
264#endif
265}
266#endif