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Kumar Gala9490a7f2008-07-25 13:31:05 -05001/*
ramneek mehresh3d7506f2012-04-18 19:39:53 +00002 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
Kumar Gala9490a7f2008-07-25 13:31:05 -05003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala9490a7f2008-07-25 13:31:05 -05005 */
6
7/*
8 * mpc8536ds board configuration file
9 *
10 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
York Sun15672c62014-04-30 14:43:49 -070014#define CONFIG_SYS_GENERIC_BOARD
15#define CONFIG_DISPLAY_BOARDINFO
Kumar Galac7e1a432010-05-21 04:14:49 -050016#include "../board/freescale/common/ics307_clk.h"
17
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020018#ifdef CONFIG_36BIT
Kumar Gala337f9fd2009-07-30 15:54:07 -050019#define CONFIG_PHYS_64BIT 1
20#endif
21
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020022#ifdef CONFIG_SDCARD
Mingkai Hue40ac482009-09-23 15:20:38 +080023#define CONFIG_RAMBOOT_SDCARD 1
Haijun.Zhange2c9bc52014-04-10 11:16:30 +080024#define CONFIG_SYS_TEXT_BASE 0xf8f40000
Kumar Gala7a577fd2011-01-12 02:48:53 -060025#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
Mingkai Hue40ac482009-09-23 15:20:38 +080026#endif
27
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020028#ifdef CONFIG_SPIFLASH
Mingkai Hue40ac482009-09-23 15:20:38 +080029#define CONFIG_RAMBOOT_SPIFLASH 1
Haijun.Zhange2c9bc52014-04-10 11:16:30 +080030#define CONFIG_SYS_TEXT_BASE 0xf8f40000
Kumar Gala7a577fd2011-01-12 02:48:53 -060031#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
Wolfgang Denk2ae18242010-10-06 09:05:45 +020032#endif
33
34#ifndef CONFIG_SYS_TEXT_BASE
Haijun.Zhangc6e8f492014-02-13 09:03:02 +080035#define CONFIG_SYS_TEXT_BASE 0xeff40000
Mingkai Hue40ac482009-09-23 15:20:38 +080036#endif
37
Kumar Gala7a577fd2011-01-12 02:48:53 -060038#ifndef CONFIG_RESET_VECTOR_ADDRESS
39#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
40#endif
41
Haiying Wang96196a12010-11-10 15:37:13 -050042#ifndef CONFIG_SYS_MONITOR_BASE
43#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
44#endif
45
Kumar Gala9490a7f2008-07-25 13:31:05 -050046/* High Level Configuration Options */
47#define CONFIG_BOOKE 1 /* BOOKE */
48#define CONFIG_E500 1 /* BOOKE e500 family */
Kumar Gala9490a7f2008-07-25 13:31:05 -050049#define CONFIG_MPC8536 1
50#define CONFIG_MPC8536DS 1
51
Kumar Galac51fc5d2009-01-23 14:22:13 -060052#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
Kumar Gala9490a7f2008-07-25 13:31:05 -050053#define CONFIG_PCI 1 /* Enable PCI/PCIE */
54#define CONFIG_PCI1 1 /* Enable PCI controller 1 */
55#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
56#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
57#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
58#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000059#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala9490a7f2008-07-25 13:31:05 -050060#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050061#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Kumar Gala9490a7f2008-07-25 13:31:05 -050062
63#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Roy Zangf6155c62009-07-09 10:05:48 +080064#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
Kumar Gala9490a7f2008-07-25 13:31:05 -050065
66#define CONFIG_TSEC_ENET /* tsec ethernet support */
67#define CONFIG_ENV_OVERWRITE
68
Kumar Galac7e1a432010-05-21 04:14:49 -050069#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
70#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
Kumar Gala9490a7f2008-07-25 13:31:05 -050071#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
Kumar Gala9490a7f2008-07-25 13:31:05 -050072
73/*
74 * These can be toggled for performance analysis, otherwise use default.
75 */
76#define CONFIG_L2_CACHE /* toggle L2 cache */
77#define CONFIG_BTB /* toggle branch predition */
Kumar Gala9490a7f2008-07-25 13:31:05 -050078
Andy Fleming80522dc2008-10-30 16:51:33 -050079#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
80
Kumar Gala9490a7f2008-07-25 13:31:05 -050081#define CONFIG_ENABLE_36BIT_PHYS 1
82
Kumar Gala337f9fd2009-07-30 15:54:07 -050083#ifdef CONFIG_PHYS_64BIT
84#define CONFIG_ADDR_MAP 1
85#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
86#endif
87
Mingkai Hu07355702009-09-23 15:19:32 +080088#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
89#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
Kumar Gala9490a7f2008-07-25 13:31:05 -050090#define CONFIG_PANIC_HANG /* do not reset board on panic */
91
92/*
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +080093 * Config the L2 Cache as L2 SRAM
94 */
95#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
96#ifdef CONFIG_PHYS_64BIT
97#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
98#else
99#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
100#endif
101#define CONFIG_SYS_L2_SIZE (512 << 10)
102#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
103
Timur Tabie46fedf2011-08-04 18:03:41 -0500104#define CONFIG_SYS_CCSRBAR 0xffe00000
105#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Kumar Gala9490a7f2008-07-25 13:31:05 -0500106
Kumar Gala8d22ddc2011-11-09 09:10:49 -0600107#if defined(CONFIG_NAND_SPL)
Timur Tabie46fedf2011-08-04 18:03:41 -0500108#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800109#endif
110
Kumar Gala9490a7f2008-07-25 13:31:05 -0500111/* DDR Setup */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500112#define CONFIG_VERY_BIG_RAM
York Sun5614e712013-09-30 09:22:09 -0700113#define CONFIG_SYS_FSL_DDR2
Kumar Gala9490a7f2008-07-25 13:31:05 -0500114#undef CONFIG_FSL_DDR_INTERACTIVE
115#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
116#define CONFIG_DDR_SPD
Kumar Gala9490a7f2008-07-25 13:31:05 -0500117
Dave Liu9b0ad1b2008-10-28 17:53:38 +0800118#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500119#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
122#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala9490a7f2008-07-25 13:31:05 -0500123
124#define CONFIG_NUM_DDR_CONTROLLERS 1
125#define CONFIG_DIMM_SLOTS_PER_CTLR 1
126#define CONFIG_CHIP_SELECTS_PER_CTRL 2
127
128/* I2C addresses of SPD EEPROMs */
129#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_SPD_BUS_NUM 1
Kumar Gala9490a7f2008-07-25 13:31:05 -0500131
132/* These are used when DDR doesn't use SPD. */
Mingkai Hu07355702009-09-23 15:19:32 +0800133#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
Mingkai Hu07355702009-09-23 15:19:32 +0800135#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_DDR_TIMING_3 0x00000000
137#define CONFIG_SYS_DDR_TIMING_0 0x00260802
138#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
139#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
140#define CONFIG_SYS_DDR_MODE_1 0x00480432
141#define CONFIG_SYS_DDR_MODE_2 0x00000000
142#define CONFIG_SYS_DDR_INTERVAL 0x06180100
143#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
144#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
145#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
146#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
Mingkai Hu07355702009-09-23 15:19:32 +0800147#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_DDR_CONTROL2 0x04400010
Kumar Gala9490a7f2008-07-25 13:31:05 -0500149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
151#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
152#define CONFIG_SYS_DDR_SBE 0x00010000
Kumar Gala9490a7f2008-07-25 13:31:05 -0500153
Kumar Gala9490a7f2008-07-25 13:31:05 -0500154/* Make sure required options are set */
155#ifndef CONFIG_SPD_EEPROM
156#error ("CONFIG_SPD_EEPROM is required")
157#endif
158
159#undef CONFIG_CLOCKS_IN_MHZ
160
161
162/*
163 * Memory map -- xxx -this is wrong, needs updating
164 *
165 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
166 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
167 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
168 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
169 *
170 * Localbus cacheable (TBD)
171 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
172 *
173 * Localbus non-cacheable
Jason Jinc57fc282008-10-31 05:07:04 -0500174 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
Kumar Gala9490a7f2008-07-25 13:31:05 -0500175 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Jason Jinc57fc282008-10-31 05:07:04 -0500176 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
Kumar Gala9490a7f2008-07-25 13:31:05 -0500177 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
178 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
179 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
180 */
181
182/*
183 * Local Bus Definitions
184 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500186#ifdef CONFIG_PHYS_64BIT
187#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
188#else
Kumar Galac953ddf2008-12-02 14:19:34 -0600189#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
Kumar Gala337f9fd2009-07-30 15:54:07 -0500190#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500191
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800192#define CONFIG_FLASH_BR_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000193 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800194#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500195
Mingkai Hu07355702009-09-23 15:19:32 +0800196#define CONFIG_SYS_BR1_PRELIM \
197 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
198 | BR_PS_16 | BR_V)
Kumar Galac953ddf2008-12-02 14:19:34 -0600199#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500200
Mingkai Hu07355702009-09-23 15:19:32 +0800201#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
202 CONFIG_SYS_FLASH_BASE_PHYS }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_FLASH_QUIET_TEST
Kumar Gala9490a7f2008-07-25 13:31:05 -0500204#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
205
Mingkai Hu07355702009-09-23 15:19:32 +0800206#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
207#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#undef CONFIG_SYS_FLASH_CHECKSUM
Mingkai Hu07355702009-09-23 15:19:32 +0800209#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
210#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500211
Masahiro Yamada02344462014-06-04 10:26:50 +0900212#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800213#define CONFIG_SYS_RAMBOOT
Kumar Galaa55bb832010-11-29 14:32:11 -0600214#define CONFIG_SYS_EXTRA_ENV_RELOC
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800215#else
216#undef CONFIG_SYS_RAMBOOT
217#endif
218
Kumar Gala9490a7f2008-07-25 13:31:05 -0500219#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_FLASH_CFI
221#define CONFIG_SYS_FLASH_EMPTY_INFO
222#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500223
224#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
225
Ramneek Mehresh68d42302011-06-07 10:10:43 +0000226#define CONFIG_HWCONFIG /* enable hwconfig */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500227#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
228#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500229#ifdef CONFIG_PHYS_64BIT
230#define PIXIS_BASE_PHYS 0xfffdf0000ull
231#else
Kumar Gala52b565f2008-12-02 14:19:33 -0600232#define PIXIS_BASE_PHYS PIXIS_BASE
Kumar Gala337f9fd2009-07-30 15:54:07 -0500233#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500234
Kumar Gala52b565f2008-12-02 14:19:33 -0600235#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
Mingkai Hu07355702009-09-23 15:19:32 +0800236#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500237
238#define PIXIS_ID 0x0 /* Board ID at offset 0 */
239#define PIXIS_VER 0x1 /* Board version at offset 1 */
240#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
241#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
242#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
243#define PIXIS_PWR 0x5 /* PIXIS Power status register */
244#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
245#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
246#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
247#define PIXIS_VCTL 0x10 /* VELA Control Register */
248#define PIXIS_VSTAT 0x11 /* VELA Status Register */
249#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
250#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
251#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
252#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala6bb5b412009-07-14 22:42:01 -0500253#define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
254#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
255#define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
256#define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
257#define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
258#define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
259#define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500260#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
261#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
262#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
263#define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
264#define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
265#define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
266#define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
267#define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
268#define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
269#define PIXIS_VWATCH 0x24 /* Watchdog Register */
270#define PIXIS_LED 0x25 /* LED Register */
271
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800272#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
273
Kumar Gala9490a7f2008-07-25 13:31:05 -0500274/* old pixis referenced names */
275#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
276#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Matthew McClintock509e19c2011-02-25 16:20:11 -0600277#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
Kumar Gala9490a7f2008-07-25 13:31:05 -0500278
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_INIT_RAM_LOCK 1
280#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200281#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500282
Mingkai Hu07355702009-09-23 15:19:32 +0800283#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200284 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Kumar Gala9490a7f2008-07-25 13:31:05 -0500286
Mingkai Hu07355702009-09-23 15:19:32 +0800287#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
288#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500289
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800290#ifndef CONFIG_NAND_SPL
Kumar Gala337f9fd2009-07-30 15:54:07 -0500291#define CONFIG_SYS_NAND_BASE 0xffa00000
292#ifdef CONFIG_PHYS_64BIT
293#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
294#else
295#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
296#endif
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800297#else
298#define CONFIG_SYS_NAND_BASE 0xfff00000
299#ifdef CONFIG_PHYS_64BIT
300#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
301#else
302#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
303#endif
304#endif
Jason Jinc57fc282008-10-31 05:07:04 -0500305#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
306 CONFIG_SYS_NAND_BASE + 0x40000, \
307 CONFIG_SYS_NAND_BASE + 0x80000, \
308 CONFIG_SYS_NAND_BASE + 0xC0000}
309#define CONFIG_SYS_MAX_NAND_DEVICE 4
Jason Jinc57fc282008-10-31 05:07:04 -0500310#define CONFIG_CMD_NAND 1
311#define CONFIG_NAND_FSL_ELBC 1
312#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
313
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800314/* NAND boot: 4K NAND loader config */
315#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
Haijun.Zhangc6e8f492014-02-13 09:03:02 +0800316#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800317#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
318#define CONFIG_SYS_NAND_U_BOOT_START \
319 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
320#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
321#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
322#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
323
Jason Jinc57fc282008-10-31 05:07:04 -0500324/* NAND flash config */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500325#define CONFIG_SYS_NAND_BR_PRELIM \
Mingkai Hu07355702009-09-23 15:19:32 +0800326 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
327 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
328 | BR_PS_8 /* Port Size = 8 bit */ \
329 | BR_MS_FCM /* MSEL = FCM */ \
330 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500331#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
Mingkai Hu07355702009-09-23 15:19:32 +0800332 | OR_FCM_PGS /* Large Page*/ \
333 | OR_FCM_CSCT \
334 | OR_FCM_CST \
335 | OR_FCM_CHT \
336 | OR_FCM_SCY_1 \
337 | OR_FCM_TRLX \
338 | OR_FCM_EHTR)
Jason Jinc57fc282008-10-31 05:07:04 -0500339
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800340#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
341#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500342#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
343#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Jason Jinc57fc282008-10-31 05:07:04 -0500344
Mingkai Hu07355702009-09-23 15:19:32 +0800345#define CONFIG_SYS_BR4_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000346 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
Mingkai Hu07355702009-09-23 15:19:32 +0800347 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
348 | BR_PS_8 /* Port Size = 8 bit */ \
349 | BR_MS_FCM /* MSEL = FCM */ \
350 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500351#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Mingkai Hu07355702009-09-23 15:19:32 +0800352#define CONFIG_SYS_BR5_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000353 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
Mingkai Hu07355702009-09-23 15:19:32 +0800354 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
355 | BR_PS_8 /* Port Size = 8 bit */ \
356 | BR_MS_FCM /* MSEL = FCM */ \
357 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500358#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Jason Jinc57fc282008-10-31 05:07:04 -0500359
Mingkai Hu07355702009-09-23 15:19:32 +0800360#define CONFIG_SYS_BR6_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000361 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
Mingkai Hu07355702009-09-23 15:19:32 +0800362 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
363 | BR_PS_8 /* Port Size = 8 bit */ \
364 | BR_MS_FCM /* MSEL = FCM */ \
365 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500366#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Jason Jinc57fc282008-10-31 05:07:04 -0500367
Kumar Gala9490a7f2008-07-25 13:31:05 -0500368/* Serial Port - controlled on board with jumper J8
369 * open - index 2
370 * shorted - index 1
371 */
372#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_NS16550
374#define CONFIG_SYS_NS16550_SERIAL
375#define CONFIG_SYS_NS16550_REG_SIZE 1
376#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Gala93341902010-04-07 01:34:11 -0500377#ifdef CONFIG_NAND_SPL
378#define CONFIG_NS16550_MIN_FUNCTIONS
379#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500380
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_BAUDRATE_TABLE \
Kumar Gala9490a7f2008-07-25 13:31:05 -0500382 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
383
Mingkai Hu07355702009-09-23 15:19:32 +0800384#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
385#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
Kumar Gala9490a7f2008-07-25 13:31:05 -0500386
387/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_HUSH_PARSER
Kumar Gala9490a7f2008-07-25 13:31:05 -0500389
390/*
391 * Pass open firmware flat tree
392 */
393#define CONFIG_OF_LIBFDT 1
394#define CONFIG_OF_BOARD_SETUP 1
395#define CONFIG_OF_STDOUT_VIA_ALIAS 1
396
Kumar Gala9490a7f2008-07-25 13:31:05 -0500397/*
398 * I2C
399 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200400#define CONFIG_SYS_I2C
401#define CONFIG_SYS_I2C_FSL
402#define CONFIG_SYS_FSL_I2C_SPEED 400000
403#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
404#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
405#define CONFIG_SYS_FSL_I2C2_SPEED 400000
406#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
407#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
408#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
Kumar Gala9490a7f2008-07-25 13:31:05 -0500409
410/*
411 * I2C2 EEPROM
412 */
Jean-Christophe PLAGNIOL-VILLARD32628c52008-08-30 23:54:58 +0200413#define CONFIG_ID_EEPROM
414#ifdef CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_I2C_EEPROM_NXID
Kumar Gala9490a7f2008-07-25 13:31:05 -0500416#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
418#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
419#define CONFIG_SYS_EEPROM_BUS_NUM 1
Kumar Gala9490a7f2008-07-25 13:31:05 -0500420
421/*
Xie Xiaoboae2044d2011-10-03 12:18:39 -0700422 * eSPI - Enhanced SPI
423 */
424#define CONFIG_HARD_SPI
425#define CONFIG_FSL_ESPI
426
427#if defined(CONFIG_SPI_FLASH)
428#define CONFIG_SPI_FLASH_SPANSION
429#define CONFIG_CMD_SF
430#define CONFIG_SF_DEFAULT_SPEED 10000000
431#define CONFIG_SF_DEFAULT_MODE 0
432#endif
433
434/*
Kumar Gala9490a7f2008-07-25 13:31:05 -0500435 * General PCI
436 * Memory space is mapped 1-1, but I/O space must start from 0.
437 */
438
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600439#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500440#ifdef CONFIG_PHYS_64BIT
441#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
442#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
443#else
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600444#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
445#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500446#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500448#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
449#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
450#ifdef CONFIG_PHYS_64BIT
451#define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
452#else
453#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
454#endif
455#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500456
457/* controller 1, Slot 1, tgtid 1, Base address a000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600458#define CONFIG_SYS_PCIE1_NAME "Slot 1"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600459#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500460#ifdef CONFIG_PHYS_64BIT
461#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
462#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
463#else
Kumar Gala10795f42008-12-02 16:08:36 -0600464#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600465#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500466#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600468#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500469#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
470#ifdef CONFIG_PHYS_64BIT
471#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
472#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500474#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500476
477/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600478#define CONFIG_SYS_PCIE2_NAME "Slot 2"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600479#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500480#ifdef CONFIG_PHYS_64BIT
481#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
482#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
483#else
Kumar Gala10795f42008-12-02 16:08:36 -0600484#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600485#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500486#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200487#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600488#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500489#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
490#ifdef CONFIG_PHYS_64BIT
491#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
492#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200493#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500494#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200495#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500496
497/* controller 3, direct to uli, tgtid 3, Base address 8000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600498#define CONFIG_SYS_PCIE3_NAME "Slot 3"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600499#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500500#ifdef CONFIG_PHYS_64BIT
501#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
502#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
503#else
Kumar Gala10795f42008-12-02 16:08:36 -0600504#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600505#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500506#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200507#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600508#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500509#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
510#ifdef CONFIG_PHYS_64BIT
511#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
512#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200513#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500514#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200515#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500516
517#if defined(CONFIG_PCI)
518
Kumar Gala9490a7f2008-07-25 13:31:05 -0500519#define CONFIG_PCI_PNP /* do pci plug-and-play */
520
521/*PCIE video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600522#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
Kumar Gala9490a7f2008-07-25 13:31:05 -0500523
524/*PCI video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600525/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
Kumar Gala9490a7f2008-07-25 13:31:05 -0500526
527/* video */
528#define CONFIG_VIDEO
529
530#if defined(CONFIG_VIDEO)
531#define CONFIG_BIOSEMU
532#define CONFIG_CFB_CONSOLE
533#define CONFIG_VIDEO_SW_CURSOR
534#define CONFIG_VGA_AS_SINGLE_DEVICE
535#define CONFIG_ATI_RADEON_FB
536#define CONFIG_VIDEO_LOGO
537/*#define CONFIG_CONSOLE_CURSOR*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600538#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
Kumar Gala9490a7f2008-07-25 13:31:05 -0500539#endif
540
541#undef CONFIG_EEPRO100
542#undef CONFIG_TULIP
543#undef CONFIG_RTL8139
544
Kumar Gala9490a7f2008-07-25 13:31:05 -0500545#ifndef CONFIG_PCI_PNP
Kumar Gala5f91ef62008-12-02 16:08:37 -0600546 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
547 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
Kumar Gala9490a7f2008-07-25 13:31:05 -0500548 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
549#endif
550
551#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
552
553#endif /* CONFIG_PCI */
554
555/* SATA */
556#define CONFIG_LIBATA
557#define CONFIG_FSL_SATA
558
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200559#define CONFIG_SYS_SATA_MAX_DEVICE 2
Kumar Gala9490a7f2008-07-25 13:31:05 -0500560#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200561#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
562#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Kumar Gala9490a7f2008-07-25 13:31:05 -0500563#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200564#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
565#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Kumar Gala9490a7f2008-07-25 13:31:05 -0500566
567#ifdef CONFIG_FSL_SATA
568#define CONFIG_LBA48
569#define CONFIG_CMD_SATA
570#define CONFIG_DOS_PARTITION
571#define CONFIG_CMD_EXT2
572#endif
573
574#if defined(CONFIG_TSEC_ENET)
575
Kumar Gala9490a7f2008-07-25 13:31:05 -0500576#define CONFIG_MII 1 /* MII PHY management */
577#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
578#define CONFIG_TSEC1 1
579#define CONFIG_TSEC1_NAME "eTSEC1"
580#define CONFIG_TSEC3 1
581#define CONFIG_TSEC3_NAME "eTSEC3"
582
Jason Jin2e26d832008-10-10 11:41:00 +0800583#define CONFIG_FSL_SGMII_RISER 1
584#define SGMII_RISER_PHY_OFFSET 0x1c
585
Kumar Gala9490a7f2008-07-25 13:31:05 -0500586#define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
587#define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
588
589#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
590#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
591
592#define TSEC1_PHYIDX 0
593#define TSEC3_PHYIDX 0
594
595#define CONFIG_ETHPRIME "eTSEC1"
596
597#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
598
599#endif /* CONFIG_TSEC_ENET */
600
601/*
602 * Environment
603 */
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800604
605#if defined(CONFIG_SYS_RAMBOOT)
Masahiro Yamada02344462014-06-04 10:26:50 +0900606#if defined(CONFIG_RAMBOOT_SPIFLASH)
Xie Xiaobo2d4afd42011-10-03 12:54:21 -0700607#define CONFIG_ENV_IS_IN_SPI_FLASH
608#define CONFIG_ENV_SPI_BUS 0
609#define CONFIG_ENV_SPI_CS 0
610#define CONFIG_ENV_SPI_MAX_HZ 10000000
611#define CONFIG_ENV_SPI_MODE 0
612#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
613#define CONFIG_ENV_OFFSET 0xF0000
614#define CONFIG_ENV_SECT_SIZE 0x10000
615#elif defined(CONFIG_RAMBOOT_SDCARD)
616#define CONFIG_ENV_IS_IN_MMC
Fabio Estevam4394d0c2012-01-11 09:20:50 +0000617#define CONFIG_FSL_FIXED_MMC_LOCATION
Xie Xiaobo2d4afd42011-10-03 12:54:21 -0700618#define CONFIG_ENV_SIZE 0x2000
619#define CONFIG_SYS_MMC_ENV_DEV 0
620#else
Mingkai Hue40ac482009-09-23 15:20:38 +0800621 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
622 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
623 #define CONFIG_ENV_SIZE 0x2000
Kumar Gala9490a7f2008-07-25 13:31:05 -0500624#endif
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800625#else
626 #define CONFIG_ENV_IS_IN_FLASH 1
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800627 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800628 #define CONFIG_ENV_SIZE 0x2000
629 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
630#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500631
632#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200633#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500634
635/*
636 * Command line configuration.
637 */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500638#define CONFIG_CMD_IRQ
639#define CONFIG_CMD_PING
640#define CONFIG_CMD_I2C
641#define CONFIG_CMD_MII
642#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500643#define CONFIG_CMD_IRQ
Becky Bruce199e2622010-06-17 11:37:25 -0500644#define CONFIG_CMD_REGINFO
Kumar Gala9490a7f2008-07-25 13:31:05 -0500645
646#if defined(CONFIG_PCI)
647#define CONFIG_CMD_PCI
Kumar Gala9490a7f2008-07-25 13:31:05 -0500648#endif
649
650#undef CONFIG_WATCHDOG /* watchdog disabled */
651
Andy Fleming80522dc2008-10-30 16:51:33 -0500652#define CONFIG_MMC 1
653
654#ifdef CONFIG_MMC
655#define CONFIG_FSL_ESDHC
656#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
657#define CONFIG_CMD_MMC
658#define CONFIG_GENERIC_MMC
Fanzc1116ebb2011-10-03 12:18:42 -0700659#endif
660
661/*
662 * USB
663 */
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000664#define CONFIG_HAS_FSL_MPH_USB
665#ifdef CONFIG_HAS_FSL_MPH_USB
Fanzc1116ebb2011-10-03 12:18:42 -0700666#define CONFIG_USB_EHCI
667
668#ifdef CONFIG_USB_EHCI
669#define CONFIG_CMD_USB
670#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
671#define CONFIG_USB_EHCI_FSL
672#define CONFIG_USB_STORAGE
673#endif
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000674#endif
Fanzc1116ebb2011-10-03 12:18:42 -0700675
676#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
Andy Fleming80522dc2008-10-30 16:51:33 -0500677#define CONFIG_CMD_EXT2
678#define CONFIG_CMD_FAT
679#define CONFIG_DOS_PARTITION
680#endif
681
Kumar Gala9490a7f2008-07-25 13:31:05 -0500682/*
683 * Miscellaneous configurable options
684 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200685#define CONFIG_SYS_LONGHELP /* undef to save memory */
Mingkai Hu07355702009-09-23 15:19:32 +0800686#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Kim Phillips5be58f52010-07-14 19:47:18 -0500687#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200688#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500689#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200690#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500691#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200692#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500693#endif
Mingkai Hu07355702009-09-23 15:19:32 +0800694#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
695 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200696#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
Mingkai Hu07355702009-09-23 15:19:32 +0800697#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500698
699/*
700 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500701 * have to be in the first 64 MB of memory, since this is
Kumar Gala9490a7f2008-07-25 13:31:05 -0500702 * the maximum mapped by the Linux kernel during initialization.
703 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500704#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
705#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500706
Kumar Gala9490a7f2008-07-25 13:31:05 -0500707#if defined(CONFIG_CMD_KGDB)
708#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500709#endif
710
711/*
712 * Environment Configuration
713 */
714
715/* The mac addresses for all ethernet interface */
716#if defined(CONFIG_TSEC_ENET)
717#define CONFIG_HAS_ETH0
Kumar Gala9490a7f2008-07-25 13:31:05 -0500718#define CONFIG_HAS_ETH1
Kumar Gala9490a7f2008-07-25 13:31:05 -0500719#define CONFIG_HAS_ETH2
Kumar Gala9490a7f2008-07-25 13:31:05 -0500720#define CONFIG_HAS_ETH3
Kumar Gala9490a7f2008-07-25 13:31:05 -0500721#endif
722
723#define CONFIG_IPADDR 192.168.1.254
724
725#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000726#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000727#define CONFIG_BOOTFILE "uImage"
Mingkai Hu07355702009-09-23 15:19:32 +0800728#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500729
730#define CONFIG_SERVERIP 192.168.1.1
731#define CONFIG_GATEWAYIP 192.168.1.1
732#define CONFIG_NETMASK 255.255.255.0
733
734/* default location for tftp and bootm */
735#define CONFIG_LOADADDR 1000000
736
737#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
738#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
739
740#define CONFIG_BAUDRATE 115200
741
742#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200743"netdev=eth0\0" \
744"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
745"tftpflash=tftpboot $loadaddr $uboot; " \
746 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
747 " +$filesize; " \
748 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
749 " +$filesize; " \
750 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
751 " $filesize; " \
752 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
753 " +$filesize; " \
754 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
755 " $filesize\0" \
756"consoledev=ttyS0\0" \
757"ramdiskaddr=2000000\0" \
758"ramdiskfile=8536ds/ramdisk.uboot\0" \
759"fdtaddr=c00000\0" \
760"fdtfile=8536ds/mpc8536ds.dtb\0" \
761"bdev=sda3\0" \
762"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
Kumar Gala9490a7f2008-07-25 13:31:05 -0500763
764#define CONFIG_HDBOOT \
765 "setenv bootargs root=/dev/$bdev rw " \
766 "console=$consoledev,$baudrate $othbootargs;" \
767 "tftp $loadaddr $bootfile;" \
768 "tftp $fdtaddr $fdtfile;" \
769 "bootm $loadaddr - $fdtaddr"
770
771#define CONFIG_NFSBOOTCOMMAND \
772 "setenv bootargs root=/dev/nfs rw " \
773 "nfsroot=$serverip:$rootpath " \
774 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
775 "console=$consoledev,$baudrate $othbootargs;" \
776 "tftp $loadaddr $bootfile;" \
777 "tftp $fdtaddr $fdtfile;" \
778 "bootm $loadaddr - $fdtaddr"
779
780#define CONFIG_RAMBOOTCOMMAND \
781 "setenv bootargs root=/dev/ram rw " \
782 "console=$consoledev,$baudrate $othbootargs;" \
783 "tftp $ramdiskaddr $ramdiskfile;" \
784 "tftp $loadaddr $bootfile;" \
785 "tftp $fdtaddr $fdtfile;" \
786 "bootm $loadaddr $ramdiskaddr $fdtaddr"
787
788#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
789
790#endif /* __CONFIG_H */