blob: 7f7ff9f4e1f42e03406a1eb51183c441bc0c99e2 [file] [log] [blame]
Kumar Gala9490a7f2008-07-25 13:31:05 -05001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2007-2009,2010-2011 Freescale Semiconductor, Inc.
Kumar Gala9490a7f2008-07-25 13:31:05 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8536ds board configuration file
25 *
26 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
Kumar Galac7e1a432010-05-21 04:14:49 -050030#include "../board/freescale/common/ics307_clk.h"
31
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020032#ifdef CONFIG_36BIT
Kumar Gala337f9fd2009-07-30 15:54:07 -050033#define CONFIG_PHYS_64BIT 1
34#endif
35
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020036#ifdef CONFIG_NAND
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +080037#define CONFIG_NAND_U_BOOT 1
38#define CONFIG_RAMBOOT_NAND 1
Haiying Wang96196a12010-11-10 15:37:13 -050039#ifdef CONFIG_NAND_SPL
40#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
41#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
42#else
Kumar Gala00203c62011-01-31 15:57:01 -060043#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
Wolfgang Denk2ae18242010-10-06 09:05:45 +020044#define CONFIG_SYS_TEXT_BASE 0xf8f82000
Haiying Wang96196a12010-11-10 15:37:13 -050045#endif /* CONFIG_NAND_SPL */
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +080046#endif
47
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020048#ifdef CONFIG_SDCARD
Mingkai Hue40ac482009-09-23 15:20:38 +080049#define CONFIG_RAMBOOT_SDCARD 1
Wolfgang Denk2ae18242010-10-06 09:05:45 +020050#define CONFIG_SYS_TEXT_BASE 0xf8f80000
Kumar Gala7a577fd2011-01-12 02:48:53 -060051#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
Mingkai Hue40ac482009-09-23 15:20:38 +080052#endif
53
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020054#ifdef CONFIG_SPIFLASH
Mingkai Hue40ac482009-09-23 15:20:38 +080055#define CONFIG_RAMBOOT_SPIFLASH 1
Wolfgang Denk2ae18242010-10-06 09:05:45 +020056#define CONFIG_SYS_TEXT_BASE 0xf8f80000
Kumar Gala7a577fd2011-01-12 02:48:53 -060057#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
Wolfgang Denk2ae18242010-10-06 09:05:45 +020058#endif
59
60#ifndef CONFIG_SYS_TEXT_BASE
61#define CONFIG_SYS_TEXT_BASE 0xeff80000
Mingkai Hue40ac482009-09-23 15:20:38 +080062#endif
63
Kumar Gala7a577fd2011-01-12 02:48:53 -060064#ifndef CONFIG_RESET_VECTOR_ADDRESS
65#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
66#endif
67
Haiying Wang96196a12010-11-10 15:37:13 -050068#ifndef CONFIG_SYS_MONITOR_BASE
69#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
70#endif
71
Kumar Gala9490a7f2008-07-25 13:31:05 -050072/* High Level Configuration Options */
73#define CONFIG_BOOKE 1 /* BOOKE */
74#define CONFIG_E500 1 /* BOOKE e500 family */
75#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
76#define CONFIG_MPC8536 1
77#define CONFIG_MPC8536DS 1
78
Kumar Galac51fc5d2009-01-23 14:22:13 -060079#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
Kumar Gala9490a7f2008-07-25 13:31:05 -050080#define CONFIG_PCI 1 /* Enable PCI/PCIE */
81#define CONFIG_PCI1 1 /* Enable PCI controller 1 */
82#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
83#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
84#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
85#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
86#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050087#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Kumar Gala9490a7f2008-07-25 13:31:05 -050088
89#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Roy Zangf6155c62009-07-09 10:05:48 +080090#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
Kumar Gala9490a7f2008-07-25 13:31:05 -050091
92#define CONFIG_TSEC_ENET /* tsec ethernet support */
93#define CONFIG_ENV_OVERWRITE
94
Kumar Galac7e1a432010-05-21 04:14:49 -050095#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
96#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
Kumar Gala9490a7f2008-07-25 13:31:05 -050097#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
Kumar Gala9490a7f2008-07-25 13:31:05 -050098
99/*
100 * These can be toggled for performance analysis, otherwise use default.
101 */
102#define CONFIG_L2_CACHE /* toggle L2 cache */
103#define CONFIG_BTB /* toggle branch predition */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500104
Andy Fleming80522dc2008-10-30 16:51:33 -0500105#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
106
Kumar Gala9490a7f2008-07-25 13:31:05 -0500107#define CONFIG_ENABLE_36BIT_PHYS 1
108
Kumar Gala337f9fd2009-07-30 15:54:07 -0500109#ifdef CONFIG_PHYS_64BIT
110#define CONFIG_ADDR_MAP 1
111#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
112#endif
113
Mingkai Hu07355702009-09-23 15:19:32 +0800114#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
115#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500116#define CONFIG_PANIC_HANG /* do not reset board on panic */
117
118/*
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800119 * Config the L2 Cache as L2 SRAM
120 */
121#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
122#ifdef CONFIG_PHYS_64BIT
123#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
124#else
125#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
126#endif
127#define CONFIG_SYS_L2_SIZE (512 << 10)
128#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
129
130/*
Kumar Gala9490a7f2008-07-25 13:31:05 -0500131 * Base addresses -- Note these are effective addresses where the
132 * actual resources get mapped (not physical addresses)
133 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500135#ifdef CONFIG_PHYS_64BIT
Mingkai Hu07355702009-09-23 15:19:32 +0800136#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500137#else
Mingkai Hu07355702009-09-23 15:19:32 +0800138#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
Kumar Gala337f9fd2009-07-30 15:54:07 -0500139#endif
Mingkai Hu07355702009-09-23 15:19:32 +0800140#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500141
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800142#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
143#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
144#else
145#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
146#endif
147
Kumar Gala9490a7f2008-07-25 13:31:05 -0500148/* DDR Setup */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500149#define CONFIG_VERY_BIG_RAM
Kumar Gala9490a7f2008-07-25 13:31:05 -0500150#define CONFIG_FSL_DDR2
151#undef CONFIG_FSL_DDR_INTERACTIVE
152#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
153#define CONFIG_DDR_SPD
Kumar Gala9490a7f2008-07-25 13:31:05 -0500154
Dave Liu9b0ad1b2008-10-28 17:53:38 +0800155#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500156#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
159#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala9490a7f2008-07-25 13:31:05 -0500160
161#define CONFIG_NUM_DDR_CONTROLLERS 1
162#define CONFIG_DIMM_SLOTS_PER_CTLR 1
163#define CONFIG_CHIP_SELECTS_PER_CTRL 2
164
165/* I2C addresses of SPD EEPROMs */
166#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_SPD_BUS_NUM 1
Kumar Gala9490a7f2008-07-25 13:31:05 -0500168
169/* These are used when DDR doesn't use SPD. */
Mingkai Hu07355702009-09-23 15:19:32 +0800170#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
Mingkai Hu07355702009-09-23 15:19:32 +0800172#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_DDR_TIMING_3 0x00000000
174#define CONFIG_SYS_DDR_TIMING_0 0x00260802
175#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
176#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
177#define CONFIG_SYS_DDR_MODE_1 0x00480432
178#define CONFIG_SYS_DDR_MODE_2 0x00000000
179#define CONFIG_SYS_DDR_INTERVAL 0x06180100
180#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
181#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
182#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
183#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
Mingkai Hu07355702009-09-23 15:19:32 +0800184#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_DDR_CONTROL2 0x04400010
Kumar Gala9490a7f2008-07-25 13:31:05 -0500186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
188#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
189#define CONFIG_SYS_DDR_SBE 0x00010000
Kumar Gala9490a7f2008-07-25 13:31:05 -0500190
Kumar Gala9490a7f2008-07-25 13:31:05 -0500191/* Make sure required options are set */
192#ifndef CONFIG_SPD_EEPROM
193#error ("CONFIG_SPD_EEPROM is required")
194#endif
195
196#undef CONFIG_CLOCKS_IN_MHZ
197
198
199/*
200 * Memory map -- xxx -this is wrong, needs updating
201 *
202 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
203 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
204 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
205 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
206 *
207 * Localbus cacheable (TBD)
208 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
209 *
210 * Localbus non-cacheable
Jason Jinc57fc282008-10-31 05:07:04 -0500211 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
Kumar Gala9490a7f2008-07-25 13:31:05 -0500212 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Jason Jinc57fc282008-10-31 05:07:04 -0500213 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
Kumar Gala9490a7f2008-07-25 13:31:05 -0500214 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
215 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
216 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
217 */
218
219/*
220 * Local Bus Definitions
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500223#ifdef CONFIG_PHYS_64BIT
224#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
225#else
Kumar Galac953ddf2008-12-02 14:19:34 -0600226#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
Kumar Gala337f9fd2009-07-30 15:54:07 -0500227#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500228
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800229#define CONFIG_FLASH_BR_PRELIM \
Mingkai Hu07355702009-09-23 15:19:32 +0800230 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
231 | BR_PS_16 | BR_V)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800232#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500233
Mingkai Hu07355702009-09-23 15:19:32 +0800234#define CONFIG_SYS_BR1_PRELIM \
235 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
236 | BR_PS_16 | BR_V)
Kumar Galac953ddf2008-12-02 14:19:34 -0600237#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500238
Mingkai Hu07355702009-09-23 15:19:32 +0800239#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
240 CONFIG_SYS_FLASH_BASE_PHYS }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_FLASH_QUIET_TEST
Kumar Gala9490a7f2008-07-25 13:31:05 -0500242#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
243
Mingkai Hu07355702009-09-23 15:19:32 +0800244#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
245#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#undef CONFIG_SYS_FLASH_CHECKSUM
Mingkai Hu07355702009-09-23 15:19:32 +0800247#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
248#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500249
Kumar Galaa55bb832010-11-29 14:32:11 -0600250#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
251 defined(CONFIG_RAMBOOT_SPIFLASH)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800252#define CONFIG_SYS_RAMBOOT
Kumar Galaa55bb832010-11-29 14:32:11 -0600253#define CONFIG_SYS_EXTRA_ENV_RELOC
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800254#else
255#undef CONFIG_SYS_RAMBOOT
256#endif
257
Kumar Gala9490a7f2008-07-25 13:31:05 -0500258#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_FLASH_CFI
260#define CONFIG_SYS_FLASH_EMPTY_INFO
261#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500262
263#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
264
265#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
266#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500267#ifdef CONFIG_PHYS_64BIT
268#define PIXIS_BASE_PHYS 0xfffdf0000ull
269#else
Kumar Gala52b565f2008-12-02 14:19:33 -0600270#define PIXIS_BASE_PHYS PIXIS_BASE
Kumar Gala337f9fd2009-07-30 15:54:07 -0500271#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500272
Kumar Gala52b565f2008-12-02 14:19:33 -0600273#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
Mingkai Hu07355702009-09-23 15:19:32 +0800274#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500275
276#define PIXIS_ID 0x0 /* Board ID at offset 0 */
277#define PIXIS_VER 0x1 /* Board version at offset 1 */
278#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
279#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
280#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
281#define PIXIS_PWR 0x5 /* PIXIS Power status register */
282#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
283#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
284#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
285#define PIXIS_VCTL 0x10 /* VELA Control Register */
286#define PIXIS_VSTAT 0x11 /* VELA Status Register */
287#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
288#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
289#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
290#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala6bb5b412009-07-14 22:42:01 -0500291#define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
292#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
293#define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
294#define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
295#define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
296#define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
297#define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500298#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
299#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
300#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
301#define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
302#define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
303#define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
304#define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
305#define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
306#define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
307#define PIXIS_VWATCH 0x24 /* Watchdog Register */
308#define PIXIS_LED 0x25 /* LED Register */
309
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800310#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
311
Kumar Gala9490a7f2008-07-25 13:31:05 -0500312/* old pixis referenced names */
313#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
314#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Matthew McClintock509e19c2011-02-25 16:20:11 -0600315#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
Kumar Gala9490a7f2008-07-25 13:31:05 -0500316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_INIT_RAM_LOCK 1
318#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200319#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500320
Mingkai Hu07355702009-09-23 15:19:32 +0800321#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200322 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Kumar Gala9490a7f2008-07-25 13:31:05 -0500324
Mingkai Hu07355702009-09-23 15:19:32 +0800325#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
326#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500327
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800328#ifndef CONFIG_NAND_SPL
Kumar Gala337f9fd2009-07-30 15:54:07 -0500329#define CONFIG_SYS_NAND_BASE 0xffa00000
330#ifdef CONFIG_PHYS_64BIT
331#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
332#else
333#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
334#endif
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800335#else
336#define CONFIG_SYS_NAND_BASE 0xfff00000
337#ifdef CONFIG_PHYS_64BIT
338#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
339#else
340#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
341#endif
342#endif
Jason Jinc57fc282008-10-31 05:07:04 -0500343#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
344 CONFIG_SYS_NAND_BASE + 0x40000, \
345 CONFIG_SYS_NAND_BASE + 0x80000, \
346 CONFIG_SYS_NAND_BASE + 0xC0000}
347#define CONFIG_SYS_MAX_NAND_DEVICE 4
Jason Jinc57fc282008-10-31 05:07:04 -0500348#define CONFIG_MTD_NAND_VERIFY_WRITE
349#define CONFIG_CMD_NAND 1
350#define CONFIG_NAND_FSL_ELBC 1
351#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
352
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800353/* NAND boot: 4K NAND loader config */
354#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
355#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
356#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
357#define CONFIG_SYS_NAND_U_BOOT_START \
358 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
359#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
360#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
361#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
362
Jason Jinc57fc282008-10-31 05:07:04 -0500363/* NAND flash config */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500364#define CONFIG_SYS_NAND_BR_PRELIM \
Mingkai Hu07355702009-09-23 15:19:32 +0800365 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
366 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
367 | BR_PS_8 /* Port Size = 8 bit */ \
368 | BR_MS_FCM /* MSEL = FCM */ \
369 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500370#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
Mingkai Hu07355702009-09-23 15:19:32 +0800371 | OR_FCM_PGS /* Large Page*/ \
372 | OR_FCM_CSCT \
373 | OR_FCM_CST \
374 | OR_FCM_CHT \
375 | OR_FCM_SCY_1 \
376 | OR_FCM_TRLX \
377 | OR_FCM_EHTR)
Jason Jinc57fc282008-10-31 05:07:04 -0500378
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800379#ifdef CONFIG_RAMBOOT_NAND
Matthew McClintocka3055c52011-04-05 14:39:33 -0500380#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
381#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800382#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
383#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
384#else
385#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
386#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500387#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
388#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800389#endif
Jason Jinc57fc282008-10-31 05:07:04 -0500390
Mingkai Hu07355702009-09-23 15:19:32 +0800391#define CONFIG_SYS_BR4_PRELIM \
392 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \
393 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
394 | BR_PS_8 /* Port Size = 8 bit */ \
395 | BR_MS_FCM /* MSEL = FCM */ \
396 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500397#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Mingkai Hu07355702009-09-23 15:19:32 +0800398#define CONFIG_SYS_BR5_PRELIM \
399 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \
400 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
401 | BR_PS_8 /* Port Size = 8 bit */ \
402 | BR_MS_FCM /* MSEL = FCM */ \
403 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500404#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Jason Jinc57fc282008-10-31 05:07:04 -0500405
Mingkai Hu07355702009-09-23 15:19:32 +0800406#define CONFIG_SYS_BR6_PRELIM \
407 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \
408 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
409 | BR_PS_8 /* Port Size = 8 bit */ \
410 | BR_MS_FCM /* MSEL = FCM */ \
411 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500412#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Jason Jinc57fc282008-10-31 05:07:04 -0500413
Kumar Gala9490a7f2008-07-25 13:31:05 -0500414/* Serial Port - controlled on board with jumper J8
415 * open - index 2
416 * shorted - index 1
417 */
418#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_NS16550
420#define CONFIG_SYS_NS16550_SERIAL
421#define CONFIG_SYS_NS16550_REG_SIZE 1
422#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Gala93341902010-04-07 01:34:11 -0500423#ifdef CONFIG_NAND_SPL
424#define CONFIG_NS16550_MIN_FUNCTIONS
425#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500426
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_BAUDRATE_TABLE \
Kumar Gala9490a7f2008-07-25 13:31:05 -0500428 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
429
Mingkai Hu07355702009-09-23 15:19:32 +0800430#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
431#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
Kumar Gala9490a7f2008-07-25 13:31:05 -0500432
433/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_HUSH_PARSER
435#ifdef CONFIG_SYS_HUSH_PARSER
436#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Kumar Gala9490a7f2008-07-25 13:31:05 -0500437#endif
438
439/*
440 * Pass open firmware flat tree
441 */
442#define CONFIG_OF_LIBFDT 1
443#define CONFIG_OF_BOARD_SETUP 1
444#define CONFIG_OF_STDOUT_VIA_ALIAS 1
445
Kumar Gala9490a7f2008-07-25 13:31:05 -0500446/*
447 * I2C
448 */
449#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
450#define CONFIG_HARD_I2C /* I2C with hardware support */
451#undef CONFIG_SOFT_I2C /* I2C bit-banged */
452#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
454#define CONFIG_SYS_I2C_SLAVE 0x7F
455#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */
456#define CONFIG_SYS_I2C_OFFSET 0x3000
457#define CONFIG_SYS_I2C2_OFFSET 0x3100
Kumar Gala9490a7f2008-07-25 13:31:05 -0500458
459/*
460 * I2C2 EEPROM
461 */
Jean-Christophe PLAGNIOL-VILLARD32628c52008-08-30 23:54:58 +0200462#define CONFIG_ID_EEPROM
463#ifdef CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200464#define CONFIG_SYS_I2C_EEPROM_NXID
Kumar Gala9490a7f2008-07-25 13:31:05 -0500465#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
467#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
468#define CONFIG_SYS_EEPROM_BUS_NUM 1
Kumar Gala9490a7f2008-07-25 13:31:05 -0500469
470/*
471 * General PCI
472 * Memory space is mapped 1-1, but I/O space must start from 0.
473 */
474
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600475#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500476#ifdef CONFIG_PHYS_64BIT
477#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
478#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
479#else
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600480#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
481#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500482#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200483#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500484#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
485#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
486#ifdef CONFIG_PHYS_64BIT
487#define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
488#else
489#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
490#endif
491#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500492
493/* controller 1, Slot 1, tgtid 1, Base address a000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600494#define CONFIG_SYS_PCIE1_NAME "Slot 1"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600495#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500496#ifdef CONFIG_PHYS_64BIT
497#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
498#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
499#else
Kumar Gala10795f42008-12-02 16:08:36 -0600500#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600501#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500502#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200503#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600504#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500505#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
506#ifdef CONFIG_PHYS_64BIT
507#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
508#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200509#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500510#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200511#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500512
513/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600514#define CONFIG_SYS_PCIE2_NAME "Slot 2"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600515#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500516#ifdef CONFIG_PHYS_64BIT
517#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
518#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
519#else
Kumar Gala10795f42008-12-02 16:08:36 -0600520#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600521#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500522#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200523#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600524#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500525#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
526#ifdef CONFIG_PHYS_64BIT
527#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
528#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200529#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500530#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200531#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500532
533/* controller 3, direct to uli, tgtid 3, Base address 8000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600534#define CONFIG_SYS_PCIE3_NAME "Slot 3"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600535#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500536#ifdef CONFIG_PHYS_64BIT
537#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
538#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
539#else
Kumar Gala10795f42008-12-02 16:08:36 -0600540#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600541#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500542#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200543#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600544#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500545#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
546#ifdef CONFIG_PHYS_64BIT
547#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
548#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200549#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500550#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200551#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500552
553#if defined(CONFIG_PCI)
554
555#define CONFIG_NET_MULTI
556#define CONFIG_PCI_PNP /* do pci plug-and-play */
557
558/*PCIE video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600559#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
Kumar Gala9490a7f2008-07-25 13:31:05 -0500560
561/*PCI video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600562/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
Kumar Gala9490a7f2008-07-25 13:31:05 -0500563
564/* video */
565#define CONFIG_VIDEO
566
567#if defined(CONFIG_VIDEO)
568#define CONFIG_BIOSEMU
569#define CONFIG_CFB_CONSOLE
570#define CONFIG_VIDEO_SW_CURSOR
571#define CONFIG_VGA_AS_SINGLE_DEVICE
572#define CONFIG_ATI_RADEON_FB
573#define CONFIG_VIDEO_LOGO
574/*#define CONFIG_CONSOLE_CURSOR*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600575#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
Kumar Gala9490a7f2008-07-25 13:31:05 -0500576#endif
577
578#undef CONFIG_EEPRO100
579#undef CONFIG_TULIP
580#undef CONFIG_RTL8139
581
Kumar Gala9490a7f2008-07-25 13:31:05 -0500582#ifndef CONFIG_PCI_PNP
Kumar Gala5f91ef62008-12-02 16:08:37 -0600583 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
584 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
Kumar Gala9490a7f2008-07-25 13:31:05 -0500585 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
586#endif
587
588#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
589
590#endif /* CONFIG_PCI */
591
592/* SATA */
593#define CONFIG_LIBATA
594#define CONFIG_FSL_SATA
595
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200596#define CONFIG_SYS_SATA_MAX_DEVICE 2
Kumar Gala9490a7f2008-07-25 13:31:05 -0500597#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200598#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
599#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Kumar Gala9490a7f2008-07-25 13:31:05 -0500600#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200601#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
602#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Kumar Gala9490a7f2008-07-25 13:31:05 -0500603
604#ifdef CONFIG_FSL_SATA
605#define CONFIG_LBA48
606#define CONFIG_CMD_SATA
607#define CONFIG_DOS_PARTITION
608#define CONFIG_CMD_EXT2
609#endif
610
611#if defined(CONFIG_TSEC_ENET)
612
613#ifndef CONFIG_NET_MULTI
614#define CONFIG_NET_MULTI 1
615#endif
616
617#define CONFIG_MII 1 /* MII PHY management */
618#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
619#define CONFIG_TSEC1 1
620#define CONFIG_TSEC1_NAME "eTSEC1"
621#define CONFIG_TSEC3 1
622#define CONFIG_TSEC3_NAME "eTSEC3"
623
Jason Jin2e26d832008-10-10 11:41:00 +0800624#define CONFIG_FSL_SGMII_RISER 1
625#define SGMII_RISER_PHY_OFFSET 0x1c
626
Kumar Gala9490a7f2008-07-25 13:31:05 -0500627#define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
628#define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
629
630#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
631#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
632
633#define TSEC1_PHYIDX 0
634#define TSEC3_PHYIDX 0
635
636#define CONFIG_ETHPRIME "eTSEC1"
637
638#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
639
640#endif /* CONFIG_TSEC_ENET */
641
642/*
643 * Environment
644 */
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800645
646#if defined(CONFIG_SYS_RAMBOOT)
647#if defined(CONFIG_RAMBOOT_NAND)
648 #define CONFIG_ENV_IS_IN_NAND 1
649 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
650 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
Mingkai Hue40ac482009-09-23 15:20:38 +0800651#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
652 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
653 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
654 #define CONFIG_ENV_SIZE 0x2000
Kumar Gala9490a7f2008-07-25 13:31:05 -0500655#endif
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800656#else
657 #define CONFIG_ENV_IS_IN_FLASH 1
658 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
659 #define CONFIG_ENV_ADDR 0xfff80000
660 #else
661 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
662 #endif
663 #define CONFIG_ENV_SIZE 0x2000
664 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
665#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500666
667#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200668#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500669
670/*
671 * Command line configuration.
672 */
673#include <config_cmd_default.h>
674
675#define CONFIG_CMD_IRQ
676#define CONFIG_CMD_PING
677#define CONFIG_CMD_I2C
678#define CONFIG_CMD_MII
679#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500680#define CONFIG_CMD_IRQ
681#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500682#define CONFIG_CMD_REGINFO
Kumar Gala9490a7f2008-07-25 13:31:05 -0500683
684#if defined(CONFIG_PCI)
685#define CONFIG_CMD_PCI
Kumar Gala9490a7f2008-07-25 13:31:05 -0500686#define CONFIG_CMD_NET
687#endif
688
689#undef CONFIG_WATCHDOG /* watchdog disabled */
690
Andy Fleming80522dc2008-10-30 16:51:33 -0500691#define CONFIG_MMC 1
692
693#ifdef CONFIG_MMC
694#define CONFIG_FSL_ESDHC
695#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
696#define CONFIG_CMD_MMC
697#define CONFIG_GENERIC_MMC
698#define CONFIG_CMD_EXT2
699#define CONFIG_CMD_FAT
700#define CONFIG_DOS_PARTITION
701#endif
702
Kumar Gala9490a7f2008-07-25 13:31:05 -0500703/*
704 * Miscellaneous configurable options
705 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200706#define CONFIG_SYS_LONGHELP /* undef to save memory */
Mingkai Hu07355702009-09-23 15:19:32 +0800707#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Kim Phillips5be58f52010-07-14 19:47:18 -0500708#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200709#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
710#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500711#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200712#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500713#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200714#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500715#endif
Mingkai Hu07355702009-09-23 15:19:32 +0800716#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
717 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200718#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
Mingkai Hu07355702009-09-23 15:19:32 +0800719#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200720#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500721
722/*
723 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500724 * have to be in the first 64 MB of memory, since this is
Kumar Gala9490a7f2008-07-25 13:31:05 -0500725 * the maximum mapped by the Linux kernel during initialization.
726 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500727#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
728#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500729
Kumar Gala9490a7f2008-07-25 13:31:05 -0500730#if defined(CONFIG_CMD_KGDB)
731#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
732#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
733#endif
734
735/*
736 * Environment Configuration
737 */
738
739/* The mac addresses for all ethernet interface */
740#if defined(CONFIG_TSEC_ENET)
741#define CONFIG_HAS_ETH0
742#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
743#define CONFIG_HAS_ETH1
744#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
745#define CONFIG_HAS_ETH2
746#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
747#define CONFIG_HAS_ETH3
748#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
749#endif
750
751#define CONFIG_IPADDR 192.168.1.254
752
753#define CONFIG_HOSTNAME unknown
754#define CONFIG_ROOTPATH /opt/nfsroot
755#define CONFIG_BOOTFILE uImage
Mingkai Hu07355702009-09-23 15:19:32 +0800756#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500757
758#define CONFIG_SERVERIP 192.168.1.1
759#define CONFIG_GATEWAYIP 192.168.1.1
760#define CONFIG_NETMASK 255.255.255.0
761
762/* default location for tftp and bootm */
763#define CONFIG_LOADADDR 1000000
764
765#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
766#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
767
768#define CONFIG_BAUDRATE 115200
769
770#define CONFIG_EXTRA_ENV_SETTINGS \
771 "netdev=eth0\0" \
772 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
773 "tftpflash=tftpboot $loadaddr $uboot; " \
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200774 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
775 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
776 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
777 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
778 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
Kumar Gala9490a7f2008-07-25 13:31:05 -0500779 "consoledev=ttyS0\0" \
780 "ramdiskaddr=2000000\0" \
781 "ramdiskfile=8536ds/ramdisk.uboot\0" \
782 "fdtaddr=c00000\0" \
783 "fdtfile=8536ds/mpc8536ds.dtb\0" \
Vivek Mahajan4bc6eb72009-05-25 17:23:18 +0530784 "bdev=sda3\0" \
785 "usb_phy_type=ulpi\0"
Kumar Gala9490a7f2008-07-25 13:31:05 -0500786
787#define CONFIG_HDBOOT \
788 "setenv bootargs root=/dev/$bdev rw " \
789 "console=$consoledev,$baudrate $othbootargs;" \
790 "tftp $loadaddr $bootfile;" \
791 "tftp $fdtaddr $fdtfile;" \
792 "bootm $loadaddr - $fdtaddr"
793
794#define CONFIG_NFSBOOTCOMMAND \
795 "setenv bootargs root=/dev/nfs rw " \
796 "nfsroot=$serverip:$rootpath " \
797 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
798 "console=$consoledev,$baudrate $othbootargs;" \
799 "tftp $loadaddr $bootfile;" \
800 "tftp $fdtaddr $fdtfile;" \
801 "bootm $loadaddr - $fdtaddr"
802
803#define CONFIG_RAMBOOTCOMMAND \
804 "setenv bootargs root=/dev/ram rw " \
805 "console=$consoledev,$baudrate $othbootargs;" \
806 "tftp $ramdiskaddr $ramdiskfile;" \
807 "tftp $loadaddr $bootfile;" \
808 "tftp $fdtaddr $fdtfile;" \
809 "bootm $loadaddr $ramdiskaddr $fdtaddr"
810
811#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
812
813#endif /* __CONFIG_H */