Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 1 | /* |
Jerry Huang | d621da0 | 2011-01-06 23:42:19 -0600 | [diff] [blame] | 2 | * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 3 | * Andy Fleming |
| 4 | * |
| 5 | * Based vaguely on the pxa mmc code: |
| 6 | * (C) Copyright 2003 |
| 7 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
| 8 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 9 | * SPDX-License-Identifier: GPL-2.0+ |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #include <config.h> |
| 13 | #include <common.h> |
| 14 | #include <command.h> |
Jaehoon Chung | 915ffa5 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 15 | #include <errno.h> |
Anton Vorontsov | b33433a | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 16 | #include <hwconfig.h> |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 17 | #include <mmc.h> |
| 18 | #include <part.h> |
Peng Fan | 4483b7e | 2017-06-12 17:50:54 +0800 | [diff] [blame] | 19 | #include <power/regulator.h> |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 20 | #include <malloc.h> |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 21 | #include <fsl_esdhc.h> |
Anton Vorontsov | b33433a | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 22 | #include <fdt_support.h> |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 23 | #include <asm/io.h> |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 24 | #include <dm.h> |
| 25 | #include <asm-generic/gpio.h> |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 26 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 27 | DECLARE_GLOBAL_DATA_PTR; |
| 28 | |
Ye.Li | a3d6e38 | 2014-11-04 15:35:49 +0800 | [diff] [blame] | 29 | #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ |
| 30 | IRQSTATEN_CINT | \ |
| 31 | IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ |
| 32 | IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ |
| 33 | IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ |
| 34 | IRQSTATEN_DINT) |
| 35 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 36 | struct fsl_esdhc { |
Haijun.Zhang | 511948b | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 37 | uint dsaddr; /* SDMA system address register */ |
| 38 | uint blkattr; /* Block attributes register */ |
| 39 | uint cmdarg; /* Command argument register */ |
| 40 | uint xfertyp; /* Transfer type register */ |
| 41 | uint cmdrsp0; /* Command response 0 register */ |
| 42 | uint cmdrsp1; /* Command response 1 register */ |
| 43 | uint cmdrsp2; /* Command response 2 register */ |
| 44 | uint cmdrsp3; /* Command response 3 register */ |
| 45 | uint datport; /* Buffer data port register */ |
| 46 | uint prsstat; /* Present state register */ |
| 47 | uint proctl; /* Protocol control register */ |
| 48 | uint sysctl; /* System Control Register */ |
| 49 | uint irqstat; /* Interrupt status register */ |
| 50 | uint irqstaten; /* Interrupt status enable register */ |
| 51 | uint irqsigen; /* Interrupt signal enable register */ |
| 52 | uint autoc12err; /* Auto CMD error status register */ |
| 53 | uint hostcapblt; /* Host controller capabilities register */ |
| 54 | uint wml; /* Watermark level register */ |
| 55 | uint mixctrl; /* For USDHC */ |
| 56 | char reserved1[4]; /* reserved */ |
| 57 | uint fevt; /* Force event register */ |
| 58 | uint admaes; /* ADMA error status register */ |
| 59 | uint adsaddr; /* ADMA system address register */ |
Peng Fan | f53225c | 2016-06-15 10:53:00 +0800 | [diff] [blame] | 60 | char reserved2[4]; |
| 61 | uint dllctrl; |
| 62 | uint dllstat; |
| 63 | uint clktunectrlstatus; |
Peng Fan | 59d3782 | 2018-01-21 19:00:22 +0800 | [diff] [blame^] | 64 | char reserved3[4]; |
| 65 | uint strobe_dllctrl; |
| 66 | uint strobe_dllstat; |
| 67 | char reserved4[72]; |
Peng Fan | f53225c | 2016-06-15 10:53:00 +0800 | [diff] [blame] | 68 | uint vendorspec; |
| 69 | uint mmcboot; |
| 70 | uint vendorspec2; |
Peng Fan | 59d3782 | 2018-01-21 19:00:22 +0800 | [diff] [blame^] | 71 | uint tuning_ctrl; /* on i.MX6/7/8 */ |
| 72 | char reserved5[44]; |
Haijun.Zhang | 511948b | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 73 | uint hostver; /* Host controller version register */ |
Otavio Salvador | f022d36 | 2015-02-17 10:42:43 -0200 | [diff] [blame] | 74 | char reserved6[4]; /* reserved */ |
Peng Fan | 59d3782 | 2018-01-21 19:00:22 +0800 | [diff] [blame^] | 75 | uint dmaerraddr; /* DMA error address register */ |
Peng Fan | f53225c | 2016-06-15 10:53:00 +0800 | [diff] [blame] | 76 | char reserved7[4]; /* reserved */ |
Peng Fan | 59d3782 | 2018-01-21 19:00:22 +0800 | [diff] [blame^] | 77 | uint dmaerrattr; /* DMA error attribute register */ |
| 78 | char reserved8[4]; /* reserved */ |
Haijun.Zhang | 511948b | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 79 | uint hostcapblt2; /* Host controller capabilities register 2 */ |
Peng Fan | 59d3782 | 2018-01-21 19:00:22 +0800 | [diff] [blame^] | 80 | char reserved9[8]; /* reserved */ |
Haijun.Zhang | 511948b | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 81 | uint tcr; /* Tuning control register */ |
Peng Fan | 59d3782 | 2018-01-21 19:00:22 +0800 | [diff] [blame^] | 82 | char reserved10[28]; /* reserved */ |
Haijun.Zhang | 511948b | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 83 | uint sddirctl; /* SD direction control register */ |
Peng Fan | 59d3782 | 2018-01-21 19:00:22 +0800 | [diff] [blame^] | 84 | char reserved11[712];/* reserved */ |
Haijun.Zhang | 511948b | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 85 | uint scr; /* eSDHC control register */ |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 86 | }; |
| 87 | |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 88 | struct fsl_esdhc_plat { |
| 89 | struct mmc_config cfg; |
| 90 | struct mmc mmc; |
| 91 | }; |
| 92 | |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 93 | /** |
| 94 | * struct fsl_esdhc_priv |
| 95 | * |
| 96 | * @esdhc_regs: registers of the sdhc controller |
| 97 | * @sdhc_clk: Current clk of the sdhc controller |
| 98 | * @bus_width: bus width, 1bit, 4bit or 8bit |
| 99 | * @cfg: mmc config |
| 100 | * @mmc: mmc |
| 101 | * Following is used when Driver Model is enabled for MMC |
| 102 | * @dev: pointer for the device |
| 103 | * @non_removable: 0: removable; 1: non-removable |
Peng Fan | 1483151 | 2016-06-15 10:53:02 +0800 | [diff] [blame] | 104 | * @wp_enable: 1: enable checking wp; 0: no check |
Peng Fan | 32a9179 | 2017-06-12 17:50:53 +0800 | [diff] [blame] | 105 | * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 106 | * @cd_gpio: gpio for card detection |
Peng Fan | 1483151 | 2016-06-15 10:53:02 +0800 | [diff] [blame] | 107 | * @wp_gpio: gpio for write protection |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 108 | */ |
| 109 | struct fsl_esdhc_priv { |
| 110 | struct fsl_esdhc *esdhc_regs; |
| 111 | unsigned int sdhc_clk; |
| 112 | unsigned int bus_width; |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 113 | #if !CONFIG_IS_ENABLED(BLK) |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 114 | struct mmc *mmc; |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 115 | #endif |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 116 | struct udevice *dev; |
| 117 | int non_removable; |
Peng Fan | 1483151 | 2016-06-15 10:53:02 +0800 | [diff] [blame] | 118 | int wp_enable; |
Peng Fan | 32a9179 | 2017-06-12 17:50:53 +0800 | [diff] [blame] | 119 | int vs18_enable; |
Yangbo Lu | fc8048a | 2016-12-07 11:54:30 +0800 | [diff] [blame] | 120 | #ifdef CONFIG_DM_GPIO |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 121 | struct gpio_desc cd_gpio; |
Peng Fan | 1483151 | 2016-06-15 10:53:02 +0800 | [diff] [blame] | 122 | struct gpio_desc wp_gpio; |
Yangbo Lu | fc8048a | 2016-12-07 11:54:30 +0800 | [diff] [blame] | 123 | #endif |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 124 | }; |
| 125 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 126 | /* Return the XFERTYP flags for a given command and data packet */ |
Kim Phillips | eafa90a | 2012-10-29 13:34:44 +0000 | [diff] [blame] | 127 | static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 128 | { |
| 129 | uint xfertyp = 0; |
| 130 | |
| 131 | if (data) { |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 132 | xfertyp |= XFERTYP_DPSEL; |
| 133 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
| 134 | xfertyp |= XFERTYP_DMAEN; |
| 135 | #endif |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 136 | if (data->blocks > 1) { |
| 137 | xfertyp |= XFERTYP_MSBSEL; |
| 138 | xfertyp |= XFERTYP_BCEN; |
Jerry Huang | d621da0 | 2011-01-06 23:42:19 -0600 | [diff] [blame] | 139 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 140 | xfertyp |= XFERTYP_AC12EN; |
| 141 | #endif |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 142 | } |
| 143 | |
| 144 | if (data->flags & MMC_DATA_READ) |
| 145 | xfertyp |= XFERTYP_DTDSEL; |
| 146 | } |
| 147 | |
| 148 | if (cmd->resp_type & MMC_RSP_CRC) |
| 149 | xfertyp |= XFERTYP_CCCEN; |
| 150 | if (cmd->resp_type & MMC_RSP_OPCODE) |
| 151 | xfertyp |= XFERTYP_CICEN; |
| 152 | if (cmd->resp_type & MMC_RSP_136) |
| 153 | xfertyp |= XFERTYP_RSPTYP_136; |
| 154 | else if (cmd->resp_type & MMC_RSP_BUSY) |
| 155 | xfertyp |= XFERTYP_RSPTYP_48_BUSY; |
| 156 | else if (cmd->resp_type & MMC_RSP_PRESENT) |
| 157 | xfertyp |= XFERTYP_RSPTYP_48; |
| 158 | |
Jason Liu | 4571de3 | 2011-03-22 01:32:31 +0000 | [diff] [blame] | 159 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
| 160 | xfertyp |= XFERTYP_CMDTYP_ABORT; |
Yangbo Lu | 2550344 | 2016-01-21 17:33:19 +0800 | [diff] [blame] | 161 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 162 | return XFERTYP_CMD(cmd->cmdidx) | xfertyp; |
| 163 | } |
| 164 | |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 165 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
| 166 | /* |
| 167 | * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. |
| 168 | */ |
Simon Glass | 09b465f | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 169 | static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv, |
| 170 | struct mmc_data *data) |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 171 | { |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 172 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 173 | uint blocks; |
| 174 | char *buffer; |
| 175 | uint databuf; |
| 176 | uint size; |
| 177 | uint irqstat; |
Benoît Thébaudeau | bcfb365 | 2017-10-29 22:08:58 +0100 | [diff] [blame] | 178 | ulong start; |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 179 | |
| 180 | if (data->flags & MMC_DATA_READ) { |
| 181 | blocks = data->blocks; |
| 182 | buffer = data->dest; |
| 183 | while (blocks) { |
Benoît Thébaudeau | bcfb365 | 2017-10-29 22:08:58 +0100 | [diff] [blame] | 184 | start = get_timer(0); |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 185 | size = data->blocksize; |
| 186 | irqstat = esdhc_read32(®s->irqstat); |
Benoît Thébaudeau | bcfb365 | 2017-10-29 22:08:58 +0100 | [diff] [blame] | 187 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) { |
| 188 | if (get_timer(start) > PIO_TIMEOUT) { |
| 189 | printf("\nData Read Failed in PIO Mode."); |
| 190 | return; |
| 191 | } |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 192 | } |
| 193 | while (size && (!(irqstat & IRQSTAT_TC))) { |
| 194 | udelay(100); /* Wait before last byte transfer complete */ |
| 195 | irqstat = esdhc_read32(®s->irqstat); |
| 196 | databuf = in_le32(®s->datport); |
| 197 | *((uint *)buffer) = databuf; |
| 198 | buffer += 4; |
| 199 | size -= 4; |
| 200 | } |
| 201 | blocks--; |
| 202 | } |
| 203 | } else { |
| 204 | blocks = data->blocks; |
Wolfgang Denk | 7b43db9 | 2010-05-09 23:52:59 +0200 | [diff] [blame] | 205 | buffer = (char *)data->src; |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 206 | while (blocks) { |
Benoît Thébaudeau | bcfb365 | 2017-10-29 22:08:58 +0100 | [diff] [blame] | 207 | start = get_timer(0); |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 208 | size = data->blocksize; |
| 209 | irqstat = esdhc_read32(®s->irqstat); |
Benoît Thébaudeau | bcfb365 | 2017-10-29 22:08:58 +0100 | [diff] [blame] | 210 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) { |
| 211 | if (get_timer(start) > PIO_TIMEOUT) { |
| 212 | printf("\nData Write Failed in PIO Mode."); |
| 213 | return; |
| 214 | } |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 215 | } |
| 216 | while (size && (!(irqstat & IRQSTAT_TC))) { |
| 217 | udelay(100); /* Wait before last byte transfer complete */ |
| 218 | databuf = *((uint *)buffer); |
| 219 | buffer += 4; |
| 220 | size -= 4; |
| 221 | irqstat = esdhc_read32(®s->irqstat); |
| 222 | out_le32(®s->datport, databuf); |
| 223 | } |
| 224 | blocks--; |
| 225 | } |
| 226 | } |
| 227 | } |
| 228 | #endif |
| 229 | |
Simon Glass | 09b465f | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 230 | static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, |
| 231 | struct mmc_data *data) |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 232 | { |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 233 | int timeout; |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 234 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Peng Fan | eec2d43 | 2018-01-10 13:20:40 +0800 | [diff] [blame] | 235 | #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ |
| 236 | defined(CONFIG_MX8M) |
Yangbo Lu | 8b06460 | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 237 | dma_addr_t addr; |
| 238 | #endif |
Wolfgang Denk | 7b43db9 | 2010-05-09 23:52:59 +0200 | [diff] [blame] | 239 | uint wml_value; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 240 | |
| 241 | wml_value = data->blocksize/4; |
| 242 | |
| 243 | if (data->flags & MMC_DATA_READ) { |
Priyanka Jain | 32c8cfb | 2011-02-09 09:24:10 +0530 | [diff] [blame] | 244 | if (wml_value > WML_RD_WML_MAX) |
| 245 | wml_value = WML_RD_WML_MAX_VAL; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 246 | |
Roy Zang | ab467c5 | 2010-02-09 18:23:33 +0800 | [diff] [blame] | 247 | esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); |
Ye.Li | 7168977 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 248 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
Peng Fan | eec2d43 | 2018-01-10 13:20:40 +0800 | [diff] [blame] | 249 | #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ |
| 250 | defined(CONFIG_MX8M) |
Yangbo Lu | 8b06460 | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 251 | addr = virt_to_phys((void *)(data->dest)); |
| 252 | if (upper_32_bits(addr)) |
| 253 | printf("Error found for upper 32 bits\n"); |
| 254 | else |
| 255 | esdhc_write32(®s->dsaddr, lower_32_bits(addr)); |
| 256 | #else |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 257 | esdhc_write32(®s->dsaddr, (u32)data->dest); |
Ye.Li | 7168977 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 258 | #endif |
Yangbo Lu | 8b06460 | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 259 | #endif |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 260 | } else { |
Ye.Li | 7168977 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 261 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
Eric Nelson | e576bd9 | 2012-04-25 14:28:48 +0000 | [diff] [blame] | 262 | flush_dcache_range((ulong)data->src, |
| 263 | (ulong)data->src+data->blocks |
| 264 | *data->blocksize); |
Ye.Li | 7168977 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 265 | #endif |
Priyanka Jain | 32c8cfb | 2011-02-09 09:24:10 +0530 | [diff] [blame] | 266 | if (wml_value > WML_WR_WML_MAX) |
| 267 | wml_value = WML_WR_WML_MAX_VAL; |
Peng Fan | 1483151 | 2016-06-15 10:53:02 +0800 | [diff] [blame] | 268 | if (priv->wp_enable) { |
| 269 | if ((esdhc_read32(®s->prsstat) & |
| 270 | PRSSTAT_WPSPL) == 0) { |
| 271 | printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); |
Jaehoon Chung | 915ffa5 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 272 | return -ETIMEDOUT; |
Peng Fan | 1483151 | 2016-06-15 10:53:02 +0800 | [diff] [blame] | 273 | } |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 274 | } |
Roy Zang | ab467c5 | 2010-02-09 18:23:33 +0800 | [diff] [blame] | 275 | |
| 276 | esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, |
| 277 | wml_value << 16); |
Ye.Li | 7168977 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 278 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
Peng Fan | eec2d43 | 2018-01-10 13:20:40 +0800 | [diff] [blame] | 279 | #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ |
| 280 | defined(CONFIG_MX8M) |
Yangbo Lu | 8b06460 | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 281 | addr = virt_to_phys((void *)(data->src)); |
| 282 | if (upper_32_bits(addr)) |
| 283 | printf("Error found for upper 32 bits\n"); |
| 284 | else |
| 285 | esdhc_write32(®s->dsaddr, lower_32_bits(addr)); |
| 286 | #else |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 287 | esdhc_write32(®s->dsaddr, (u32)data->src); |
Ye.Li | 7168977 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 288 | #endif |
Yangbo Lu | 8b06460 | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 289 | #endif |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 290 | } |
| 291 | |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 292 | esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 293 | |
| 294 | /* Calculate the timeout period for data transactions */ |
Priyanka Jain | b71ea33 | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 295 | /* |
| 296 | * 1)Timeout period = (2^(timeout+13)) SD Clock cycles |
| 297 | * 2)Timeout period should be minimum 0.250sec as per SD Card spec |
| 298 | * So, Number of SD Clock cycles for 0.25sec should be minimum |
| 299 | * (SD Clock/sec * 0.25 sec) SD Clock cycles |
Andrew Gabbasov | fb82398 | 2014-03-24 02:40:41 -0500 | [diff] [blame] | 300 | * = (mmc->clock * 1/4) SD Clock cycles |
Priyanka Jain | b71ea33 | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 301 | * As 1) >= 2) |
Andrew Gabbasov | fb82398 | 2014-03-24 02:40:41 -0500 | [diff] [blame] | 302 | * => (2^(timeout+13)) >= mmc->clock * 1/4 |
Priyanka Jain | b71ea33 | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 303 | * Taking log2 both the sides |
Andrew Gabbasov | fb82398 | 2014-03-24 02:40:41 -0500 | [diff] [blame] | 304 | * => timeout + 13 >= log2(mmc->clock/4) |
Priyanka Jain | b71ea33 | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 305 | * Rounding up to next power of 2 |
Andrew Gabbasov | fb82398 | 2014-03-24 02:40:41 -0500 | [diff] [blame] | 306 | * => timeout + 13 = log2(mmc->clock/4) + 1 |
| 307 | * => timeout + 13 = fls(mmc->clock/4) |
Yangbo Lu | e978a31 | 2015-12-30 14:19:30 +0800 | [diff] [blame] | 308 | * |
| 309 | * However, the MMC spec "It is strongly recommended for hosts to |
| 310 | * implement more than 500ms timeout value even if the card |
| 311 | * indicates the 250ms maximum busy length." Even the previous |
| 312 | * value of 300ms is known to be insufficient for some cards. |
| 313 | * So, we use |
| 314 | * => timeout + 13 = fls(mmc->clock/2) |
Priyanka Jain | b71ea33 | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 315 | */ |
Yangbo Lu | e978a31 | 2015-12-30 14:19:30 +0800 | [diff] [blame] | 316 | timeout = fls(mmc->clock/2); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 317 | timeout -= 13; |
| 318 | |
| 319 | if (timeout > 14) |
| 320 | timeout = 14; |
| 321 | |
| 322 | if (timeout < 0) |
| 323 | timeout = 0; |
| 324 | |
Kumar Gala | 5103a03 | 2011-01-29 15:36:10 -0600 | [diff] [blame] | 325 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
| 326 | if ((timeout == 4) || (timeout == 8) || (timeout == 12)) |
| 327 | timeout++; |
| 328 | #endif |
| 329 | |
Haijun.Zhang | 1336e2d | 2014-03-18 17:04:23 +0800 | [diff] [blame] | 330 | #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE |
| 331 | timeout = 0xE; |
| 332 | #endif |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 333 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 334 | |
| 335 | return 0; |
| 336 | } |
| 337 | |
Eric Nelson | e576bd9 | 2012-04-25 14:28:48 +0000 | [diff] [blame] | 338 | static void check_and_invalidate_dcache_range |
| 339 | (struct mmc_cmd *cmd, |
| 340 | struct mmc_data *data) { |
Yangbo Lu | 8b06460 | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 341 | unsigned start = 0; |
Yangbo Lu | cc634e2 | 2016-05-12 19:12:58 +0800 | [diff] [blame] | 342 | unsigned end = 0; |
Eric Nelson | e576bd9 | 2012-04-25 14:28:48 +0000 | [diff] [blame] | 343 | unsigned size = roundup(ARCH_DMA_MINALIGN, |
| 344 | data->blocks*data->blocksize); |
Peng Fan | eec2d43 | 2018-01-10 13:20:40 +0800 | [diff] [blame] | 345 | #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ |
| 346 | defined(CONFIG_MX8M) |
Yangbo Lu | 8b06460 | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 347 | dma_addr_t addr; |
| 348 | |
| 349 | addr = virt_to_phys((void *)(data->dest)); |
| 350 | if (upper_32_bits(addr)) |
| 351 | printf("Error found for upper 32 bits\n"); |
| 352 | else |
| 353 | start = lower_32_bits(addr); |
Yangbo Lu | cc634e2 | 2016-05-12 19:12:58 +0800 | [diff] [blame] | 354 | #else |
| 355 | start = (unsigned)data->dest; |
Yangbo Lu | 8b06460 | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 356 | #endif |
Yangbo Lu | cc634e2 | 2016-05-12 19:12:58 +0800 | [diff] [blame] | 357 | end = start + size; |
Eric Nelson | e576bd9 | 2012-04-25 14:28:48 +0000 | [diff] [blame] | 358 | invalidate_dcache_range(start, end); |
| 359 | } |
Tom Rini | 10dc777 | 2014-05-23 09:19:05 -0400 | [diff] [blame] | 360 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 361 | /* |
| 362 | * Sends a command out on the bus. Takes the mmc pointer, |
| 363 | * a command pointer, and an optional data pointer. |
| 364 | */ |
Simon Glass | 9586aa6 | 2017-07-29 11:35:18 -0600 | [diff] [blame] | 365 | static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, |
| 366 | struct mmc_cmd *cmd, struct mmc_data *data) |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 367 | { |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 368 | int err = 0; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 369 | uint xfertyp; |
| 370 | uint irqstat; |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 371 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 372 | |
Jerry Huang | d621da0 | 2011-01-06 23:42:19 -0600 | [diff] [blame] | 373 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 374 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
| 375 | return 0; |
| 376 | #endif |
| 377 | |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 378 | esdhc_write32(®s->irqstat, -1); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 379 | |
| 380 | sync(); |
| 381 | |
| 382 | /* Wait for the bus to be idle */ |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 383 | while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || |
| 384 | (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) |
| 385 | ; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 386 | |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 387 | while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) |
| 388 | ; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 389 | |
| 390 | /* Wait at least 8 SD clock cycles before the next command */ |
| 391 | /* |
| 392 | * Note: This is way more than 8 cycles, but 1ms seems to |
| 393 | * resolve timing issues with some cards |
| 394 | */ |
| 395 | udelay(1000); |
| 396 | |
| 397 | /* Set up for a data transfer if we have one */ |
| 398 | if (data) { |
Simon Glass | 09b465f | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 399 | err = esdhc_setup_data(priv, mmc, data); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 400 | if(err) |
| 401 | return err; |
Peng Fan | 4683b22 | 2015-06-25 10:32:26 +0800 | [diff] [blame] | 402 | |
| 403 | if (data->flags & MMC_DATA_READ) |
| 404 | check_and_invalidate_dcache_range(cmd, data); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 405 | } |
| 406 | |
| 407 | /* Figure out the transfer arguments */ |
| 408 | xfertyp = esdhc_xfertyp(cmd, data); |
| 409 | |
Andrew Gabbasov | 01b7735 | 2013-06-11 10:34:22 -0500 | [diff] [blame] | 410 | /* Mask all irqs */ |
| 411 | esdhc_write32(®s->irqsigen, 0); |
| 412 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 413 | /* Send the command */ |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 414 | esdhc_write32(®s->cmdarg, cmd->cmdarg); |
Jason Liu | 4692708 | 2011-11-25 00:18:04 +0000 | [diff] [blame] | 415 | #if defined(CONFIG_FSL_USDHC) |
| 416 | esdhc_write32(®s->mixctrl, |
Volodymyr Riazantsev | 0e1bf61 | 2015-01-20 10:16:44 -0500 | [diff] [blame] | 417 | (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) |
| 418 | | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); |
Jason Liu | 4692708 | 2011-11-25 00:18:04 +0000 | [diff] [blame] | 419 | esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); |
| 420 | #else |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 421 | esdhc_write32(®s->xfertyp, xfertyp); |
Jason Liu | 4692708 | 2011-11-25 00:18:04 +0000 | [diff] [blame] | 422 | #endif |
Dirk Behme | 7a5b802 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 423 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 424 | /* Wait for the command to complete */ |
Dirk Behme | 7a5b802 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 425 | while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 426 | ; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 427 | |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 428 | irqstat = esdhc_read32(®s->irqstat); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 429 | |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 430 | if (irqstat & CMD_ERR) { |
Jaehoon Chung | 915ffa5 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 431 | err = -ECOMM; |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 432 | goto out; |
Dirk Behme | 7a5b802 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 433 | } |
| 434 | |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 435 | if (irqstat & IRQSTAT_CTOE) { |
Jaehoon Chung | 915ffa5 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 436 | err = -ETIMEDOUT; |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 437 | goto out; |
| 438 | } |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 439 | |
Otavio Salvador | f022d36 | 2015-02-17 10:42:43 -0200 | [diff] [blame] | 440 | /* Switch voltage to 1.8V if CMD11 succeeded */ |
| 441 | if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { |
| 442 | esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); |
| 443 | |
| 444 | printf("Run CMD11 1.8V switch\n"); |
| 445 | /* Sleep for 5 ms - max time for card to switch to 1.8V */ |
| 446 | udelay(5000); |
| 447 | } |
| 448 | |
Dirk Behme | 7a5b802 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 449 | /* Workaround for ESDHC errata ENGcm03648 */ |
| 450 | if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { |
Yangbo Lu | 253d5bd | 2015-04-15 10:13:12 +0800 | [diff] [blame] | 451 | int timeout = 6000; |
Dirk Behme | 7a5b802 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 452 | |
Yangbo Lu | 253d5bd | 2015-04-15 10:13:12 +0800 | [diff] [blame] | 453 | /* Poll on DATA0 line for cmd with busy signal for 600 ms */ |
Dirk Behme | 7a5b802 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 454 | while (timeout > 0 && !(esdhc_read32(®s->prsstat) & |
| 455 | PRSSTAT_DAT0)) { |
| 456 | udelay(100); |
| 457 | timeout--; |
| 458 | } |
| 459 | |
| 460 | if (timeout <= 0) { |
| 461 | printf("Timeout waiting for DAT0 to go high!\n"); |
Jaehoon Chung | 915ffa5 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 462 | err = -ETIMEDOUT; |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 463 | goto out; |
Dirk Behme | 7a5b802 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 464 | } |
| 465 | } |
| 466 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 467 | /* Copy the response to the response buffer */ |
| 468 | if (cmd->resp_type & MMC_RSP_136) { |
| 469 | u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; |
| 470 | |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 471 | cmdrsp3 = esdhc_read32(®s->cmdrsp3); |
| 472 | cmdrsp2 = esdhc_read32(®s->cmdrsp2); |
| 473 | cmdrsp1 = esdhc_read32(®s->cmdrsp1); |
| 474 | cmdrsp0 = esdhc_read32(®s->cmdrsp0); |
Rabin Vincent | 998be3d | 2009-04-05 13:30:56 +0530 | [diff] [blame] | 475 | cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); |
| 476 | cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); |
| 477 | cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); |
| 478 | cmd->response[3] = (cmdrsp0 << 8); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 479 | } else |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 480 | cmd->response[0] = esdhc_read32(®s->cmdrsp0); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 481 | |
| 482 | /* Wait until all of the blocks are transferred */ |
| 483 | if (data) { |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 484 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
Simon Glass | 09b465f | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 485 | esdhc_pio_read_write(priv, data); |
Dipen Dudhat | 77c1458 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 486 | #else |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 487 | do { |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 488 | irqstat = esdhc_read32(®s->irqstat); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 489 | |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 490 | if (irqstat & IRQSTAT_DTOE) { |
Jaehoon Chung | 915ffa5 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 491 | err = -ETIMEDOUT; |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 492 | goto out; |
| 493 | } |
Frans Meulenbroeks | 63fb5a7 | 2010-07-31 04:45:18 +0000 | [diff] [blame] | 494 | |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 495 | if (irqstat & DATA_ERR) { |
Jaehoon Chung | 915ffa5 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 496 | err = -ECOMM; |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 497 | goto out; |
| 498 | } |
Andrew Gabbasov | 9b74dc5 | 2013-04-07 23:06:08 +0000 | [diff] [blame] | 499 | } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); |
Ye.Li | 7168977 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 500 | |
Peng Fan | 4683b22 | 2015-06-25 10:32:26 +0800 | [diff] [blame] | 501 | /* |
| 502 | * Need invalidate the dcache here again to avoid any |
| 503 | * cache-fill during the DMA operations such as the |
| 504 | * speculative pre-fetching etc. |
| 505 | */ |
Eric Nelson | 54899fc | 2013-04-03 12:31:56 +0000 | [diff] [blame] | 506 | if (data->flags & MMC_DATA_READ) |
| 507 | check_and_invalidate_dcache_range(cmd, data); |
Ye.Li | 7168977 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 508 | #endif |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 509 | } |
| 510 | |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 511 | out: |
| 512 | /* Reset CMD and DATA portions on error */ |
| 513 | if (err) { |
| 514 | esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | |
| 515 | SYSCTL_RSTC); |
| 516 | while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) |
| 517 | ; |
| 518 | |
| 519 | if (data) { |
| 520 | esdhc_write32(®s->sysctl, |
| 521 | esdhc_read32(®s->sysctl) | |
| 522 | SYSCTL_RSTD); |
| 523 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) |
| 524 | ; |
| 525 | } |
Otavio Salvador | f022d36 | 2015-02-17 10:42:43 -0200 | [diff] [blame] | 526 | |
| 527 | /* If this was CMD11, then notify that power cycle is needed */ |
| 528 | if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) |
| 529 | printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 530 | } |
| 531 | |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 532 | esdhc_write32(®s->irqstat, -1); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 533 | |
Andrew Gabbasov | 8a57302 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 534 | return err; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 535 | } |
| 536 | |
Simon Glass | 09b465f | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 537 | static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 538 | { |
Benoît Thébaudeau | b9b4f14 | 2018-01-16 22:44:18 +0100 | [diff] [blame] | 539 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Benoît Thébaudeau | 4f42528 | 2017-05-03 11:59:03 +0200 | [diff] [blame] | 540 | int div = 1; |
| 541 | #ifdef ARCH_MXC |
Benoît Thébaudeau | b9b4f14 | 2018-01-16 22:44:18 +0100 | [diff] [blame] | 542 | #ifdef CONFIG_MX53 |
| 543 | /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ |
| 544 | int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1; |
| 545 | #else |
Benoît Thébaudeau | 4f42528 | 2017-05-03 11:59:03 +0200 | [diff] [blame] | 546 | int pre_div = 1; |
Benoît Thébaudeau | b9b4f14 | 2018-01-16 22:44:18 +0100 | [diff] [blame] | 547 | #endif |
Benoît Thébaudeau | 4f42528 | 2017-05-03 11:59:03 +0200 | [diff] [blame] | 548 | #else |
| 549 | int pre_div = 2; |
| 550 | #endif |
| 551 | int ddr_pre_div = mmc->ddr_mode ? 2 : 1; |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 552 | int sdhc_clk = priv->sdhc_clk; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 553 | uint clk; |
| 554 | |
Pantelis Antoniou | 93bfd61 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 555 | if (clock < mmc->cfg->f_min) |
| 556 | clock = mmc->cfg->f_min; |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 557 | |
Benoît Thébaudeau | 4f42528 | 2017-05-03 11:59:03 +0200 | [diff] [blame] | 558 | while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) |
| 559 | pre_div *= 2; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 560 | |
Benoît Thébaudeau | 4f42528 | 2017-05-03 11:59:03 +0200 | [diff] [blame] | 561 | while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) |
| 562 | div++; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 563 | |
Benoît Thébaudeau | 4f42528 | 2017-05-03 11:59:03 +0200 | [diff] [blame] | 564 | pre_div >>= 1; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 565 | div -= 1; |
| 566 | |
| 567 | clk = (pre_div << 8) | (div << 4); |
| 568 | |
Eric Nelson | f0b5f23 | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 569 | #ifdef CONFIG_FSL_USDHC |
Ye Li | 84ecdf6 | 2016-06-15 10:53:01 +0800 | [diff] [blame] | 570 | esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); |
Eric Nelson | f0b5f23 | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 571 | #else |
Kumar Gala | cc4d122 | 2010-03-18 15:51:05 -0500 | [diff] [blame] | 572 | esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); |
Eric Nelson | f0b5f23 | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 573 | #endif |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 574 | |
| 575 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 576 | |
| 577 | udelay(10000); |
| 578 | |
Eric Nelson | f0b5f23 | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 579 | #ifdef CONFIG_FSL_USDHC |
Ye Li | 84ecdf6 | 2016-06-15 10:53:01 +0800 | [diff] [blame] | 580 | esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); |
Eric Nelson | f0b5f23 | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 581 | #else |
| 582 | esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); |
| 583 | #endif |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 584 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 585 | } |
| 586 | |
Yangbo Lu | 2d9ca2c | 2015-04-22 13:57:40 +0800 | [diff] [blame] | 587 | #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
Simon Glass | 09b465f | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 588 | static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable) |
Yangbo Lu | 2d9ca2c | 2015-04-22 13:57:40 +0800 | [diff] [blame] | 589 | { |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 590 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Yangbo Lu | 2d9ca2c | 2015-04-22 13:57:40 +0800 | [diff] [blame] | 591 | u32 value; |
| 592 | u32 time_out; |
| 593 | |
| 594 | value = esdhc_read32(®s->sysctl); |
| 595 | |
| 596 | if (enable) |
| 597 | value |= SYSCTL_CKEN; |
| 598 | else |
| 599 | value &= ~SYSCTL_CKEN; |
| 600 | |
| 601 | esdhc_write32(®s->sysctl, value); |
| 602 | |
| 603 | time_out = 20; |
| 604 | value = PRSSTAT_SDSTB; |
| 605 | while (!(esdhc_read32(®s->prsstat) & value)) { |
| 606 | if (time_out == 0) { |
| 607 | printf("fsl_esdhc: Internal clock never stabilised.\n"); |
| 608 | break; |
| 609 | } |
| 610 | time_out--; |
| 611 | mdelay(1); |
| 612 | } |
| 613 | } |
| 614 | #endif |
| 615 | |
Simon Glass | 9586aa6 | 2017-07-29 11:35:18 -0600 | [diff] [blame] | 616 | static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 617 | { |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 618 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 619 | |
Yangbo Lu | 2d9ca2c | 2015-04-22 13:57:40 +0800 | [diff] [blame] | 620 | #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
| 621 | /* Select to use peripheral clock */ |
Simon Glass | 09b465f | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 622 | esdhc_clock_control(priv, false); |
Yangbo Lu | 2d9ca2c | 2015-04-22 13:57:40 +0800 | [diff] [blame] | 623 | esdhc_setbits32(®s->scr, ESDHCCTL_PCS); |
Simon Glass | 09b465f | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 624 | esdhc_clock_control(priv, true); |
Yangbo Lu | 2d9ca2c | 2015-04-22 13:57:40 +0800 | [diff] [blame] | 625 | #endif |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 626 | /* Set the clock speed */ |
Simon Glass | 09b465f | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 627 | set_sysctl(priv, mmc, mmc->clock); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 628 | |
| 629 | /* Set the bus width */ |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 630 | esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 631 | |
| 632 | if (mmc->bus_width == 4) |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 633 | esdhc_setbits32(®s->proctl, PROCTL_DTW_4); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 634 | else if (mmc->bus_width == 8) |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 635 | esdhc_setbits32(®s->proctl, PROCTL_DTW_8); |
| 636 | |
Jaehoon Chung | 07b0b9c | 2016-12-30 15:30:16 +0900 | [diff] [blame] | 637 | return 0; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 638 | } |
| 639 | |
Simon Glass | 9586aa6 | 2017-07-29 11:35:18 -0600 | [diff] [blame] | 640 | static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 641 | { |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 642 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Simon Glass | 201e828 | 2017-07-29 11:35:20 -0600 | [diff] [blame] | 643 | ulong start; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 644 | |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 645 | /* Reset the entire host controller */ |
Dirk Behme | a61da72 | 2013-07-15 15:44:29 +0200 | [diff] [blame] | 646 | esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 647 | |
| 648 | /* Wait until the controller is available */ |
Simon Glass | 201e828 | 2017-07-29 11:35:20 -0600 | [diff] [blame] | 649 | start = get_timer(0); |
| 650 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) { |
| 651 | if (get_timer(start) > 1000) |
| 652 | return -ETIMEDOUT; |
| 653 | } |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 654 | |
Peng Fan | f53225c | 2016-06-15 10:53:00 +0800 | [diff] [blame] | 655 | #if defined(CONFIG_FSL_USDHC) |
| 656 | /* RSTA doesn't reset MMC_BOOT register, so manually reset it */ |
| 657 | esdhc_write32(®s->mmcboot, 0x0); |
| 658 | /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */ |
| 659 | esdhc_write32(®s->mixctrl, 0x0); |
| 660 | esdhc_write32(®s->clktunectrlstatus, 0x0); |
| 661 | |
| 662 | /* Put VEND_SPEC to default value */ |
Peng Fan | db359ef | 2018-01-02 16:51:22 +0800 | [diff] [blame] | 663 | if (priv->vs18_enable) |
| 664 | esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT | |
| 665 | ESDHC_VENDORSPEC_VSELECT)); |
| 666 | else |
| 667 | esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); |
Peng Fan | f53225c | 2016-06-15 10:53:00 +0800 | [diff] [blame] | 668 | |
| 669 | /* Disable DLL_CTRL delay line */ |
| 670 | esdhc_write32(®s->dllctrl, 0x0); |
| 671 | #endif |
| 672 | |
Benoît Thébaudeau | 16e43f3 | 2012-08-13 07:28:16 +0000 | [diff] [blame] | 673 | #ifndef ARCH_MXC |
P.V.Suresh | 2c1764e | 2010-12-04 10:37:23 +0530 | [diff] [blame] | 674 | /* Enable cache snooping */ |
Benoît Thébaudeau | 16e43f3 | 2012-08-13 07:28:16 +0000 | [diff] [blame] | 675 | esdhc_write32(®s->scr, 0x00000040); |
| 676 | #endif |
P.V.Suresh | 2c1764e | 2010-12-04 10:37:23 +0530 | [diff] [blame] | 677 | |
Eric Nelson | f0b5f23 | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 678 | #ifndef CONFIG_FSL_USDHC |
Dirk Behme | a61da72 | 2013-07-15 15:44:29 +0200 | [diff] [blame] | 679 | esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); |
Ye Li | 84ecdf6 | 2016-06-15 10:53:01 +0800 | [diff] [blame] | 680 | #else |
| 681 | esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); |
Eric Nelson | f0b5f23 | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 682 | #endif |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 683 | |
| 684 | /* Set the initial clock speed */ |
Kishon Vijay Abraham I | 35f6782 | 2017-09-21 16:30:03 +0200 | [diff] [blame] | 685 | mmc_set_clock(mmc, 400000, false); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 686 | |
| 687 | /* Disable the BRR and BWR bits in IRQSTAT */ |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 688 | esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 689 | |
| 690 | /* Put the PROCTL reg back to the default */ |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 691 | esdhc_write32(®s->proctl, PROCTL_INIT); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 692 | |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 693 | /* Set timout to the maximum value */ |
| 694 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 695 | |
Thierry Reding | d48d2e2 | 2012-01-02 01:15:38 +0000 | [diff] [blame] | 696 | return 0; |
| 697 | } |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 698 | |
Simon Glass | 9586aa6 | 2017-07-29 11:35:18 -0600 | [diff] [blame] | 699 | static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) |
Thierry Reding | d48d2e2 | 2012-01-02 01:15:38 +0000 | [diff] [blame] | 700 | { |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 701 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Thierry Reding | d48d2e2 | 2012-01-02 01:15:38 +0000 | [diff] [blame] | 702 | int timeout = 1000; |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 703 | |
Haijun.Zhang | f7e27cc | 2014-01-10 13:52:17 +0800 | [diff] [blame] | 704 | #ifdef CONFIG_ESDHC_DETECT_QUIRK |
| 705 | if (CONFIG_ESDHC_DETECT_QUIRK) |
| 706 | return 1; |
| 707 | #endif |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 708 | |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 709 | #if CONFIG_IS_ENABLED(DM_MMC) |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 710 | if (priv->non_removable) |
| 711 | return 1; |
Yangbo Lu | fc8048a | 2016-12-07 11:54:30 +0800 | [diff] [blame] | 712 | #ifdef CONFIG_DM_GPIO |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 713 | if (dm_gpio_is_valid(&priv->cd_gpio)) |
| 714 | return dm_gpio_get_value(&priv->cd_gpio); |
| 715 | #endif |
Yangbo Lu | fc8048a | 2016-12-07 11:54:30 +0800 | [diff] [blame] | 716 | #endif |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 717 | |
Thierry Reding | d48d2e2 | 2012-01-02 01:15:38 +0000 | [diff] [blame] | 718 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) |
| 719 | udelay(1000); |
| 720 | |
| 721 | return timeout > 0; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 722 | } |
| 723 | |
Simon Glass | 446e077 | 2017-07-29 11:35:19 -0600 | [diff] [blame] | 724 | static int esdhc_reset(struct fsl_esdhc *regs) |
Jerry Huang | 48bb3bb | 2010-03-18 15:57:06 -0500 | [diff] [blame] | 725 | { |
Simon Glass | 446e077 | 2017-07-29 11:35:19 -0600 | [diff] [blame] | 726 | ulong start; |
Jerry Huang | 48bb3bb | 2010-03-18 15:57:06 -0500 | [diff] [blame] | 727 | |
| 728 | /* reset the controller */ |
Dirk Behme | a61da72 | 2013-07-15 15:44:29 +0200 | [diff] [blame] | 729 | esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); |
Jerry Huang | 48bb3bb | 2010-03-18 15:57:06 -0500 | [diff] [blame] | 730 | |
| 731 | /* hardware clears the bit when it is done */ |
Simon Glass | 446e077 | 2017-07-29 11:35:19 -0600 | [diff] [blame] | 732 | start = get_timer(0); |
| 733 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) { |
| 734 | if (get_timer(start) > 100) { |
| 735 | printf("MMC/SD: Reset never completed.\n"); |
| 736 | return -ETIMEDOUT; |
| 737 | } |
| 738 | } |
| 739 | |
| 740 | return 0; |
Jerry Huang | 48bb3bb | 2010-03-18 15:57:06 -0500 | [diff] [blame] | 741 | } |
| 742 | |
Simon Glass | e7881d8 | 2017-07-29 11:35:31 -0600 | [diff] [blame] | 743 | #if !CONFIG_IS_ENABLED(DM_MMC) |
Simon Glass | 9586aa6 | 2017-07-29 11:35:18 -0600 | [diff] [blame] | 744 | static int esdhc_getcd(struct mmc *mmc) |
| 745 | { |
| 746 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 747 | |
| 748 | return esdhc_getcd_common(priv); |
| 749 | } |
| 750 | |
| 751 | static int esdhc_init(struct mmc *mmc) |
| 752 | { |
| 753 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 754 | |
| 755 | return esdhc_init_common(priv, mmc); |
| 756 | } |
| 757 | |
| 758 | static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
| 759 | struct mmc_data *data) |
| 760 | { |
| 761 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 762 | |
| 763 | return esdhc_send_cmd_common(priv, mmc, cmd, data); |
| 764 | } |
| 765 | |
| 766 | static int esdhc_set_ios(struct mmc *mmc) |
| 767 | { |
| 768 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 769 | |
| 770 | return esdhc_set_ios_common(priv, mmc); |
| 771 | } |
| 772 | |
Pantelis Antoniou | ab769f2 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 773 | static const struct mmc_ops esdhc_ops = { |
Simon Glass | 9586aa6 | 2017-07-29 11:35:18 -0600 | [diff] [blame] | 774 | .getcd = esdhc_getcd, |
| 775 | .init = esdhc_init, |
Pantelis Antoniou | ab769f2 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 776 | .send_cmd = esdhc_send_cmd, |
| 777 | .set_ios = esdhc_set_ios, |
Pantelis Antoniou | ab769f2 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 778 | }; |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 779 | #endif |
Pantelis Antoniou | ab769f2 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 780 | |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 781 | static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, |
| 782 | struct fsl_esdhc_plat *plat) |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 783 | { |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 784 | struct mmc_config *cfg; |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 785 | struct fsl_esdhc *regs; |
Li Yang | 030955c | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 786 | u32 caps, voltage_caps; |
Simon Glass | 446e077 | 2017-07-29 11:35:19 -0600 | [diff] [blame] | 787 | int ret; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 788 | |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 789 | if (!priv) |
| 790 | return -EINVAL; |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 791 | |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 792 | regs = priv->esdhc_regs; |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 793 | |
Jerry Huang | 48bb3bb | 2010-03-18 15:57:06 -0500 | [diff] [blame] | 794 | /* First reset the eSDHC controller */ |
Simon Glass | 446e077 | 2017-07-29 11:35:19 -0600 | [diff] [blame] | 795 | ret = esdhc_reset(regs); |
| 796 | if (ret) |
| 797 | return ret; |
Jerry Huang | 48bb3bb | 2010-03-18 15:57:06 -0500 | [diff] [blame] | 798 | |
Eric Nelson | f0b5f23 | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 799 | #ifndef CONFIG_FSL_USDHC |
Jerry Huang | 975324a | 2012-05-17 23:57:02 +0000 | [diff] [blame] | 800 | esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN |
| 801 | | SYSCTL_IPGEN | SYSCTL_CKEN); |
Ye Li | 84ecdf6 | 2016-06-15 10:53:01 +0800 | [diff] [blame] | 802 | #else |
| 803 | esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | |
| 804 | VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); |
Eric Nelson | f0b5f23 | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 805 | #endif |
Jerry Huang | 975324a | 2012-05-17 23:57:02 +0000 | [diff] [blame] | 806 | |
Peng Fan | 32a9179 | 2017-06-12 17:50:53 +0800 | [diff] [blame] | 807 | if (priv->vs18_enable) |
| 808 | esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); |
| 809 | |
Ye.Li | a3d6e38 | 2014-11-04 15:35:49 +0800 | [diff] [blame] | 810 | writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 811 | cfg = &plat->cfg; |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 812 | #ifndef CONFIG_DM_MMC |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 813 | memset(cfg, '\0', sizeof(*cfg)); |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 814 | #endif |
Pantelis Antoniou | 93bfd61 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 815 | |
Li Yang | 030955c | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 816 | voltage_caps = 0; |
Wang Huan | 19060bd | 2014-09-05 13:52:40 +0800 | [diff] [blame] | 817 | caps = esdhc_read32(®s->hostcapblt); |
Roy Zang | 3b4456e | 2011-01-07 00:06:47 -0600 | [diff] [blame] | 818 | |
| 819 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 |
| 820 | caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | |
| 821 | ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); |
| 822 | #endif |
Haijun.Zhang | ef38f3f | 2013-10-31 09:38:19 +0800 | [diff] [blame] | 823 | |
| 824 | /* T4240 host controller capabilities register should have VS33 bit */ |
| 825 | #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 |
| 826 | caps = caps | ESDHC_HOSTCAPBLT_VS33; |
| 827 | #endif |
| 828 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 829 | if (caps & ESDHC_HOSTCAPBLT_VS18) |
Li Yang | 030955c | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 830 | voltage_caps |= MMC_VDD_165_195; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 831 | if (caps & ESDHC_HOSTCAPBLT_VS30) |
Li Yang | 030955c | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 832 | voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 833 | if (caps & ESDHC_HOSTCAPBLT_VS33) |
Li Yang | 030955c | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 834 | voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; |
| 835 | |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 836 | cfg->name = "FSL_SDHC"; |
Simon Glass | e7881d8 | 2017-07-29 11:35:31 -0600 | [diff] [blame] | 837 | #if !CONFIG_IS_ENABLED(DM_MMC) |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 838 | cfg->ops = &esdhc_ops; |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 839 | #endif |
Li Yang | 030955c | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 840 | #ifdef CONFIG_SYS_SD_VOLTAGE |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 841 | cfg->voltages = CONFIG_SYS_SD_VOLTAGE; |
Li Yang | 030955c | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 842 | #else |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 843 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; |
Li Yang | 030955c | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 844 | #endif |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 845 | if ((cfg->voltages & voltage_caps) == 0) { |
Li Yang | 030955c | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 846 | printf("voltage not supported by controller\n"); |
| 847 | return -1; |
| 848 | } |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 849 | |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 850 | if (priv->bus_width == 8) |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 851 | cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 852 | else if (priv->bus_width == 4) |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 853 | cfg->host_caps = MMC_MODE_4BIT; |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 854 | |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 855 | cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; |
Volodymyr Riazantsev | 0e1bf61 | 2015-01-20 10:16:44 -0500 | [diff] [blame] | 856 | #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 857 | cfg->host_caps |= MMC_MODE_DDR_52MHz; |
Volodymyr Riazantsev | 0e1bf61 | 2015-01-20 10:16:44 -0500 | [diff] [blame] | 858 | #endif |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 859 | |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 860 | if (priv->bus_width > 0) { |
| 861 | if (priv->bus_width < 8) |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 862 | cfg->host_caps &= ~MMC_MODE_8BIT; |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 863 | if (priv->bus_width < 4) |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 864 | cfg->host_caps &= ~MMC_MODE_4BIT; |
Abbas Raza | aad4659 | 2013-03-25 09:13:34 +0000 | [diff] [blame] | 865 | } |
| 866 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 867 | if (caps & ESDHC_HOSTCAPBLT_HSS) |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 868 | cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 869 | |
Haijun.Zhang | d47e3d2 | 2014-01-10 13:52:18 +0800 | [diff] [blame] | 870 | #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK |
| 871 | if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 872 | cfg->host_caps &= ~MMC_MODE_8BIT; |
Haijun.Zhang | d47e3d2 | 2014-01-10 13:52:18 +0800 | [diff] [blame] | 873 | #endif |
| 874 | |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 875 | cfg->f_min = 400000; |
| 876 | cfg->f_max = min(priv->sdhc_clk, (u32)52000000); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 877 | |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 878 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
Pantelis Antoniou | 93bfd61 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 879 | |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 880 | return 0; |
| 881 | } |
| 882 | |
Simon Glass | 5248930 | 2017-07-29 11:35:28 -0600 | [diff] [blame] | 883 | #if !CONFIG_IS_ENABLED(DM_MMC) |
Jagan Teki | 2e87c44 | 2017-05-12 17:18:20 +0530 | [diff] [blame] | 884 | static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, |
| 885 | struct fsl_esdhc_priv *priv) |
| 886 | { |
| 887 | if (!cfg || !priv) |
| 888 | return -EINVAL; |
| 889 | |
| 890 | priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); |
| 891 | priv->bus_width = cfg->max_bus_width; |
| 892 | priv->sdhc_clk = cfg->sdhc_clk; |
| 893 | priv->wp_enable = cfg->wp_enable; |
Peng Fan | 32a9179 | 2017-06-12 17:50:53 +0800 | [diff] [blame] | 894 | priv->vs18_enable = cfg->vs18_enable; |
Jagan Teki | 2e87c44 | 2017-05-12 17:18:20 +0530 | [diff] [blame] | 895 | |
| 896 | return 0; |
| 897 | }; |
| 898 | |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 899 | int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) |
| 900 | { |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 901 | struct fsl_esdhc_plat *plat; |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 902 | struct fsl_esdhc_priv *priv; |
Simon Glass | d6eb25e | 2017-07-29 11:35:22 -0600 | [diff] [blame] | 903 | struct mmc *mmc; |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 904 | int ret; |
| 905 | |
| 906 | if (!cfg) |
| 907 | return -EINVAL; |
| 908 | |
| 909 | priv = calloc(sizeof(struct fsl_esdhc_priv), 1); |
| 910 | if (!priv) |
| 911 | return -ENOMEM; |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 912 | plat = calloc(sizeof(struct fsl_esdhc_plat), 1); |
| 913 | if (!plat) { |
| 914 | free(priv); |
| 915 | return -ENOMEM; |
| 916 | } |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 917 | |
| 918 | ret = fsl_esdhc_cfg_to_priv(cfg, priv); |
| 919 | if (ret) { |
| 920 | debug("%s xlate failure\n", __func__); |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 921 | free(plat); |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 922 | free(priv); |
| 923 | return ret; |
| 924 | } |
| 925 | |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 926 | ret = fsl_esdhc_init(priv, plat); |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 927 | if (ret) { |
| 928 | debug("%s init failure\n", __func__); |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 929 | free(plat); |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 930 | free(priv); |
| 931 | return ret; |
| 932 | } |
| 933 | |
Simon Glass | d6eb25e | 2017-07-29 11:35:22 -0600 | [diff] [blame] | 934 | mmc = mmc_create(&plat->cfg, priv); |
| 935 | if (!mmc) |
| 936 | return -EIO; |
| 937 | |
| 938 | priv->mmc = mmc; |
| 939 | |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 940 | return 0; |
| 941 | } |
| 942 | |
| 943 | int fsl_esdhc_mmc_init(bd_t *bis) |
| 944 | { |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 945 | struct fsl_esdhc_cfg *cfg; |
| 946 | |
Fabio Estevam | 88227a1 | 2012-12-27 08:51:08 +0000 | [diff] [blame] | 947 | cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 948 | cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; |
Simon Glass | e9adeca | 2012-12-13 20:49:05 +0000 | [diff] [blame] | 949 | cfg->sdhc_clk = gd->arch.sdhc_clk; |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 950 | return fsl_esdhc_initialize(bis, cfg); |
Andy Fleming | 50586ef | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 951 | } |
Jagan Teki | 2e87c44 | 2017-05-12 17:18:20 +0530 | [diff] [blame] | 952 | #endif |
Anton Vorontsov | b33433a | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 953 | |
Yangbo Lu | 5a8dbdc | 2015-04-22 13:57:00 +0800 | [diff] [blame] | 954 | #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT |
| 955 | void mmc_adapter_card_type_ident(void) |
| 956 | { |
| 957 | u8 card_id; |
| 958 | u8 value; |
| 959 | |
| 960 | card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; |
| 961 | gd->arch.sdhc_adapter = card_id; |
| 962 | |
| 963 | switch (card_id) { |
| 964 | case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: |
Yangbo Lu | cdc6955 | 2015-09-17 10:27:12 +0800 | [diff] [blame] | 965 | value = QIXIS_READ(brdcfg[5]); |
| 966 | value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); |
| 967 | QIXIS_WRITE(brdcfg[5], value); |
Yangbo Lu | 5a8dbdc | 2015-04-22 13:57:00 +0800 | [diff] [blame] | 968 | break; |
| 969 | case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: |
Yangbo Lu | bf50be8 | 2015-09-17 10:27:48 +0800 | [diff] [blame] | 970 | value = QIXIS_READ(pwr_ctl[1]); |
| 971 | value |= QIXIS_EVDD_BY_SDHC_VS; |
| 972 | QIXIS_WRITE(pwr_ctl[1], value); |
Yangbo Lu | 5a8dbdc | 2015-04-22 13:57:00 +0800 | [diff] [blame] | 973 | break; |
| 974 | case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: |
| 975 | value = QIXIS_READ(brdcfg[5]); |
| 976 | value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); |
| 977 | QIXIS_WRITE(brdcfg[5], value); |
| 978 | break; |
| 979 | case QIXIS_ESDHC_ADAPTER_TYPE_RSV: |
| 980 | break; |
| 981 | case QIXIS_ESDHC_ADAPTER_TYPE_MMC: |
| 982 | break; |
| 983 | case QIXIS_ESDHC_ADAPTER_TYPE_SD: |
| 984 | break; |
| 985 | case QIXIS_ESDHC_NO_ADAPTER: |
| 986 | break; |
| 987 | default: |
| 988 | break; |
| 989 | } |
| 990 | } |
| 991 | #endif |
| 992 | |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 993 | #ifdef CONFIG_OF_LIBFDT |
Yangbo Lu | fce1e16 | 2017-01-17 10:43:54 +0800 | [diff] [blame] | 994 | __weak int esdhc_status_fixup(void *blob, const char *compat) |
| 995 | { |
| 996 | #ifdef CONFIG_FSL_ESDHC_PIN_MUX |
| 997 | if (!hwconfig("esdhc")) { |
| 998 | do_fixup_by_compat(blob, compat, "status", "disabled", |
| 999 | sizeof("disabled"), 1); |
| 1000 | return 1; |
| 1001 | } |
| 1002 | #endif |
Yangbo Lu | fce1e16 | 2017-01-17 10:43:54 +0800 | [diff] [blame] | 1003 | return 0; |
| 1004 | } |
| 1005 | |
Anton Vorontsov | b33433a | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 1006 | void fdt_fixup_esdhc(void *blob, bd_t *bd) |
| 1007 | { |
| 1008 | const char *compat = "fsl,esdhc"; |
Anton Vorontsov | b33433a | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 1009 | |
Yangbo Lu | fce1e16 | 2017-01-17 10:43:54 +0800 | [diff] [blame] | 1010 | if (esdhc_status_fixup(blob, compat)) |
Chenhui Zhao | a6da8b8 | 2011-01-04 17:23:05 +0800 | [diff] [blame] | 1011 | return; |
Anton Vorontsov | b33433a | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 1012 | |
Yangbo Lu | 2d9ca2c | 2015-04-22 13:57:40 +0800 | [diff] [blame] | 1013 | #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
| 1014 | do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", |
| 1015 | gd->arch.sdhc_clk, 1); |
| 1016 | #else |
Anton Vorontsov | b33433a | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 1017 | do_fixup_by_compat_u32(blob, compat, "clock-frequency", |
Simon Glass | e9adeca | 2012-12-13 20:49:05 +0000 | [diff] [blame] | 1018 | gd->arch.sdhc_clk, 1); |
Yangbo Lu | 2d9ca2c | 2015-04-22 13:57:40 +0800 | [diff] [blame] | 1019 | #endif |
Yangbo Lu | 5a8dbdc | 2015-04-22 13:57:00 +0800 | [diff] [blame] | 1020 | #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT |
| 1021 | do_fixup_by_compat_u32(blob, compat, "adapter-type", |
| 1022 | (u32)(gd->arch.sdhc_adapter), 1); |
| 1023 | #endif |
Anton Vorontsov | b33433a | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 1024 | } |
Stefano Babic | c67bee1 | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 1025 | #endif |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1026 | |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 1027 | #if CONFIG_IS_ENABLED(DM_MMC) |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1028 | #include <asm/arch/clock.h> |
Peng Fan | b60f145 | 2017-02-22 16:21:55 +0800 | [diff] [blame] | 1029 | __weak void init_clk_usdhc(u32 index) |
| 1030 | { |
| 1031 | } |
| 1032 | |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1033 | static int fsl_esdhc_probe(struct udevice *dev) |
| 1034 | { |
| 1035 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 1036 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1037 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
York Sun | 9bb272e | 2017-08-08 15:45:13 -0700 | [diff] [blame] | 1038 | #ifdef CONFIG_DM_REGULATOR |
Peng Fan | 4483b7e | 2017-06-12 17:50:54 +0800 | [diff] [blame] | 1039 | struct udevice *vqmmc_dev; |
York Sun | 9bb272e | 2017-08-08 15:45:13 -0700 | [diff] [blame] | 1040 | #endif |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1041 | fdt_addr_t addr; |
| 1042 | unsigned int val; |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 1043 | struct mmc *mmc; |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1044 | int ret; |
| 1045 | |
Simon Glass | 4aac33f | 2017-07-29 11:35:23 -0600 | [diff] [blame] | 1046 | addr = dev_read_addr(dev); |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1047 | if (addr == FDT_ADDR_T_NONE) |
| 1048 | return -EINVAL; |
| 1049 | |
| 1050 | priv->esdhc_regs = (struct fsl_esdhc *)addr; |
| 1051 | priv->dev = dev; |
| 1052 | |
Simon Glass | 4aac33f | 2017-07-29 11:35:23 -0600 | [diff] [blame] | 1053 | val = dev_read_u32_default(dev, "bus-width", -1); |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1054 | if (val == 8) |
| 1055 | priv->bus_width = 8; |
| 1056 | else if (val == 4) |
| 1057 | priv->bus_width = 4; |
| 1058 | else |
| 1059 | priv->bus_width = 1; |
| 1060 | |
Simon Glass | 4aac33f | 2017-07-29 11:35:23 -0600 | [diff] [blame] | 1061 | if (dev_read_bool(dev, "non-removable")) { |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1062 | priv->non_removable = 1; |
| 1063 | } else { |
| 1064 | priv->non_removable = 0; |
Yangbo Lu | fc8048a | 2016-12-07 11:54:30 +0800 | [diff] [blame] | 1065 | #ifdef CONFIG_DM_GPIO |
Simon Glass | 4aac33f | 2017-07-29 11:35:23 -0600 | [diff] [blame] | 1066 | gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, |
| 1067 | GPIOD_IS_IN); |
Yangbo Lu | fc8048a | 2016-12-07 11:54:30 +0800 | [diff] [blame] | 1068 | #endif |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1069 | } |
| 1070 | |
Peng Fan | 1483151 | 2016-06-15 10:53:02 +0800 | [diff] [blame] | 1071 | priv->wp_enable = 1; |
| 1072 | |
Yangbo Lu | fc8048a | 2016-12-07 11:54:30 +0800 | [diff] [blame] | 1073 | #ifdef CONFIG_DM_GPIO |
Simon Glass | 4aac33f | 2017-07-29 11:35:23 -0600 | [diff] [blame] | 1074 | ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, |
| 1075 | GPIOD_IS_IN); |
Peng Fan | 1483151 | 2016-06-15 10:53:02 +0800 | [diff] [blame] | 1076 | if (ret) |
| 1077 | priv->wp_enable = 0; |
Yangbo Lu | fc8048a | 2016-12-07 11:54:30 +0800 | [diff] [blame] | 1078 | #endif |
Peng Fan | 4483b7e | 2017-06-12 17:50:54 +0800 | [diff] [blame] | 1079 | |
| 1080 | priv->vs18_enable = 0; |
| 1081 | |
| 1082 | #ifdef CONFIG_DM_REGULATOR |
| 1083 | /* |
| 1084 | * If emmc I/O has a fixed voltage at 1.8V, this must be provided, |
| 1085 | * otherwise, emmc will work abnormally. |
| 1086 | */ |
| 1087 | ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev); |
| 1088 | if (ret) { |
| 1089 | dev_dbg(dev, "no vqmmc-supply\n"); |
| 1090 | } else { |
| 1091 | ret = regulator_set_enable(vqmmc_dev, true); |
| 1092 | if (ret) { |
| 1093 | dev_err(dev, "fail to enable vqmmc-supply\n"); |
| 1094 | return ret; |
| 1095 | } |
| 1096 | |
| 1097 | if (regulator_get_value(vqmmc_dev) == 1800000) |
| 1098 | priv->vs18_enable = 1; |
| 1099 | } |
| 1100 | #endif |
| 1101 | |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1102 | /* |
| 1103 | * TODO: |
| 1104 | * Because lack of clk driver, if SDHC clk is not enabled, |
| 1105 | * need to enable it first before this driver is invoked. |
| 1106 | * |
| 1107 | * we use MXC_ESDHC_CLK to get clk freq. |
| 1108 | * If one would like to make this function work, |
| 1109 | * the aliases should be provided in dts as this: |
| 1110 | * |
| 1111 | * aliases { |
| 1112 | * mmc0 = &usdhc1; |
| 1113 | * mmc1 = &usdhc2; |
| 1114 | * mmc2 = &usdhc3; |
| 1115 | * mmc3 = &usdhc4; |
| 1116 | * }; |
| 1117 | * Then if your board only supports mmc2 and mmc3, but we can |
| 1118 | * correctly get the seq as 2 and 3, then let mxc_get_clock |
| 1119 | * work as expected. |
| 1120 | */ |
Peng Fan | b60f145 | 2017-02-22 16:21:55 +0800 | [diff] [blame] | 1121 | |
| 1122 | init_clk_usdhc(dev->seq); |
| 1123 | |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1124 | priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); |
| 1125 | if (priv->sdhc_clk <= 0) { |
| 1126 | dev_err(dev, "Unable to get clk for %s\n", dev->name); |
| 1127 | return -EINVAL; |
| 1128 | } |
| 1129 | |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 1130 | ret = fsl_esdhc_init(priv, plat); |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1131 | if (ret) { |
| 1132 | dev_err(dev, "fsl_esdhc_init failure\n"); |
| 1133 | return ret; |
| 1134 | } |
| 1135 | |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 1136 | mmc = &plat->mmc; |
| 1137 | mmc->cfg = &plat->cfg; |
| 1138 | mmc->dev = dev; |
| 1139 | upriv->mmc = mmc; |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1140 | |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 1141 | return esdhc_init_common(priv, mmc); |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1142 | } |
| 1143 | |
Simon Glass | e7881d8 | 2017-07-29 11:35:31 -0600 | [diff] [blame] | 1144 | #if CONFIG_IS_ENABLED(DM_MMC) |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 1145 | static int fsl_esdhc_get_cd(struct udevice *dev) |
| 1146 | { |
| 1147 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 1148 | |
| 1149 | return true; |
| 1150 | return esdhc_getcd_common(priv); |
| 1151 | } |
| 1152 | |
| 1153 | static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, |
| 1154 | struct mmc_data *data) |
| 1155 | { |
| 1156 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); |
| 1157 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 1158 | |
| 1159 | return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data); |
| 1160 | } |
| 1161 | |
| 1162 | static int fsl_esdhc_set_ios(struct udevice *dev) |
| 1163 | { |
| 1164 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); |
| 1165 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 1166 | |
| 1167 | return esdhc_set_ios_common(priv, &plat->mmc); |
| 1168 | } |
| 1169 | |
| 1170 | static const struct dm_mmc_ops fsl_esdhc_ops = { |
| 1171 | .get_cd = fsl_esdhc_get_cd, |
| 1172 | .send_cmd = fsl_esdhc_send_cmd, |
| 1173 | .set_ios = fsl_esdhc_set_ios, |
| 1174 | }; |
| 1175 | #endif |
| 1176 | |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1177 | static const struct udevice_id fsl_esdhc_ids[] = { |
| 1178 | { .compatible = "fsl,imx6ul-usdhc", }, |
| 1179 | { .compatible = "fsl,imx6sx-usdhc", }, |
| 1180 | { .compatible = "fsl,imx6sl-usdhc", }, |
| 1181 | { .compatible = "fsl,imx6q-usdhc", }, |
| 1182 | { .compatible = "fsl,imx7d-usdhc", }, |
Peng Fan | b60f145 | 2017-02-22 16:21:55 +0800 | [diff] [blame] | 1183 | { .compatible = "fsl,imx7ulp-usdhc", }, |
Yangbo Lu | a6473f8 | 2016-12-07 11:54:31 +0800 | [diff] [blame] | 1184 | { .compatible = "fsl,esdhc", }, |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1185 | { /* sentinel */ } |
| 1186 | }; |
| 1187 | |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 1188 | #if CONFIG_IS_ENABLED(BLK) |
| 1189 | static int fsl_esdhc_bind(struct udevice *dev) |
| 1190 | { |
| 1191 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); |
| 1192 | |
| 1193 | return mmc_bind(dev, &plat->mmc, &plat->cfg); |
| 1194 | } |
| 1195 | #endif |
| 1196 | |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1197 | U_BOOT_DRIVER(fsl_esdhc) = { |
| 1198 | .name = "fsl-esdhc-mmc", |
| 1199 | .id = UCLASS_MMC, |
| 1200 | .of_match = fsl_esdhc_ids, |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 1201 | .ops = &fsl_esdhc_ops, |
Simon Glass | 653282b | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 1202 | #if CONFIG_IS_ENABLED(BLK) |
| 1203 | .bind = fsl_esdhc_bind, |
| 1204 | #endif |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1205 | .probe = fsl_esdhc_probe, |
Simon Glass | e88e1d9 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 1206 | .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat), |
Peng Fan | 96f0407 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 1207 | .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), |
| 1208 | }; |
| 1209 | #endif |