commit 9b74dc56fba2b9db39420f81c990284f36d5801f
author Andrew Gabbasov <andrew_gabbasov@mentor.com> Sun Apr 07 23:06:08 2013 +0000
committer Stefano Babic <sbabic@denx.de> Sun Apr 14 11:22:47 2013 +0200
tree de12f8c9a57135903b70ae9895fdc8a97397fee7
parent 54899fc8fe7b33cbe1a7179e39d24e75ababcdc6

fsl_esdhc: Fix DMA transfer completion waiting loop

Rework the waiting for transfer completion loop condition
to continue waiting until both Transfer Complete and DMA End
interrupts occur. Checking of DLA bit in Present State register
looks not needed in addition to interrupts status checking,
so it can be removed from the condition. Also, DMA Error
condition is added to the list of data errors, checked in the loop.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>

drivers/mmc/fsl_esdhc.c

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 737b812..e945c0a 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -397,8 +397,7 @@
 
 			if (irqstat & DATA_ERR)
 				return COMM_ERR;
-		} while (!(irqstat & IRQSTAT_TC) &&
-				(esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
+		} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
 #endif
 		if (data->flags & MMC_DATA_READ)
 			check_and_invalidate_dcache_range(cmd, data);