Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net> |
| 3 | * |
| 4 | * (C) Copyright 2007-2011 |
| 5 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> |
| 6 | * Tom Cubie <tangliang@allwinnertech.com> |
| 7 | * |
| 8 | * Some init for sunxi platform. |
| 9 | * |
| 10 | * SPDX-License-Identifier: GPL-2.0+ |
| 11 | */ |
| 12 | |
| 13 | #include <common.h> |
Daniel Kochmański | a151403 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 14 | #include <mmc.h> |
Hans de Goede | 6620377 | 2014-06-13 22:55:49 +0200 | [diff] [blame] | 15 | #include <i2c.h> |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 16 | #include <serial.h> |
| 17 | #ifdef CONFIG_SPL_BUILD |
| 18 | #include <spl.h> |
| 19 | #endif |
| 20 | #include <asm/gpio.h> |
| 21 | #include <asm/io.h> |
| 22 | #include <asm/arch/clock.h> |
| 23 | #include <asm/arch/gpio.h> |
Bernhard Nortmann | af654d1 | 2015-09-17 18:52:52 +0200 | [diff] [blame] | 24 | #include <asm/arch/spl.h> |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 25 | #include <asm/arch/sys_proto.h> |
| 26 | #include <asm/arch/timer.h> |
Chen-Yu Tsai | 9236984 | 2015-08-25 10:49:19 +0800 | [diff] [blame] | 27 | #include <asm/arch/tzpc.h> |
Daniel Kochmański | a151403 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 28 | #include <asm/arch/mmc.h> |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 29 | |
Ian Campbell | 799aff3 | 2014-07-06 20:03:20 +0100 | [diff] [blame] | 30 | #include <linux/compiler.h> |
| 31 | |
Simon Glass | 942cb0b | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 32 | struct fel_stash { |
| 33 | uint32_t sp; |
| 34 | uint32_t lr; |
Siarhei Siamashka | 840fe95 | 2015-02-16 10:23:59 +0200 | [diff] [blame] | 35 | uint32_t cpsr; |
| 36 | uint32_t sctlr; |
| 37 | uint32_t vbar; |
| 38 | uint32_t cr; |
Simon Glass | 942cb0b | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 39 | }; |
| 40 | |
| 41 | struct fel_stash fel_stash __attribute__((section(".data"))); |
| 42 | |
Simon Glass | f630974 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 43 | static int gpio_init(void) |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 44 | { |
Chen-Yu Tsai | ff2b47f | 2014-10-22 16:47:42 +0800 | [diff] [blame] | 45 | #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) |
Ian Campbell | ed41e62 | 2014-10-24 21:20:47 +0100 | [diff] [blame] | 46 | #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) |
Chen-Yu Tsai | ff2b47f | 2014-10-22 16:47:42 +0800 | [diff] [blame] | 47 | /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ |
| 48 | sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); |
| 49 | sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); |
| 50 | #endif |
Paul Kocialkowski | 487b327 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 51 | #if defined(CONFIG_MACH_SUN8I) |
Chen-Yu Tsai | 6ad8c74 | 2015-06-23 19:57:23 +0800 | [diff] [blame] | 52 | sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); |
| 53 | sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); |
Paul Kocialkowski | 487b327 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 54 | #else |
Chen-Yu Tsai | 6ad8c74 | 2015-06-23 19:57:23 +0800 | [diff] [blame] | 55 | sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0); |
| 56 | sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); |
Paul Kocialkowski | 487b327 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 57 | #endif |
Chen-Yu Tsai | ff2b47f | 2014-10-22 16:47:42 +0800 | [diff] [blame] | 58 | sunxi_gpio_set_pull(SUNXI_GPF(4), 1); |
Ian Campbell | ed41e62 | 2014-10-24 21:20:47 +0100 | [diff] [blame] | 59 | #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)) |
Paul Kocialkowski | 487b327 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 60 | sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0); |
| 61 | sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0); |
Chen-Yu Tsai | ea52094 | 2014-10-03 20:16:21 +0800 | [diff] [blame] | 62 | sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); |
Ian Campbell | ed41e62 | 2014-10-24 21:20:47 +0100 | [diff] [blame] | 63 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I) |
Paul Kocialkowski | 487b327 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 64 | sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0); |
| 65 | sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0); |
Chen-Yu Tsai | ea52094 | 2014-10-03 20:16:21 +0800 | [diff] [blame] | 66 | sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); |
Ian Campbell | ed41e62 | 2014-10-24 21:20:47 +0100 | [diff] [blame] | 67 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I) |
Paul Kocialkowski | 487b327 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 68 | sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0); |
| 69 | sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0); |
Maxime Ripard | 7711539 | 2014-10-03 20:16:28 +0800 | [diff] [blame] | 70 | sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); |
Chen-Yu Tsai | e506889 | 2015-06-23 19:57:25 +0800 | [diff] [blame] | 71 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33) |
| 72 | sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); |
| 73 | sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); |
| 74 | sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); |
Jens Kuske | 1c27b7d | 2015-11-17 15:12:58 +0100 | [diff] [blame] | 75 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3) |
| 76 | sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); |
| 77 | sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); |
| 78 | sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); |
vishnupatekar | d5a3357 | 2015-11-29 01:07:20 +0800 | [diff] [blame] | 79 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) |
| 80 | sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); |
| 81 | sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); |
| 82 | sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); |
Hans de Goede | 1871a8c | 2015-01-13 19:25:06 +0100 | [diff] [blame] | 83 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) |
| 84 | sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); |
| 85 | sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); |
| 86 | sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); |
Ian Campbell | ed41e62 | 2014-10-24 21:20:47 +0100 | [diff] [blame] | 87 | #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) |
Paul Kocialkowski | 487b327 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 88 | sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); |
| 89 | sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); |
Chen-Yu Tsai | ea52094 | 2014-10-03 20:16:21 +0800 | [diff] [blame] | 90 | sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); |
Laurent Itti | 5cd83b11 | 2015-05-05 17:02:00 -0700 | [diff] [blame] | 91 | #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) |
| 92 | sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); |
| 93 | sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); |
| 94 | sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); |
Ian Campbell | ed41e62 | 2014-10-24 21:20:47 +0100 | [diff] [blame] | 95 | #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) |
Paul Kocialkowski | 487b327 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 96 | sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); |
| 97 | sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); |
Chen-Yu Tsai | c757a50 | 2014-10-22 16:47:47 +0800 | [diff] [blame] | 98 | sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); |
Hans de Goede | f84269c | 2014-06-09 11:36:58 +0200 | [diff] [blame] | 99 | #else |
| 100 | #error Unsupported console port number. Please fix pin mux settings in board.c |
| 101 | #endif |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 102 | |
| 103 | return 0; |
| 104 | } |
| 105 | |
Nikita Kiryanov | 36afd45 | 2015-11-08 17:11:49 +0200 | [diff] [blame] | 106 | int spl_board_load_image(void) |
Simon Glass | 942cb0b | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 107 | { |
| 108 | debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr); |
| 109 | return_to_fel(fel_stash.sp, fel_stash.lr); |
Nikita Kiryanov | 36afd45 | 2015-11-08 17:11:49 +0200 | [diff] [blame] | 110 | |
| 111 | return 0; |
Simon Glass | 942cb0b | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 112 | } |
| 113 | |
Hans de Goede | b56f6e2 | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 114 | void s_init(void) |
Simon Glass | f630974 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 115 | { |
Hans de Goede | 5e6bacd | 2015-04-06 20:55:39 +0200 | [diff] [blame] | 116 | #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23 |
Simon Glass | f630974 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 117 | /* Magic (undocmented) value taken from boot0, without this DRAM |
| 118 | * access gets messed up (seems cache related) */ |
| 119 | setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); |
| 120 | #endif |
Hans de Goede | 92bcc6c | 2015-04-06 20:16:36 +0200 | [diff] [blame] | 121 | #if defined CONFIG_MACH_SUN6I || \ |
| 122 | defined CONFIG_MACH_SUN7I || \ |
| 123 | defined CONFIG_MACH_SUN8I |
Simon Glass | f630974 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 124 | /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ |
| 125 | asm volatile( |
| 126 | "mrc p15, 0, r0, c1, c0, 1\n" |
| 127 | "orr r0, r0, #1 << 6\n" |
| 128 | "mcr p15, 0, r0, c1, c0, 1\n"); |
| 129 | #endif |
Chen-Yu Tsai | 5823664 | 2016-01-06 15:13:06 +0800 | [diff] [blame^] | 130 | #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 |
| 131 | /* Enable non-secure access to some peripherals */ |
Chen-Yu Tsai | 9236984 | 2015-08-25 10:49:19 +0800 | [diff] [blame] | 132 | tzpc_init(); |
| 133 | #endif |
Simon Glass | f630974 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 134 | |
| 135 | clock_init(); |
| 136 | timer_init(); |
| 137 | gpio_init(); |
| 138 | i2c_init_board(); |
Hans de Goede | b56f6e2 | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 139 | } |
Simon Glass | f630974 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 140 | |
Hans de Goede | b56f6e2 | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 141 | #ifdef CONFIG_SPL_BUILD |
Daniel Kochmański | a151403 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 142 | DECLARE_GLOBAL_DATA_PTR; |
| 143 | |
Hans de Goede | b56f6e2 | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 144 | /* The sunxi internal brom will try to loader external bootloader |
| 145 | * from mmc0, nand flash, mmc2. |
Hans de Goede | b56f6e2 | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 146 | */ |
| 147 | u32 spl_boot_device(void) |
| 148 | { |
Maxime Ripard | f7d6b3c | 2015-10-15 22:04:06 +0200 | [diff] [blame] | 149 | __maybe_unused struct mmc *mmc0, *mmc1; |
Siarhei Siamashka | 840fe95 | 2015-02-16 10:23:59 +0200 | [diff] [blame] | 150 | /* |
Daniel Kochmański | a151403 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 151 | * When booting from the SD card or NAND memory, the "eGON.BT0" |
| 152 | * signature is expected to be found in memory at the address 0x0004 |
| 153 | * (see the "mksunxiboot" tool, which generates this header). |
Siarhei Siamashka | 840fe95 | 2015-02-16 10:23:59 +0200 | [diff] [blame] | 154 | * |
| 155 | * When booting in the FEL mode over USB, this signature is patched in |
| 156 | * memory and replaced with something else by the 'fel' tool. This other |
| 157 | * signature is selected in such a way, that it can't be present in a |
| 158 | * valid bootable SD card image (because the BROM would refuse to |
| 159 | * execute the SPL in this case). |
| 160 | * |
Daniel Kochmański | a151403 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 161 | * This checks for the signature and if it is not found returns to |
| 162 | * the FEL code in the BROM to wait and receive the main u-boot |
| 163 | * binary over USB. If it is found, it determines where SPL was |
| 164 | * read from. |
Siarhei Siamashka | 840fe95 | 2015-02-16 10:23:59 +0200 | [diff] [blame] | 165 | */ |
Bernhard Nortmann | af654d1 | 2015-09-17 18:52:52 +0200 | [diff] [blame] | 166 | if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */ |
Simon Glass | 942cb0b | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 167 | return BOOT_DEVICE_BOARD; |
Daniel Kochmański | a151403 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 168 | |
| 169 | /* The BROM will try to boot from mmc0 first, so try that first. */ |
Maxime Ripard | f7d6b3c | 2015-10-15 22:04:06 +0200 | [diff] [blame] | 170 | #ifdef CONFIG_MMC |
Daniel Kochmański | a151403 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 171 | mmc_initialize(gd->bd); |
| 172 | mmc0 = find_mmc_device(0); |
| 173 | if (sunxi_mmc_has_egon_boot_signature(mmc0)) |
| 174 | return BOOT_DEVICE_MMC1; |
Maxime Ripard | f7d6b3c | 2015-10-15 22:04:06 +0200 | [diff] [blame] | 175 | #endif |
Daniel Kochmański | a151403 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 176 | |
| 177 | /* Fallback to booting NAND if enabled. */ |
| 178 | if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT)) |
| 179 | return BOOT_DEVICE_NAND; |
| 180 | |
Maxime Ripard | f7d6b3c | 2015-10-15 22:04:06 +0200 | [diff] [blame] | 181 | #ifdef CONFIG_MMC |
Daniel Kochmański | a151403 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 182 | if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) { |
| 183 | mmc1 = find_mmc_device(1); |
Nikita Kiryanov | a1e56cf | 2015-11-08 17:11:54 +0200 | [diff] [blame] | 184 | if (sunxi_mmc_has_egon_boot_signature(mmc1)) |
Daniel Kochmański | a151403 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 185 | return BOOT_DEVICE_MMC2; |
Daniel Kochmański | a151403 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 186 | } |
Maxime Ripard | f7d6b3c | 2015-10-15 22:04:06 +0200 | [diff] [blame] | 187 | #endif |
Daniel Kochmański | a151403 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 188 | |
| 189 | panic("Could not determine boot source\n"); |
| 190 | return -1; /* Never reached */ |
Hans de Goede | b56f6e2 | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 191 | } |
| 192 | |
| 193 | /* No confirmation data available in SPL yet. Hardcode bootmode */ |
| 194 | u32 spl_boot_mode(void) |
| 195 | { |
| 196 | return MMCSD_MODE_RAW; |
| 197 | } |
| 198 | |
| 199 | void board_init_f(ulong dummy) |
| 200 | { |
Hans de Goede | 6d0bdfd | 2015-09-13 12:31:24 +0200 | [diff] [blame] | 201 | spl_init(); |
Simon Glass | f630974 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 202 | preloader_console_init(); |
| 203 | |
| 204 | #ifdef CONFIG_SPL_I2C_SUPPORT |
| 205 | /* Needed early by sunxi_board_init if PMU is enabled */ |
| 206 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
| 207 | #endif |
| 208 | sunxi_board_init(); |
Simon Glass | f630974 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 209 | } |
| 210 | #endif |
| 211 | |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 212 | void reset_cpu(ulong addr) |
| 213 | { |
Hans de Goede | 44d8ae5 | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 214 | #ifdef CONFIG_SUNXI_GEN_SUN4I |
Hans de Goede | c7e79de | 2014-06-09 11:36:56 +0200 | [diff] [blame] | 215 | static const struct sunxi_wdog *wdog = |
| 216 | &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; |
| 217 | |
| 218 | /* Set the watchdog for its shortest interval (.5s) and wait */ |
| 219 | writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); |
| 220 | writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); |
Hans de Goede | ae5de5a | 2014-06-13 22:55:52 +0200 | [diff] [blame] | 221 | |
| 222 | while (1) { |
| 223 | /* sun5i sometimes gets stuck without this */ |
| 224 | writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); |
| 225 | } |
Hans de Goede | 44d8ae5 | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 226 | #endif |
| 227 | #ifdef CONFIG_SUNXI_GEN_SUN6I |
Chen-Yu Tsai | 78c396a | 2014-10-04 20:37:28 +0800 | [diff] [blame] | 228 | static const struct sunxi_wdog *wdog = |
| 229 | ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; |
| 230 | |
| 231 | /* Set the watchdog for its shortest interval (.5s) and wait */ |
| 232 | writel(WDT_CFG_RESET, &wdog->cfg); |
| 233 | writel(WDT_MODE_EN, &wdog->mode); |
| 234 | writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); |
Hans de Goede | fc17543 | 2015-06-14 16:53:15 +0200 | [diff] [blame] | 235 | while (1) { } |
Chen-Yu Tsai | 78c396a | 2014-10-04 20:37:28 +0800 | [diff] [blame] | 236 | #endif |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 237 | } |
| 238 | |
Ian Campbell | cba69ee | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 239 | #ifndef CONFIG_SYS_DCACHE_OFF |
| 240 | void enable_caches(void) |
| 241 | { |
| 242 | /* Enable D-cache. I-cache is already enabled in start.S */ |
| 243 | dcache_enable(); |
| 244 | } |
| 245 | #endif |
Ian Campbell | 5835823 | 2014-05-05 11:52:28 +0100 | [diff] [blame] | 246 | |
| 247 | #ifdef CONFIG_CMD_NET |
| 248 | /* |
| 249 | * Initializes on-chip ethernet controllers. |
| 250 | * to override, implement board_eth_init() |
| 251 | */ |
| 252 | int cpu_eth_init(bd_t *bis) |
| 253 | { |
Ian Campbell | 799aff3 | 2014-07-06 20:03:20 +0100 | [diff] [blame] | 254 | __maybe_unused int rc; |
Ian Campbell | 5835823 | 2014-05-05 11:52:28 +0100 | [diff] [blame] | 255 | |
Hans de Goede | fc70300 | 2014-07-26 17:09:13 +0200 | [diff] [blame] | 256 | #ifdef CONFIG_MACPWR |
Hans de Goede | 8aeed95 | 2015-06-07 15:26:42 +0200 | [diff] [blame] | 257 | gpio_request(CONFIG_MACPWR, "macpwr"); |
Hans de Goede | fc70300 | 2014-07-26 17:09:13 +0200 | [diff] [blame] | 258 | gpio_direction_output(CONFIG_MACPWR, 1); |
| 259 | mdelay(200); |
| 260 | #endif |
| 261 | |
Ian Campbell | 5835823 | 2014-05-05 11:52:28 +0100 | [diff] [blame] | 262 | #ifdef CONFIG_SUNXI_GMAC |
| 263 | rc = sunxi_gmac_initialize(bis); |
| 264 | if (rc < 0) { |
| 265 | printf("sunxi: failed to initialize gmac\n"); |
| 266 | return rc; |
| 267 | } |
| 268 | #endif |
| 269 | |
| 270 | return 0; |
| 271 | } |
| 272 | #endif |