blob: 7dfb7f5340dba4c93ff3ba7a67c33221aef613c7 [file] [log] [blame]
Ian Campbellcba69ee2014-05-05 11:52:26 +01001/*
2 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
3 *
4 * (C) Copyright 2007-2011
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
7 *
8 * Some init for sunxi platform.
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#include <common.h>
Daniel Kochmańskia1514032015-05-29 16:55:42 +020014#include <mmc.h>
Hans de Goede66203772014-06-13 22:55:49 +020015#include <i2c.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010016#include <serial.h>
17#ifdef CONFIG_SPL_BUILD
18#include <spl.h>
19#endif
20#include <asm/gpio.h>
21#include <asm/io.h>
22#include <asm/arch/clock.h>
23#include <asm/arch/gpio.h>
Bernhard Nortmannaf654d12015-09-17 18:52:52 +020024#include <asm/arch/spl.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010025#include <asm/arch/sys_proto.h>
26#include <asm/arch/timer.h>
Chen-Yu Tsai92369842015-08-25 10:49:19 +080027#include <asm/arch/tzpc.h>
Daniel Kochmańskia1514032015-05-29 16:55:42 +020028#include <asm/arch/mmc.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010029
Ian Campbell799aff32014-07-06 20:03:20 +010030#include <linux/compiler.h>
31
Simon Glass942cb0b2015-02-07 10:47:30 -070032struct fel_stash {
33 uint32_t sp;
34 uint32_t lr;
Siarhei Siamashka840fe952015-02-16 10:23:59 +020035 uint32_t cpsr;
36 uint32_t sctlr;
37 uint32_t vbar;
38 uint32_t cr;
Simon Glass942cb0b2015-02-07 10:47:30 -070039};
40
41struct fel_stash fel_stash __attribute__((section(".data")));
42
Simon Glassf6309742014-12-23 12:04:52 -070043static int gpio_init(void)
Ian Campbellcba69ee2014-05-05 11:52:26 +010044{
Chen-Yu Tsaiff2b47f2014-10-22 16:47:42 +080045#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
Ian Campbelled41e622014-10-24 21:20:47 +010046#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
Chen-Yu Tsaiff2b47f2014-10-22 16:47:42 +080047 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
48 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
49 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
50#endif
Paul Kocialkowski487b3272015-03-22 18:12:22 +010051#if defined(CONFIG_MACH_SUN8I)
Chen-Yu Tsai6ad8c742015-06-23 19:57:23 +080052 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
53 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
Paul Kocialkowski487b3272015-03-22 18:12:22 +010054#else
Chen-Yu Tsai6ad8c742015-06-23 19:57:23 +080055 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
56 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
Paul Kocialkowski487b3272015-03-22 18:12:22 +010057#endif
Chen-Yu Tsaiff2b47f2014-10-22 16:47:42 +080058 sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
Ian Campbelled41e622014-10-24 21:20:47 +010059#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
Paul Kocialkowski487b3272015-03-22 18:12:22 +010060 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
61 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
Chen-Yu Tsaiea520942014-10-03 20:16:21 +080062 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
Ian Campbelled41e622014-10-24 21:20:47 +010063#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
Paul Kocialkowski487b3272015-03-22 18:12:22 +010064 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
65 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
Chen-Yu Tsaiea520942014-10-03 20:16:21 +080066 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
Ian Campbelled41e622014-10-24 21:20:47 +010067#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
Paul Kocialkowski487b3272015-03-22 18:12:22 +010068 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
69 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
Maxime Ripard77115392014-10-03 20:16:28 +080070 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
Chen-Yu Tsaie5068892015-06-23 19:57:25 +080071#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
72 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
73 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
74 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
Jens Kuske1c27b7d2015-11-17 15:12:58 +010075#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
76 sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
77 sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
78 sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
vishnupatekard5a33572015-11-29 01:07:20 +080079#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
80 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
81 sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
82 sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
Hans de Goede1871a8c2015-01-13 19:25:06 +010083#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
84 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
85 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
86 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
Ian Campbelled41e622014-10-24 21:20:47 +010087#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
Paul Kocialkowski487b3272015-03-22 18:12:22 +010088 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
89 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
Chen-Yu Tsaiea520942014-10-03 20:16:21 +080090 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
Laurent Itti5cd83b112015-05-05 17:02:00 -070091#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
92 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
93 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
94 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
Ian Campbelled41e622014-10-24 21:20:47 +010095#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
Paul Kocialkowski487b3272015-03-22 18:12:22 +010096 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
97 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
Chen-Yu Tsaic757a502014-10-22 16:47:47 +080098 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
Hans de Goedef84269c2014-06-09 11:36:58 +020099#else
100#error Unsupported console port number. Please fix pin mux settings in board.c
101#endif
Ian Campbellcba69ee2014-05-05 11:52:26 +0100102
103 return 0;
104}
105
Nikita Kiryanov36afd452015-11-08 17:11:49 +0200106int spl_board_load_image(void)
Simon Glass942cb0b2015-02-07 10:47:30 -0700107{
108 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
109 return_to_fel(fel_stash.sp, fel_stash.lr);
Nikita Kiryanov36afd452015-11-08 17:11:49 +0200110
111 return 0;
Simon Glass942cb0b2015-02-07 10:47:30 -0700112}
113
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100114void s_init(void)
Simon Glassf6309742014-12-23 12:04:52 -0700115{
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200116#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
Simon Glassf6309742014-12-23 12:04:52 -0700117 /* Magic (undocmented) value taken from boot0, without this DRAM
118 * access gets messed up (seems cache related) */
119 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
120#endif
Hans de Goede92bcc6c2015-04-06 20:16:36 +0200121#if defined CONFIG_MACH_SUN6I || \
122 defined CONFIG_MACH_SUN7I || \
123 defined CONFIG_MACH_SUN8I
Simon Glassf6309742014-12-23 12:04:52 -0700124 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
125 asm volatile(
126 "mrc p15, 0, r0, c1, c0, 1\n"
127 "orr r0, r0, #1 << 6\n"
128 "mcr p15, 0, r0, c1, c0, 1\n");
129#endif
Chen-Yu Tsai92369842015-08-25 10:49:19 +0800130#if defined CONFIG_MACH_SUN6I
131 /* Enable non-secure access to the RTC */
132 tzpc_init();
133#endif
Simon Glassf6309742014-12-23 12:04:52 -0700134
135 clock_init();
136 timer_init();
137 gpio_init();
138 i2c_init_board();
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100139}
Simon Glassf6309742014-12-23 12:04:52 -0700140
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100141#ifdef CONFIG_SPL_BUILD
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200142DECLARE_GLOBAL_DATA_PTR;
143
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100144/* The sunxi internal brom will try to loader external bootloader
145 * from mmc0, nand flash, mmc2.
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100146 */
147u32 spl_boot_device(void)
148{
Maxime Ripardf7d6b3c2015-10-15 22:04:06 +0200149 __maybe_unused struct mmc *mmc0, *mmc1;
Siarhei Siamashka840fe952015-02-16 10:23:59 +0200150 /*
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200151 * When booting from the SD card or NAND memory, the "eGON.BT0"
152 * signature is expected to be found in memory at the address 0x0004
153 * (see the "mksunxiboot" tool, which generates this header).
Siarhei Siamashka840fe952015-02-16 10:23:59 +0200154 *
155 * When booting in the FEL mode over USB, this signature is patched in
156 * memory and replaced with something else by the 'fel' tool. This other
157 * signature is selected in such a way, that it can't be present in a
158 * valid bootable SD card image (because the BROM would refuse to
159 * execute the SPL in this case).
160 *
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200161 * This checks for the signature and if it is not found returns to
162 * the FEL code in the BROM to wait and receive the main u-boot
163 * binary over USB. If it is found, it determines where SPL was
164 * read from.
Siarhei Siamashka840fe952015-02-16 10:23:59 +0200165 */
Bernhard Nortmannaf654d12015-09-17 18:52:52 +0200166 if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
Simon Glass942cb0b2015-02-07 10:47:30 -0700167 return BOOT_DEVICE_BOARD;
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200168
169 /* The BROM will try to boot from mmc0 first, so try that first. */
Maxime Ripardf7d6b3c2015-10-15 22:04:06 +0200170#ifdef CONFIG_MMC
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200171 mmc_initialize(gd->bd);
172 mmc0 = find_mmc_device(0);
173 if (sunxi_mmc_has_egon_boot_signature(mmc0))
174 return BOOT_DEVICE_MMC1;
Maxime Ripardf7d6b3c2015-10-15 22:04:06 +0200175#endif
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200176
177 /* Fallback to booting NAND if enabled. */
178 if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT))
179 return BOOT_DEVICE_NAND;
180
Maxime Ripardf7d6b3c2015-10-15 22:04:06 +0200181#ifdef CONFIG_MMC
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200182 if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) {
183 mmc1 = find_mmc_device(1);
Nikita Kiryanova1e56cf2015-11-08 17:11:54 +0200184 if (sunxi_mmc_has_egon_boot_signature(mmc1))
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200185 return BOOT_DEVICE_MMC2;
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200186 }
Maxime Ripardf7d6b3c2015-10-15 22:04:06 +0200187#endif
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200188
189 panic("Could not determine boot source\n");
190 return -1; /* Never reached */
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100191}
192
193/* No confirmation data available in SPL yet. Hardcode bootmode */
194u32 spl_boot_mode(void)
195{
196 return MMCSD_MODE_RAW;
197}
198
199void board_init_f(ulong dummy)
200{
Hans de Goede6d0bdfd2015-09-13 12:31:24 +0200201 spl_init();
Simon Glassf6309742014-12-23 12:04:52 -0700202 preloader_console_init();
203
204#ifdef CONFIG_SPL_I2C_SUPPORT
205 /* Needed early by sunxi_board_init if PMU is enabled */
206 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
207#endif
208 sunxi_board_init();
Simon Glassf6309742014-12-23 12:04:52 -0700209}
210#endif
211
Ian Campbellcba69ee2014-05-05 11:52:26 +0100212void reset_cpu(ulong addr)
213{
Hans de Goede44d8ae52015-04-06 20:33:34 +0200214#ifdef CONFIG_SUNXI_GEN_SUN4I
Hans de Goedec7e79de2014-06-09 11:36:56 +0200215 static const struct sunxi_wdog *wdog =
216 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
217
218 /* Set the watchdog for its shortest interval (.5s) and wait */
219 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
220 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
Hans de Goedeae5de5a2014-06-13 22:55:52 +0200221
222 while (1) {
223 /* sun5i sometimes gets stuck without this */
224 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
225 }
Hans de Goede44d8ae52015-04-06 20:33:34 +0200226#endif
227#ifdef CONFIG_SUNXI_GEN_SUN6I
Chen-Yu Tsai78c396a2014-10-04 20:37:28 +0800228 static const struct sunxi_wdog *wdog =
229 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
230
231 /* Set the watchdog for its shortest interval (.5s) and wait */
232 writel(WDT_CFG_RESET, &wdog->cfg);
233 writel(WDT_MODE_EN, &wdog->mode);
234 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
Hans de Goedefc175432015-06-14 16:53:15 +0200235 while (1) { }
Chen-Yu Tsai78c396a2014-10-04 20:37:28 +0800236#endif
Ian Campbellcba69ee2014-05-05 11:52:26 +0100237}
238
Ian Campbellcba69ee2014-05-05 11:52:26 +0100239#ifndef CONFIG_SYS_DCACHE_OFF
240void enable_caches(void)
241{
242 /* Enable D-cache. I-cache is already enabled in start.S */
243 dcache_enable();
244}
245#endif
Ian Campbell58358232014-05-05 11:52:28 +0100246
247#ifdef CONFIG_CMD_NET
248/*
249 * Initializes on-chip ethernet controllers.
250 * to override, implement board_eth_init()
251 */
252int cpu_eth_init(bd_t *bis)
253{
Ian Campbell799aff32014-07-06 20:03:20 +0100254 __maybe_unused int rc;
Ian Campbell58358232014-05-05 11:52:28 +0100255
Hans de Goedefc703002014-07-26 17:09:13 +0200256#ifdef CONFIG_MACPWR
Hans de Goede8aeed952015-06-07 15:26:42 +0200257 gpio_request(CONFIG_MACPWR, "macpwr");
Hans de Goedefc703002014-07-26 17:09:13 +0200258 gpio_direction_output(CONFIG_MACPWR, 1);
259 mdelay(200);
260#endif
261
Ian Campbell58358232014-05-05 11:52:28 +0100262#ifdef CONFIG_SUNXI_GMAC
263 rc = sunxi_gmac_initialize(bis);
264 if (rc < 0) {
265 printf("sunxi: failed to initialize gmac\n");
266 return rc;
267 }
268#endif
269
270 return 0;
271}
272#endif